49 	uint32_t value = 0, regval;  in hal_tx_set_dscp_tid_map_5332()  local
65 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_5332()
66 	regval |=  in hal_tx_set_dscp_tid_map_5332()
70 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_5332()
88 		regval = *(uint32_t *)(val + i);  in hal_tx_set_dscp_tid_map_5332()
90 			      (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_set_dscp_tid_map_5332()
95 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_5332()
96 	regval &=  in hal_tx_set_dscp_tid_map_5332()
99 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_5332()
117 	uint32_t regval;  in hal_tx_update_dscp_tid_5332()  local
149 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_5332()
150 	regval |=  in hal_tx_update_dscp_tid_5332()
153 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_5332()
155 	regval = HAL_REG_READ(soc, addr);  in hal_tx_update_dscp_tid_5332()
158 		regval &= (~0) >> start_bits;  in hal_tx_update_dscp_tid_5332()
160 		regval &= ~(7 << start_index);  in hal_tx_update_dscp_tid_5332()
162 	regval |= start_value;  in hal_tx_update_dscp_tid_5332()
164 	HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_update_dscp_tid_5332()
167 		regval = HAL_REG_READ(soc, addr1);  in hal_tx_update_dscp_tid_5332()
168 		regval &= (~0) << end_bits;  in hal_tx_update_dscp_tid_5332()
169 		regval |= end_value;  in hal_tx_update_dscp_tid_5332()
171 		HAL_REG_WRITE(soc, addr1, (regval &  in hal_tx_update_dscp_tid_5332()
176 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_5332()
177 	regval &=  in hal_tx_update_dscp_tid_5332()
179 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_5332()