68 	uint32_t value = 0, regval;  in hal_tx_set_dscp_tid_map_8074v2()  local
82 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_8074v2()
83 	regval |=  in hal_tx_set_dscp_tid_map_8074v2()
86 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_8074v2()
104 		regval = *(uint32_t *)(val + i);  in hal_tx_set_dscp_tid_map_8074v2()
106 			      (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_set_dscp_tid_map_8074v2()
111 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_8074v2()
112 	regval &=  in hal_tx_set_dscp_tid_map_8074v2()
115 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_8074v2()
133 	uint32_t regval;  in hal_tx_update_dscp_tid_8074v2()  local
164 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_8074v2()
165 	regval |=  in hal_tx_update_dscp_tid_8074v2()
168 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_8074v2()
170 	regval = HAL_REG_READ(soc, addr);  in hal_tx_update_dscp_tid_8074v2()
173 		regval &= (regmask >> start_bits);  in hal_tx_update_dscp_tid_8074v2()
175 		regval &= ~(7 << start_index);  in hal_tx_update_dscp_tid_8074v2()
177 	regval |= start_value;  in hal_tx_update_dscp_tid_8074v2()
179 	HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_update_dscp_tid_8074v2()
182 		regval = HAL_REG_READ(soc, addr1);  in hal_tx_update_dscp_tid_8074v2()
183 		regval &= (~0) << end_bits;  in hal_tx_update_dscp_tid_8074v2()
184 		regval |= end_value;  in hal_tx_update_dscp_tid_8074v2()
186 		HAL_REG_WRITE(soc, addr1, (regval &  in hal_tx_update_dscp_tid_8074v2()
191 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_8074v2()
192 	regval &=  in hal_tx_update_dscp_tid_8074v2()
194 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_8074v2()