64 	uint32_t value = 0, regval;  in hal_tx_set_dscp_tid_map_6122()  local
78 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_6122()
79 	regval |=  in hal_tx_set_dscp_tid_map_6122()
82 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_6122()
100 		regval = *(uint32_t *)(val + i);  in hal_tx_set_dscp_tid_map_6122()
102 			      (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_set_dscp_tid_map_6122()
107 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_6122()
108 	regval &=  in hal_tx_set_dscp_tid_map_6122()
111 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_6122()
129 	uint32_t regval;  in hal_tx_update_dscp_tid_6122()  local
161 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_6122()
162 	regval |=  in hal_tx_update_dscp_tid_6122()
165 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_6122()
167 	regval = HAL_REG_READ(soc, addr);  in hal_tx_update_dscp_tid_6122()
170 		regval &= (~0) >> start_bits;  in hal_tx_update_dscp_tid_6122()
172 		regval &= ~(7 << start_index);  in hal_tx_update_dscp_tid_6122()
174 	regval |= start_value;  in hal_tx_update_dscp_tid_6122()
176 	HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_update_dscp_tid_6122()
179 		regval = HAL_REG_READ(soc, addr1);  in hal_tx_update_dscp_tid_6122()
180 		regval &= (~0) << end_bits;  in hal_tx_update_dscp_tid_6122()
181 		regval |= end_value;  in hal_tx_update_dscp_tid_6122()
183 		HAL_REG_WRITE(soc, addr1, (regval &  in hal_tx_update_dscp_tid_6122()
188 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_6122()
189 	regval &=  in hal_tx_update_dscp_tid_6122()
191 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_6122()