221 	uint32_t reg_val = 0;  in hal_tx_config_rbm_mapping_be_6432()  local
243 	reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<  in hal_tx_config_rbm_mapping_be_6432()
247 	HAL_REG_WRITE(hal_soc, reg_addr, reg_val);  in hal_tx_config_rbm_mapping_be_6432()
519 	uint32_t reg_addr, reg_val = 0;  in hal_tx_set_ppe_cmn_config_6432()  local
523 	reg_val = HAL_REG_READ(soc, reg_addr);  in hal_tx_set_ppe_cmn_config_6432()
525 	reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK;  in hal_tx_set_ppe_cmn_config_6432()
526 	reg_val |=  in hal_tx_set_ppe_cmn_config_6432()
531 	reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK;  in hal_tx_set_ppe_cmn_config_6432()
532 	reg_val |=  in hal_tx_set_ppe_cmn_config_6432()
537 	reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK;  in hal_tx_set_ppe_cmn_config_6432()
538 	reg_val |=  in hal_tx_set_ppe_cmn_config_6432()
543 	reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK;  in hal_tx_set_ppe_cmn_config_6432()
544 	reg_val |=  in hal_tx_set_ppe_cmn_config_6432()
549 	HAL_REG_WRITE(soc, reg_addr, reg_val);  in hal_tx_set_ppe_cmn_config_6432()
610 	uint32_t reg_addr, reg_val = 0;  in hal_tx_set_ppe_pri2tid_map_6432()  local
619 	reg_val |= val;  in hal_tx_set_ppe_pri2tid_map_6432()
620 	HAL_REG_WRITE(soc, reg_addr, reg_val);  in hal_tx_set_ppe_pri2tid_map_6432()
637 	uint32_t reg_addr, reg_val = 0;  in hal_tx_enable_pri2tid_map_6432()  local
645 	reg_val = HAL_REG_READ(soc, reg_addr);  in hal_tx_enable_pri2tid_map_6432()
647 	reg_val &=  in hal_tx_enable_pri2tid_map_6432()
650 	reg_val |=  in hal_tx_enable_pri2tid_map_6432()
655 	HAL_REG_WRITE(soc, reg_addr, reg_val);  in hal_tx_enable_pri2tid_map_6432()
672 	uint32_t reg_addr, reg_val = 0, mask, shift;  in hal_tx_update_ppe_pri2tid_6432()  local
699 	reg_val = HAL_REG_READ(soc, reg_addr);  in hal_tx_update_ppe_pri2tid_6432()
700 	reg_val &= ~mask;  in hal_tx_update_ppe_pri2tid_6432()
701 	reg_val |= (pri << shift) & mask;  in hal_tx_update_ppe_pri2tid_6432()
703 	HAL_REG_WRITE(soc, reg_addr, reg_val);  in hal_tx_update_ppe_pri2tid_6432()
716 	uint32_t reg_addr, reg_val = 0, i;  in hal_tx_dump_ppe_vp_entry_6432()  local
723 		reg_val = HAL_REG_READ(soc, reg_addr);  in hal_tx_dump_ppe_vp_entry_6432()
724 		hal_verbose_debug("%d: 0x%x\n", i, reg_val);  in hal_tx_dump_ppe_vp_entry_6432()