64 	uint32_t value = 0, regval;  in hal_tx_set_dscp_tid_map_6432()  local
80 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_6432()
81 	regval |=  in hal_tx_set_dscp_tid_map_6432()
85 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_6432()
103 		regval = *(uint32_t *)(val + i);  in hal_tx_set_dscp_tid_map_6432()
105 				(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_set_dscp_tid_map_6432()
110 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_6432()
111 	regval &=  in hal_tx_set_dscp_tid_map_6432()
114 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_6432()
132 	uint32_t regval;  in hal_tx_update_dscp_tid_6432()  local
164 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_6432()
165 	regval |=  in hal_tx_update_dscp_tid_6432()
168 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_6432()
170 	regval = HAL_REG_READ(soc, addr);  in hal_tx_update_dscp_tid_6432()
173 		regval &= (~0) >> start_bits;  in hal_tx_update_dscp_tid_6432()
175 		regval &= ~(7 << start_index);  in hal_tx_update_dscp_tid_6432()
177 	regval |= start_value;  in hal_tx_update_dscp_tid_6432()
179 	HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_update_dscp_tid_6432()
182 		regval = HAL_REG_READ(soc, addr1);  in hal_tx_update_dscp_tid_6432()
183 		regval &= (~0) << end_bits;  in hal_tx_update_dscp_tid_6432()
184 		regval |= end_value;  in hal_tx_update_dscp_tid_6432()
186 		HAL_REG_WRITE(soc, addr1, (regval &  in hal_tx_update_dscp_tid_6432()
191 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_6432()
192 	regval &=  in hal_tx_update_dscp_tid_6432()
194 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_6432()
749 	uint32_t regval;  in hal_tx_ppe2tcl_ring_halt_set_6432()  local
756 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_ppe2tcl_ring_halt_set_6432()
757 	regval |=  in hal_tx_ppe2tcl_ring_halt_set_6432()
761 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_ppe2tcl_ring_halt_set_6432()
773 	uint32_t regval;  in hal_tx_ppe2tcl_ring_halt_reset_6432()  local
780 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_ppe2tcl_ring_halt_reset_6432()
781 	regval &= ~(1 <<  in hal_tx_ppe2tcl_ring_halt_reset_6432()
784 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_ppe2tcl_ring_halt_reset_6432()
796 	uint32_t regval;  in hal_tx_ppe2tcl_ring_halt_done_6432()  local
802 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_ppe2tcl_ring_halt_done_6432()
803 	regval &= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT);  in hal_tx_ppe2tcl_ring_halt_done_6432()
805 	return(!!regval);  in hal_tx_ppe2tcl_ring_halt_done_6432()