44 	uint32_t regval;  in hal_tx_ppe2tcl_ring_halt_get_9224()  local
51 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_ppe2tcl_ring_halt_get_9224()
52 	return (regval &  in hal_tx_ppe2tcl_ring_halt_get_9224()
66 	uint32_t regval;  in hal_tx_ppe2tcl_ring_halt_set_9224()  local
73 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_ppe2tcl_ring_halt_set_9224()
74 	regval |=  in hal_tx_ppe2tcl_ring_halt_set_9224()
78 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_ppe2tcl_ring_halt_set_9224()
91 	uint32_t regval;  in hal_tx_ppe2tcl_ring_halt_reset_9224()  local
98 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_ppe2tcl_ring_halt_reset_9224()
99 	regval &= ~(1 <<  in hal_tx_ppe2tcl_ring_halt_reset_9224()
102 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_ppe2tcl_ring_halt_reset_9224()
115 	uint32_t regval;  in hal_tx_ppe2tcl_ring_halt_done_9224()  local
121 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_ppe2tcl_ring_halt_done_9224()
122 	regval &= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT);  in hal_tx_ppe2tcl_ring_halt_done_9224()
124 	return(!!regval);  in hal_tx_ppe2tcl_ring_halt_done_9224()
143 	uint32_t value = 0, regval;  in hal_tx_set_dscp_tid_map_9224()  local
159 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_9224()
160 	regval |=  in hal_tx_set_dscp_tid_map_9224()
164 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_9224()
182 		regval = *(uint32_t *)(val + i);  in hal_tx_set_dscp_tid_map_9224()
184 			      (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_set_dscp_tid_map_9224()
189 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_set_dscp_tid_map_9224()
190 	regval &=  in hal_tx_set_dscp_tid_map_9224()
193 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_set_dscp_tid_map_9224()
211 	uint32_t regval;  in hal_tx_update_dscp_tid_9224()  local
243 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_9224()
244 	regval |=  in hal_tx_update_dscp_tid_9224()
247 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_9224()
249 	regval = HAL_REG_READ(soc, addr);  in hal_tx_update_dscp_tid_9224()
252 		regval &= (~0) >> start_bits;  in hal_tx_update_dscp_tid_9224()
254 		regval &= ~(7 << start_index);  in hal_tx_update_dscp_tid_9224()
256 	regval |= start_value;  in hal_tx_update_dscp_tid_9224()
258 	HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));  in hal_tx_update_dscp_tid_9224()
261 		regval = HAL_REG_READ(soc, addr1);  in hal_tx_update_dscp_tid_9224()
262 		regval &= (~0) << end_bits;  in hal_tx_update_dscp_tid_9224()
263 		regval |= end_value;  in hal_tx_update_dscp_tid_9224()
265 		HAL_REG_WRITE(soc, addr1, (regval &  in hal_tx_update_dscp_tid_9224()
270 	regval = HAL_REG_READ(soc, cmn_reg_addr);  in hal_tx_update_dscp_tid_9224()
271 	regval &=  in hal_tx_update_dscp_tid_9224()
273 	HAL_REG_WRITE(soc, cmn_reg_addr, regval);  in hal_tx_update_dscp_tid_9224()