Lines Matching defs:ce_reg_def
618 struct ce_reg_def { struct
620 uint32_t d_DST_WR_INDEX_ADDRESS;
621 uint32_t d_SRC_WATERMARK_ADDRESS;
622 uint32_t d_SRC_WATERMARK_LOW_MASK;
623 uint32_t d_SRC_WATERMARK_HIGH_MASK;
624 uint32_t d_DST_WATERMARK_LOW_MASK;
625 uint32_t d_DST_WATERMARK_HIGH_MASK;
626 uint32_t d_CURRENT_SRRI_ADDRESS;
627 uint32_t d_CURRENT_DRRI_ADDRESS;
628 uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK;
629 uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK;
630 uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK;
631 uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK;
632 uint32_t d_HOST_IS_ADDRESS;
633 uint32_t d_MISC_IS_ADDRESS;
634 uint32_t d_HOST_IS_COPY_COMPLETE_MASK;
635 uint32_t d_CE_WRAPPER_BASE_ADDRESS;
636 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS;
637 uint32_t d_CE_DDR_ADDRESS_FOR_RRI_LOW;
638 uint32_t d_CE_DDR_ADDRESS_FOR_RRI_HIGH;
639 uint32_t d_HOST_IE_ADDRESS;
640 uint32_t d_HOST_IE_ADDRESS_2;
641 uint32_t d_HOST_IE_COPY_COMPLETE_MASK;
642 uint32_t d_HOST_IE_SRC_TIMER_BATCH_MASK;
643 uint32_t d_HOST_IE_DST_TIMER_BATCH_MASK;
644 uint32_t d_SR_BA_ADDRESS;
645 uint32_t d_SR_BA_ADDRESS_HIGH;
646 uint32_t d_SR_SIZE_ADDRESS;
647 uint32_t d_CE_CTRL1_ADDRESS;
648 uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK;
649 uint32_t d_DR_BA_ADDRESS;
650 uint32_t d_DR_BA_ADDRESS_HIGH;
651 uint32_t d_DR_SIZE_ADDRESS;
652 uint32_t d_CE_CMD_REGISTER;
653 uint32_t d_CE_MSI_ADDRESS;
654 uint32_t d_CE_MSI_ADDRESS_HIGH;
655 uint32_t d_CE_MSI_DATA;
656 uint32_t d_CE_MSI_ENABLE_BIT;
657 uint32_t d_MISC_IE_ADDRESS;
658 uint32_t d_MISC_IS_AXI_ERR_MASK;
659 uint32_t d_MISC_IS_DST_ADDR_ERR_MASK;
660 uint32_t d_MISC_IS_SRC_LEN_ERR_MASK;
661 uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK;
662 uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK;
663 uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK;
664 uint32_t d_SRC_WATERMARK_LOW_LSB;
665 uint32_t d_SRC_WATERMARK_HIGH_LSB;
666 uint32_t d_DST_WATERMARK_LOW_LSB;
667 uint32_t d_DST_WATERMARK_HIGH_LSB;
668 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK;
669 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB;
670 uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB;
671 uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK;
672 uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK;
673 uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB;
674 uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB;
675 uint32_t d_CE_CTRL1_IDX_UPD_EN_MASK;
676 uint32_t d_CE_WRAPPER_DEBUG_OFFSET;
677 uint32_t d_CE_WRAPPER_DEBUG_SEL_MSB;
678 uint32_t d_CE_WRAPPER_DEBUG_SEL_LSB;
679 uint32_t d_CE_WRAPPER_DEBUG_SEL_MASK;
680 uint32_t d_CE_DEBUG_OFFSET;
681 uint32_t d_CE_DEBUG_SEL_MSB;
682 uint32_t d_CE_DEBUG_SEL_LSB;
683 uint32_t d_CE_DEBUG_SEL_MASK;
684 uint32_t d_CE0_BASE_ADDRESS;
685 uint32_t d_CE1_BASE_ADDRESS;
686 uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES;
687 uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS;
688 uint32_t d_HOST_IE_ADDRESS_3;
689 uint32_t d_HOST_IE_REG1_CE_LSB;
690 uint32_t d_HOST_IE_REG2_CE_LSB;
691 uint32_t d_HOST_IE_REG3_CE_LSB;
692 uint32_t d_HOST_CE_ADDRESS;
693 uint32_t d_HOST_CMEM_ADDRESS;
694 uint32_t d_PMM_SCRATCH_BASE;
695 uint32_t d_CE_SRC_BATCH_TIMER_THRESH_MASK;
696 uint32_t d_CE_SRC_BATCH_COUNTER_THRESH_MASK;
697 uint32_t d_CE_SRC_BATCH_TIMER_THRESH_LSB;
698 uint32_t d_CE_SRC_BATCH_COUNTER_THRESH_LSB;
699 uint32_t d_CE_DST_BATCH_TIMER_THRESH_MASK;
700 uint32_t d_CE_DST_BATCH_COUNTER_THRESH_MASK;
701 uint32_t d_CE_DST_BATCH_TIMER_THRESH_LSB;
702 uint32_t d_CE_DST_BATCH_COUNTER_THRESH_LSB;
703 uint32_t d_CE_SRC_BATCH_TIMER_INT_SETUP;
704 uint32_t d_CE_DST_BATCH_TIMER_INT_SETUP;