Lines Matching defs:hostdef_s
311 struct hostdef_s { struct
312 uint32_t d_INT_STATUS_ENABLE_ERROR_LSB;
313 uint32_t d_INT_STATUS_ENABLE_ERROR_MASK;
314 uint32_t d_INT_STATUS_ENABLE_CPU_LSB;
315 uint32_t d_INT_STATUS_ENABLE_CPU_MASK;
316 uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB;
317 uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK;
318 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
319 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
320 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
321 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
322 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
323 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
324 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
325 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
326 uint32_t d_INT_STATUS_ENABLE_ADDRESS;
327 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB;
328 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK;
329 uint32_t d_HOST_INT_STATUS_ADDRESS;
330 uint32_t d_CPU_INT_STATUS_ADDRESS;
331 uint32_t d_ERROR_INT_STATUS_ADDRESS;
332 uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK;
333 uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB;
334 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
335 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
336 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
337 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
338 uint32_t d_COUNT_DEC_ADDRESS;
339 uint32_t d_HOST_INT_STATUS_CPU_MASK;
340 uint32_t d_HOST_INT_STATUS_CPU_LSB;
341 uint32_t d_HOST_INT_STATUS_ERROR_MASK;
342 uint32_t d_HOST_INT_STATUS_ERROR_LSB;
343 uint32_t d_HOST_INT_STATUS_COUNTER_MASK;
344 uint32_t d_HOST_INT_STATUS_COUNTER_LSB;
345 uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS;
346 uint32_t d_WINDOW_DATA_ADDRESS;
347 uint32_t d_WINDOW_READ_ADDR_ADDRESS;
348 uint32_t d_WINDOW_WRITE_ADDR_ADDRESS;
349 uint32_t d_SOC_GLOBAL_RESET_ADDRESS;
350 uint32_t d_RTC_STATE_ADDRESS;
351 uint32_t d_RTC_STATE_COLD_RESET_MASK;
352 uint32_t d_PCIE_LOCAL_BASE_ADDRESS;
353 uint32_t d_PCIE_SOC_WAKE_RESET;
354 uint32_t d_PCIE_SOC_WAKE_ADDRESS;
355 uint32_t d_PCIE_SOC_WAKE_V_MASK;
356 uint32_t d_RTC_STATE_V_MASK;
357 uint32_t d_RTC_STATE_V_LSB;
358 uint32_t d_FW_IND_EVENT_PENDING;
359 uint32_t d_FW_IND_INITIALIZED;
360 uint32_t d_FW_IND_HELPER;
361 uint32_t d_RTC_STATE_V_ON;
363 uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK;
364 uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB;
366 uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS;
367 uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK;
368 uint32_t d_SOC_PCIE_BASE_ADDRESS;
369 uint32_t d_MSI_MAGIC_ADR_ADDRESS;
370 uint32_t d_MSI_MAGIC_ADDRESS;
371 uint32_t d_HOST_CE_COUNT;
372 uint32_t d_ENABLE_MSI;
373 uint32_t d_MUX_ID_MASK;
374 uint32_t d_TRANSACTION_ID_MASK;
375 uint32_t d_DESC_DATA_FLAG_MASK;
376 uint32_t d_A_SOC_PCIE_PCIE_BAR0_START;
377 uint32_t d_FW_IND_HOST_READY;