hif/inc/regtable_pcie.h

452 #define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)
453 #define DESC_DATA_FLAG_MASK        (scn->hostdef->d_DESC_DATA_FLAG_MASK)
454 #define MUX_ID_MASK                (scn->hostdef->d_MUX_ID_MASK)
455 #define TRANSACTION_ID_MASK        (scn->hostdef->d_TRANSACTION_ID_MASK)
456 #define HOST_CE_COUNT              (scn->hostdef->d_HOST_CE_COUNT)
457 #define ENABLE_MSI                 (scn->hostdef->d_ENABLE_MSI)
459 	(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
461 	(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
462 #define INT_STATUS_ENABLE_CPU_LSB  (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
463 #define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
465 	(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
467 	(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
469 	(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
471 	(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
473 	(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
475 	(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
477 	(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
479 	(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
481 	(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
483 	(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
485 	(scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
487 	(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
489 	(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
490 #define HOST_INT_STATUS_ADDRESS     (scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
491 #define CPU_INT_STATUS_ADDRESS      (scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
492 #define ERROR_INT_STATUS_ADDRESS    (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
494 	(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
496 	(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
498 	(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
500 	(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
502 	(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
504 	(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
505 #define COUNT_DEC_ADDRESS          (scn->hostdef->d_COUNT_DEC_ADDRESS)
506 #define HOST_INT_STATUS_CPU_MASK   (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
507 #define HOST_INT_STATUS_CPU_LSB    (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
508 #define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
509 #define HOST_INT_STATUS_ERROR_LSB  (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
511 	(scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
513 	(scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
514 #define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
515 #define WINDOW_DATA_ADDRESS        (scn->hostdef->d_WINDOW_DATA_ADDRESS)
516 #define WINDOW_READ_ADDR_ADDRESS   (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
517 #define WINDOW_WRITE_ADDR_ADDRESS  (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
518 #define SOC_GLOBAL_RESET_ADDRESS   (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
519 #define RTC_STATE_ADDRESS          (scn->hostdef->d_RTC_STATE_ADDRESS)
520 #define RTC_STATE_COLD_RESET_MASK  (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
521 #define PCIE_LOCAL_BASE_ADDRESS    (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS)
522 #define PCIE_SOC_WAKE_RESET        (scn->hostdef->d_PCIE_SOC_WAKE_RESET)
523 #define PCIE_SOC_WAKE_ADDRESS      (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS)
524 #define PCIE_SOC_WAKE_V_MASK       (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK)
525 #define RTC_STATE_V_MASK           (scn->hostdef->d_RTC_STATE_V_MASK)
526 #define RTC_STATE_V_LSB            (scn->hostdef->d_RTC_STATE_V_LSB)
527 #define FW_IND_EVENT_PENDING       (scn->hostdef->d_FW_IND_EVENT_PENDING)
528 #define FW_IND_INITIALIZED         (scn->hostdef->d_FW_IND_INITIALIZED)
529 #define FW_IND_HELPER              (scn->hostdef->d_FW_IND_HELPER)
530 #define RTC_STATE_V_ON             (scn->hostdef->d_RTC_STATE_V_ON)
532 #define FW_IND_HOST_READY          (scn->hostdef->d_FW_IND_HOST_READY)
536 	(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
538 	(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)