hif/inc/regtable_pcie.h

25 	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
27 	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1)
29 	(scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER)
31 	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1)
33 	(scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1)
35 	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0)
37 	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1)
39 	(scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA)
41 	(scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2)
45 	(scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK)
47 	(scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER)
49 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS)
51 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS)
53 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS)
55 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS)
57 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS)
59 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS)
61 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS)
63 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS)
64 #define RTC_SOC_BASE_ADDRESS  (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
65 #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
66 #define SYSTEM_SLEEP_OFFSET   (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
68 	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
70 	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
72 	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
73 #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
75 	(scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
76 #define RESET_CONTROL_OFFSET    (scn->targetdef->d_RESET_CONTROL_OFFSET)
78 	(scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
80 	(scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
82 	(scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
84 	(scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
86 	(scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
87 #define GPIO_BASE_ADDRESS       (scn->targetdef->d_GPIO_BASE_ADDRESS)
88 #define GPIO_PIN0_OFFSET        (scn->targetdef->d_GPIO_PIN0_OFFSET)
89 #define GPIO_PIN1_OFFSET        (scn->targetdef->d_GPIO_PIN1_OFFSET)
90 #define GPIO_PIN0_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
91 #define GPIO_PIN1_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
92 #define A_SOC_CORE_SCRATCH_0    (scn->targetdef->d_A_SOC_CORE_SCRATCH_0)
94 	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
96 	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
97 #define SI_CONFIG_I2C_LSB       (scn->targetdef->d_SI_CONFIG_I2C_LSB)
99 	(scn->targetdef->d_SI_CONFIG_I2C_MASK)
101 	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
103 	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
105 	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
107 	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
109 	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
111 	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
112 #define SI_CONFIG_DIVIDER_LSB   (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
113 #define SI_CONFIG_DIVIDER_MASK  (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
114 #define SI_BASE_ADDRESS         (scn->targetdef->d_SI_BASE_ADDRESS)
115 #define SI_CONFIG_OFFSET        (scn->targetdef->d_SI_CONFIG_OFFSET)
116 #define SI_TX_DATA0_OFFSET      (scn->targetdef->d_SI_TX_DATA0_OFFSET)
117 #define SI_TX_DATA1_OFFSET      (scn->targetdef->d_SI_TX_DATA1_OFFSET)
118 #define SI_RX_DATA0_OFFSET      (scn->targetdef->d_SI_RX_DATA0_OFFSET)
119 #define SI_RX_DATA1_OFFSET      (scn->targetdef->d_SI_RX_DATA1_OFFSET)
120 #define SI_CS_OFFSET            (scn->targetdef->d_SI_CS_OFFSET)
121 #define SI_CS_DONE_ERR_MASK     (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
122 #define SI_CS_DONE_INT_MASK     (scn->targetdef->d_SI_CS_DONE_INT_MASK)
123 #define SI_CS_START_LSB         (scn->targetdef->d_SI_CS_START_LSB)
124 #define SI_CS_START_MASK        (scn->targetdef->d_SI_CS_START_MASK)
125 #define SI_CS_RX_CNT_LSB        (scn->targetdef->d_SI_CS_RX_CNT_LSB)
126 #define SI_CS_RX_CNT_MASK       (scn->targetdef->d_SI_CS_RX_CNT_MASK)
127 #define SI_CS_TX_CNT_LSB        (scn->targetdef->d_SI_CS_TX_CNT_LSB)
128 #define SI_CS_TX_CNT_MASK       (scn->targetdef->d_SI_CS_TX_CNT_MASK)
129 #define EEPROM_SZ               (scn->targetdef->d_BOARD_DATA_SZ)
130 #define EEPROM_EXT_SZ           (scn->targetdef->d_BOARD_EXT_DATA_SZ)
131 #define MBOX_BASE_ADDRESS       (scn->targetdef->d_MBOX_BASE_ADDRESS)
132 #define LOCAL_SCRATCH_OFFSET    (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
133 #define CPU_CLOCK_OFFSET        (scn->targetdef->d_CPU_CLOCK_OFFSET)
134 #define LPO_CAL_OFFSET          (scn->targetdef->d_LPO_CAL_OFFSET)
135 #define GPIO_PIN10_OFFSET       (scn->targetdef->d_GPIO_PIN10_OFFSET)
136 #define GPIO_PIN11_OFFSET       (scn->targetdef->d_GPIO_PIN11_OFFSET)
137 #define GPIO_PIN12_OFFSET       (scn->targetdef->d_GPIO_PIN12_OFFSET)
138 #define GPIO_PIN13_OFFSET       (scn->targetdef->d_GPIO_PIN13_OFFSET)
139 #define CLOCK_GPIO_OFFSET       (scn->targetdef->d_CLOCK_GPIO_OFFSET)
140 #define CPU_CLOCK_STANDARD_LSB  (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
141 #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
142 #define LPO_CAL_ENABLE_LSB      (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
143 #define LPO_CAL_ENABLE_MASK     (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
145 	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
147 	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
148 #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
149 #define WLAN_MAC_BASE_ADDRESS    (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
150 #define FW_INDICATOR_ADDRESS     (scn->targetdef->d_FW_INDICATOR_ADDRESS)
151 #define DRAM_BASE_ADDRESS        (scn->targetdef->d_DRAM_BASE_ADDRESS)
152 #define SOC_CORE_BASE_ADDRESS    (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
153 #define CORE_CTRL_ADDRESS        (scn->targetdef->d_CORE_CTRL_ADDRESS)
154 #define CE_COUNT                 (scn->targetdef->d_CE_COUNT)
155 #define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS)
156 #define PCIE_INTR_CLR_ADDRESS    (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS)
157 #define PCIE_INTR_FIRMWARE_MASK  (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK)
158 #define PCIE_INTR_CE_MASK_ALL    (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL)
159 #define CORE_CTRL_CPU_INTR_MASK  (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
160 #define PCIE_INTR_CAUSE_ADDRESS  (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS)
161 #define SOC_RESET_CONTROL_ADDRESS  (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
165 	(scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK)
167 	(scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
168 #define CPU_INTR_ADDRESS        (scn->targetdef->d_CPU_INTR_ADDRESS)
170 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
172 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
174 	(scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)
176 	(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
178 	(scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
188 #define CHIP_ID_ADDRESS           (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
189 #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
190 #define SOC_CHIP_ID_REVISION_LSB  (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
191 #define SOC_CHIP_ID_VERSION_MASK  (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
192 #define SOC_CHIP_ID_VERSION_LSB   (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
200 #define SR_WR_INDEX_ADDRESS     (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
201 #define DST_WATERMARK_ADDRESS   (scn->targetdef->d_DST_WATERMARK_ADDRESS)
202 #define SOC_POWER_REG_OFFSET    (scn->targetdef->d_SOC_POWER_REG_OFFSET)
208 #define EFUSE_OFFSET              (scn->targetdef->d_EFUSE_OFFSET)
209 #define EFUSE_XTAL_SEL_MSB        (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
210 #define EFUSE_XTAL_SEL_LSB        (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
211 #define EFUSE_XTAL_SEL_MASK       (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
212 #define BB_PLL_CONFIG_OFFSET      (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
213 #define BB_PLL_CONFIG_OUTDIV_MSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
214 #define BB_PLL_CONFIG_OUTDIV_LSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
215 #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
216 #define BB_PLL_CONFIG_FRAC_MSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
217 #define BB_PLL_CONFIG_FRAC_LSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
218 #define BB_PLL_CONFIG_FRAC_MASK   (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
219 #define WLAN_PLL_SETTLE_TIME_MSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
220 #define WLAN_PLL_SETTLE_TIME_LSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
221 #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
222 #define WLAN_PLL_SETTLE_OFFSET    (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
223 #define WLAN_PLL_SETTLE_SW_MASK   (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
224 #define WLAN_PLL_SETTLE_RSTMASK   (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
225 #define WLAN_PLL_SETTLE_RESET     (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
227 	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
229 	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
231 	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
233 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
235 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
237 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
239 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
241 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
243 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
245 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
247 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
249 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
251 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
253 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
255 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
256 #define WLAN_PLL_CONTROL_DIV_MSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
257 #define WLAN_PLL_CONTROL_DIV_LSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
258 #define WLAN_PLL_CONTROL_DIV_MASK  (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
260 	(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
261 #define WLAN_PLL_CONTROL_OFFSET    (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
262 #define WLAN_PLL_CONTROL_SW_MASK   (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
263 #define WLAN_PLL_CONTROL_RSTMASK   (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
264 #define WLAN_PLL_CONTROL_RESET     (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
265 #define SOC_CORE_CLK_CTRL_OFFSET   (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
266 #define SOC_CORE_CLK_CTRL_DIV_MSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
267 #define SOC_CORE_CLK_CTRL_DIV_LSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
269 	(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
271 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
273 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
275 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
277 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
278 #define RTC_SYNC_STATUS_OFFSET      (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
279 #define SOC_CPU_CLOCK_OFFSET        (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
281 	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
283 	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
285 	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
289 	(scn->targetdef->d_FW_CPU_PLL_CONFIG)
292 	(sc->targetdef->d_WIFICMN_PCIE_BAR_REG_ADDRESS)
296 	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK)
298 	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK)
300 	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK)
302 	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK)
304 	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB)
306 	(pdev->targetdef->d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB)
308 	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB)
310 	(pdev->targetdef->d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB)
313 	(scn->targetdef->d_CE_CMD_ADDRESS)
315 	(scn->targetdef->d_CE_CMD_HALT_MASK)
317 	(scn->targetdef->d_CE_CMD_HALT_STATUS_MASK)
319 	(scn->targetdef->d_CE_CMD_HALT_STATUS_LSB)
322 	(scn->targetdef->d_SI_CONFIG_ERR_INT_MASK)
324 	(scn->targetdef->d_SI_CONFIG_ERR_INT_LSB)
326 	(scn->targetdef->d_GPIO_ENABLE_W1TS_LOW_ADDRESS)
328 	(scn->targetdef->d_GPIO_PIN0_CONFIG_LSB)
330 	(scn->targetdef->d_GPIO_PIN0_PAD_PULL_LSB)
332 	(scn->targetdef->d_GPIO_PIN0_PAD_PULL_MASK)
335 	(scn->targetdef->d_SOC_CHIP_ID_REVISION_MSB)
338 	(scn->targetdef->d_FW_AXI_MSI_ADDR)
340 	(scn->targetdef->d_FW_AXI_MSI_DATA)
342 	(scn->targetdef->d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS)
344 	(scn->targetdef->d_FPGA_VERSION_ADDRESS)
434 	(scn->targetdef->d_Q6_ENABLE_REGISTER_0)
436 	(scn->targetdef->d_Q6_ENABLE_REGISTER_1)
438 	(scn->targetdef->d_Q6_CAUSE_REGISTER_0)
440 	(scn->targetdef->d_Q6_CAUSE_REGISTER_1)
442 	(scn->targetdef->d_Q6_CLEAR_REGISTER_0)
444 	(scn->targetdef->d_Q6_CLEAR_REGISTER_1)
449 	(scn->targetdef->d_BYPASS_QMI_TEMP_REGISTER)