Lines Matching refs:MISSING
56 #define MISSING 0 macro
63 #define RESET_CONTROL_MBOX_RST_MASK MISSING
84 #define MBOX_BASE_ADDRESS MISSING
85 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
86 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
87 #define INT_STATUS_ENABLE_CPU_LSB MISSING
88 #define INT_STATUS_ENABLE_CPU_MASK MISSING
89 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
90 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
91 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
92 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
93 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
94 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
95 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
96 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
97 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
98 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
99 #define INT_STATUS_ENABLE_ADDRESS MISSING
100 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
101 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
102 #define HOST_INT_STATUS_ADDRESS MISSING
103 #define CPU_INT_STATUS_ADDRESS MISSING
104 #define ERROR_INT_STATUS_ADDRESS MISSING
105 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
106 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
107 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
108 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
109 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
110 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
111 #define COUNT_DEC_ADDRESS MISSING
112 #define HOST_INT_STATUS_CPU_MASK MISSING
113 #define HOST_INT_STATUS_CPU_LSB MISSING
114 #define HOST_INT_STATUS_ERROR_MASK MISSING
115 #define HOST_INT_STATUS_ERROR_LSB MISSING
116 #define HOST_INT_STATUS_COUNTER_MASK MISSING
117 #define HOST_INT_STATUS_COUNTER_LSB MISSING
118 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
119 #define WINDOW_DATA_ADDRESS MISSING
120 #define WINDOW_READ_ADDR_ADDRESS MISSING
121 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
123 #define RX_ATTENTION_0_PHY_DATA_TYPE_MASK MISSING
124 #define RX_MSDU_END_8_LRO_ELIGIBLE_MASK MISSING
125 #define RX_MSDU_END_8_LRO_ELIGIBLE_LSB MISSING
126 #define RX_MSDU_END_8_L3_HEADER_PADDING_LSB MISSING
127 #define RX_MSDU_END_8_L3_HEADER_PADDING_MASK MISSING
129 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
130 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
131 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
132 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
133 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
134 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
135 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
136 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
150 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK MISSING
151 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT MISSING
152 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK MISSING
153 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT MISSING
154 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK MISSING
155 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT MISSING
156 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK MISSING
157 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT MISSING