Lines Matching refs:RTC_SOC_BASE_ADDRESS
662 (RTC_SOC_BASE_ADDRESS + in hif_pci_device_warm_reset()
665 (RTC_SOC_BASE_ADDRESS + SOC_LF_TIMER_CONTROL0_ADDRESS), val); in hif_pci_device_warm_reset()
668 (RTC_SOC_BASE_ADDRESS + SOC_LF_TIMER_CONTROL0_ADDRESS), in hif_pci_device_warm_reset()
674 (RTC_SOC_BASE_ADDRESS | in hif_pci_device_warm_reset()
678 (RTC_SOC_BASE_ADDRESS | SOC_RESET_CONTROL_ADDRESS)), in hif_pci_device_warm_reset()
682 (RTC_SOC_BASE_ADDRESS | in hif_pci_device_warm_reset()
688 hif_write32_mb(sc, mem + (RTC_SOC_BASE_ADDRESS | in hif_pci_device_warm_reset()
692 (RTC_SOC_BASE_ADDRESS | in hif_pci_device_warm_reset()
704 (RTC_SOC_BASE_ADDRESS | in hif_pci_device_warm_reset()
707 hif_write32_mb(sc, mem + (RTC_SOC_BASE_ADDRESS | in hif_pci_device_warm_reset()
711 (RTC_SOC_BASE_ADDRESS | in hif_pci_device_warm_reset()
794 hif_read32_mb(sc, sc->mem + RTC_SOC_BASE_ADDRESS + in hif_check_soc_status()
1606 RTC_SOC_BASE_ADDRESS, &chip_id); in hif_set_hia()
3617 tmp = hif_read32_mb(scn, scn->mem + (RTC_SOC_BASE_ADDRESS + in hif_trigger_timer_irq()
3622 hif_write32_mb(scn, scn->mem + (RTC_SOC_BASE_ADDRESS + in hif_trigger_timer_irq()