1179 	QDF_STATUS rv;  in hif_wake_target_cpu()  local
1183 	rv = hif_diag_read_access(hif_hdl,  in hif_wake_target_cpu()
1186 	QDF_ASSERT(rv == QDF_STATUS_SUCCESS);  in hif_wake_target_cpu()
1190 	rv = hif_diag_write_access(hif_hdl,  in hif_wake_target_cpu()
1193 	QDF_ASSERT(rv == QDF_STATUS_SUCCESS);  in hif_wake_target_cpu()
1415 	QDF_STATUS rv;  in hif_set_hia()  local
1495 	rv = hif_diag_read_access(hif_hdl, interconnect_targ_addr,  in hif_set_hia()
1497 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1499 			interconnect_targ_addr, rv);  in hif_set_hia()
1503 		rv = QDF_STATUS_E_FAILURE;  in hif_set_hia()
1510 	rv = hif_diag_read_access(hif_hdl,  in hif_set_hia()
1513 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1514 		hif_err("pipe_cfg_addr = 0x%0x, ret = %d", pipe_cfg_addr, rv);  in hif_set_hia()
1518 		rv = QDF_STATUS_E_FAILURE;  in hif_set_hia()
1523 	rv = hif_diag_write_mem(hif_hdl, pipe_cfg_targ_addr,  in hif_set_hia()
1527 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1528 		hif_err("write pipe cfg: %d", rv);  in hif_set_hia()
1532 	rv = hif_diag_read_access(hif_hdl,  in hif_set_hia()
1537 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1538 		hif_err("get svc/pipe map: %d", rv);  in hif_set_hia()
1542 		rv = QDF_STATUS_E_FAILURE;  in hif_set_hia()
1547 	rv = hif_diag_write_mem(hif_hdl,  in hif_set_hia()
1551 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1552 		hif_err("write svc/pipe map: %d", rv);  in hif_set_hia()
1556 	rv = hif_diag_read_access(hif_hdl,  in hif_set_hia()
1561 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1562 		hif_err("get pcie config_flags: %d", rv);  in hif_set_hia()
1574 	rv = hif_diag_write_mem(hif_hdl,  in hif_set_hia()
1580 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1581 		hif_err("write pcie config_flags: %d", rv);  in hif_set_hia()
1592 	rv = hif_diag_read_access(hif_hdl, ealloc_targ_addr,  in hif_set_hia()
1594 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1595 		hif_err("get early alloc val: %d", rv);  in hif_set_hia()
1604 	rv = hif_diag_read_access(hif_hdl,  in hif_set_hia()
1607 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1608 		hif_err("get chip id val: %d", rv);  in hif_set_hia()
1640 	rv = hif_diag_write_access(hif_hdl,  in hif_set_hia()
1643 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1644 		hif_err("set early alloc val: %d", rv);  in hif_set_hia()
1661 	rv = hif_diag_read_access(hif_hdl, flag2_targ_addr,  in hif_set_hia()
1663 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1664 		hif_err("get option val: %d", rv);  in hif_set_hia()
1669 	rv = hif_diag_write_access(hif_hdl, flag2_targ_addr,  in hif_set_hia()
1671 	if (rv != QDF_STATUS_SUCCESS) {  in hif_set_hia()
1672 		hif_err("set option val: %d", rv);  in hif_set_hia()
1680 	return qdf_status_to_os_return(rv);  in hif_set_hia()