Lines Matching refs:MISSING
27 #define MISSING 0 macro
29 #define SOC_RESET_CONTROL_OFFSET MISSING
30 #define GPIO_PIN0_OFFSET MISSING
31 #define GPIO_PIN1_OFFSET MISSING
32 #define GPIO_PIN0_CONFIG_MASK MISSING
33 #define GPIO_PIN1_CONFIG_MASK MISSING
35 #define GPIO_PIN10_OFFSET MISSING
36 #define GPIO_PIN11_OFFSET MISSING
37 #define GPIO_PIN12_OFFSET MISSING
38 #define GPIO_PIN13_OFFSET MISSING
39 #define MBOX_BASE_ADDRESS MISSING
40 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
41 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
42 #define INT_STATUS_ENABLE_CPU_LSB MISSING
43 #define INT_STATUS_ENABLE_CPU_MASK MISSING
44 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
45 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
46 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
47 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
48 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
49 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
50 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
51 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
52 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
53 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
54 #define INT_STATUS_ENABLE_ADDRESS MISSING
55 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
56 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
57 #define HOST_INT_STATUS_ADDRESS MISSING
58 #define CPU_INT_STATUS_ADDRESS MISSING
59 #define ERROR_INT_STATUS_ADDRESS MISSING
60 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
61 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
62 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
63 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
64 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
65 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
66 #define COUNT_DEC_ADDRESS MISSING
67 #define HOST_INT_STATUS_CPU_MASK MISSING
68 #define HOST_INT_STATUS_CPU_LSB MISSING
69 #define HOST_INT_STATUS_ERROR_MASK MISSING
70 #define HOST_INT_STATUS_ERROR_LSB MISSING
71 #define HOST_INT_STATUS_COUNTER_MASK MISSING
72 #define HOST_INT_STATUS_COUNTER_LSB MISSING
73 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
74 #define WINDOW_DATA_ADDRESS MISSING
75 #define WINDOW_READ_ADDR_ADDRESS MISSING
76 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
78 #define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING
79 #define GPIO_PIN0_CONFIG_LSB MISSING
80 #define GPIO_PIN0_PAD_PULL_LSB MISSING
81 #define GPIO_PIN0_PAD_PULL_MASK MISSING
83 #define SI_CONFIG_ERR_INT_MASK MISSING
84 #define SI_CONFIG_ERR_INT_LSB MISSING
86 #define RTC_SOC_BASE_ADDRESS MISSING
87 #define RTC_WMAC_BASE_ADDRESS MISSING
88 #define SOC_CORE_BASE_ADDRESS MISSING
89 #define WLAN_MAC_BASE_ADDRESS MISSING
90 #define GPIO_BASE_ADDRESS MISSING
91 #define ANALOG_INTF_BASE_ADDRESS MISSING
92 #define CE0_BASE_ADDRESS MISSING
93 #define CE1_BASE_ADDRESS MISSING
95 #define CE_WRAPPER_BASE_ADDRESS MISSING
96 #define SI_BASE_ADDRESS MISSING
97 #define DRAM_BASE_ADDRESS MISSING
99 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
100 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
101 #define CLOCK_CONTROL_OFFSET MISSING
102 #define CLOCK_CONTROL_SI0_CLK_MASK MISSING
103 #define RESET_CONTROL_SI0_RST_MASK MISSING
104 #define WLAN_RESET_CONTROL_OFFSET MISSING
105 #define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
106 #define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
107 #define CPU_CLOCK_OFFSET MISSING
109 #define CPU_CLOCK_STANDARD_LSB MISSING
110 #define CPU_CLOCK_STANDARD_MASK MISSING
111 #define LPO_CAL_ENABLE_LSB MISSING
112 #define LPO_CAL_ENABLE_MASK MISSING
113 #define WLAN_SYSTEM_SLEEP_OFFSET MISSING
115 #define SOC_CHIP_ID_ADDRESS MISSING
116 #define SOC_CHIP_ID_REVISION_MASK MISSING
117 #define SOC_CHIP_ID_REVISION_LSB MISSING
118 #define SOC_CHIP_ID_REVISION_MSB MISSING
120 #define FW_IND_EVENT_PENDING MISSING
121 #define FW_IND_INITIALIZED MISSING
123 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
124 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
125 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
126 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
127 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
128 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
129 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
130 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
132 #define SR_WR_INDEX_ADDRESS MISSING
133 #define DST_WATERMARK_ADDRESS MISSING
135 #define DST_WR_INDEX_ADDRESS MISSING
136 #define SRC_WATERMARK_ADDRESS MISSING
137 #define SRC_WATERMARK_LOW_MASK MISSING
138 #define SRC_WATERMARK_HIGH_MASK MISSING
139 #define DST_WATERMARK_LOW_MASK MISSING
140 #define DST_WATERMARK_HIGH_MASK MISSING
141 #define CURRENT_SRRI_ADDRESS MISSING
142 #define CURRENT_DRRI_ADDRESS MISSING
143 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
144 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
145 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
146 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
147 #define HOST_IS_ADDRESS MISSING
148 #define MISC_IS_ADDRESS MISSING
149 #define HOST_IS_COPY_COMPLETE_MASK MISSING
150 #define CE_WRAPPER_BASE_ADDRESS MISSING
151 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
152 #define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
153 #define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
158 #define HOST_IE_COPY_COMPLETE_MASK MISSING
159 #define SR_BA_ADDRESS MISSING
160 #define SR_BA_ADDRESS_HIGH MISSING
161 #define SR_SIZE_ADDRESS MISSING
162 #define CE_CTRL1_ADDRESS MISSING
163 #define CE_CTRL1_DMAX_LENGTH_MASK MISSING
164 #define DR_BA_ADDRESS MISSING
165 #define DR_BA_ADDRESS_HIGH MISSING
166 #define DR_SIZE_ADDRESS MISSING
167 #define CE_CMD_REGISTER MISSING
168 #define CE_MSI_ADDRESS MISSING
169 #define CE_MSI_ADDRESS_HIGH MISSING
170 #define CE_MSI_DATA MISSING
171 #define CE_MSI_ENABLE_BIT MISSING
172 #define MISC_IE_ADDRESS MISSING
173 #define MISC_IS_AXI_ERR_MASK MISSING
174 #define MISC_IS_DST_ADDR_ERR_MASK MISSING
175 #define MISC_IS_SRC_LEN_ERR_MASK MISSING
176 #define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
177 #define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
178 #define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
179 #define SRC_WATERMARK_LOW_LSB MISSING
180 #define SRC_WATERMARK_HIGH_LSB MISSING
181 #define DST_WATERMARK_LOW_LSB MISSING
182 #define DST_WATERMARK_HIGH_LSB MISSING
183 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
184 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
185 #define CE_CTRL1_DMAX_LENGTH_LSB MISSING
186 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
187 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
188 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
189 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
190 #define CE_CTRL1_IDX_UPD_EN_MASK MISSING
191 #define CE_WRAPPER_DEBUG_OFFSET MISSING
192 #define CE_WRAPPER_DEBUG_SEL_MSB MISSING
193 #define CE_WRAPPER_DEBUG_SEL_LSB MISSING
194 #define CE_WRAPPER_DEBUG_SEL_MASK MISSING
195 #define CE_DEBUG_OFFSET MISSING
196 #define CE_DEBUG_SEL_MSB MISSING
197 #define CE_DEBUG_SEL_LSB MISSING
198 #define CE_DEBUG_SEL_MASK MISSING
199 #define CE0_BASE_ADDRESS MISSING
200 #define CE1_BASE_ADDRESS MISSING
201 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
202 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
204 #define QCA6390_BOARD_DATA_SZ MISSING
205 #define QCA6390_BOARD_EXT_DATA_SZ MISSING