src/sdio/regtable_sdio.h

249 	(scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER)
251 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS)
253 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS)
255 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS)
257 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS)
259 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS)
261 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS)
263 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS)
265 	(scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS)
266 #define RTC_SOC_BASE_ADDRESS  (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
267 #define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
268 #define SYSTEM_SLEEP_OFFSET   (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
270 	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
272 	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
274 	(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
275 #define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
277 	(scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
278 #define RESET_CONTROL_OFFSET    (scn->targetdef->d_RESET_CONTROL_OFFSET)
280 	(scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
282 	(scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
284 	(scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
286 	(scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
288 	(scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
289 #define GPIO_BASE_ADDRESS       (scn->targetdef->d_GPIO_BASE_ADDRESS)
290 #define GPIO_PIN0_OFFSET        (scn->targetdef->d_GPIO_PIN0_OFFSET)
291 #define GPIO_PIN1_OFFSET        (scn->targetdef->d_GPIO_PIN1_OFFSET)
292 #define GPIO_PIN0_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
293 #define GPIO_PIN1_CONFIG_MASK   (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
294 #define A_SOC_CORE_SCRATCH_0    (scn->targetdef->d_A_SOC_CORE_SCRATCH_0)
296 	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
298 	(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
299 #define SI_CONFIG_I2C_LSB       (scn->targetdef->d_SI_CONFIG_I2C_LSB)
301 	(scn->targetdef->d_SI_CONFIG_I2C_MASK)
303 	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
305 	(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
307 	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
309 	(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
311 	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
313 	(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
314 #define SI_CONFIG_DIVIDER_LSB   (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
315 #define SI_CONFIG_DIVIDER_MASK  (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
316 #define SI_BASE_ADDRESS         (scn->targetdef->d_SI_BASE_ADDRESS)
317 #define SI_CONFIG_OFFSET        (scn->targetdef->d_SI_CONFIG_OFFSET)
318 #define SI_TX_DATA0_OFFSET      (scn->targetdef->d_SI_TX_DATA0_OFFSET)
319 #define SI_TX_DATA1_OFFSET      (scn->targetdef->d_SI_TX_DATA1_OFFSET)
320 #define SI_RX_DATA0_OFFSET      (scn->targetdef->d_SI_RX_DATA0_OFFSET)
321 #define SI_RX_DATA1_OFFSET      (scn->targetdef->d_SI_RX_DATA1_OFFSET)
322 #define SI_CS_OFFSET            (scn->targetdef->d_SI_CS_OFFSET)
323 #define SI_CS_DONE_ERR_MASK     (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
324 #define SI_CS_DONE_INT_MASK     (scn->targetdef->d_SI_CS_DONE_INT_MASK)
325 #define SI_CS_START_LSB         (scn->targetdef->d_SI_CS_START_LSB)
326 #define SI_CS_START_MASK        (scn->targetdef->d_SI_CS_START_MASK)
327 #define SI_CS_RX_CNT_LSB        (scn->targetdef->d_SI_CS_RX_CNT_LSB)
328 #define SI_CS_RX_CNT_MASK       (scn->targetdef->d_SI_CS_RX_CNT_MASK)
329 #define SI_CS_TX_CNT_LSB        (scn->targetdef->d_SI_CS_TX_CNT_LSB)
330 #define SI_CS_TX_CNT_MASK       (scn->targetdef->d_SI_CS_TX_CNT_MASK)
331 #define EEPROM_SZ               (scn->targetdef->d_BOARD_DATA_SZ)
332 #define EEPROM_EXT_SZ           (scn->targetdef->d_BOARD_EXT_DATA_SZ)
333 #define MBOX_BASE_ADDRESS       (scn->targetdef->d_MBOX_BASE_ADDRESS)
334 #define LOCAL_SCRATCH_OFFSET    (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
335 #define CPU_CLOCK_OFFSET        (scn->targetdef->d_CPU_CLOCK_OFFSET)
336 #define LPO_CAL_OFFSET          (scn->targetdef->d_LPO_CAL_OFFSET)
337 #define GPIO_PIN10_OFFSET       (scn->targetdef->d_GPIO_PIN10_OFFSET)
338 #define GPIO_PIN11_OFFSET       (scn->targetdef->d_GPIO_PIN11_OFFSET)
339 #define GPIO_PIN12_OFFSET       (scn->targetdef->d_GPIO_PIN12_OFFSET)
340 #define GPIO_PIN13_OFFSET       (scn->targetdef->d_GPIO_PIN13_OFFSET)
341 #define CLOCK_GPIO_OFFSET       (scn->targetdef->d_CLOCK_GPIO_OFFSET)
342 #define CPU_CLOCK_STANDARD_LSB  (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
343 #define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
344 #define LPO_CAL_ENABLE_LSB      (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
345 #define LPO_CAL_ENABLE_MASK     (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
347 	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
349 	(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
350 #define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
351 #define WLAN_MAC_BASE_ADDRESS    (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
352 #define FW_INDICATOR_ADDRESS     (scn->targetdef->d_FW_INDICATOR_ADDRESS)
353 #define DRAM_BASE_ADDRESS        (scn->targetdef->d_DRAM_BASE_ADDRESS)
354 #define SOC_CORE_BASE_ADDRESS    (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
355 #define CORE_CTRL_ADDRESS        (scn->targetdef->d_CORE_CTRL_ADDRESS)
356 #define CORE_CTRL_CPU_INTR_MASK  (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
357 #define SOC_RESET_CONTROL_ADDRESS  (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
359 	(scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
360 #define CPU_INTR_ADDRESS        (scn->targetdef->d_CPU_INTR_ADDRESS)
362 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
364 	(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
366 	(scn->targetdef->d_SOC_LF_TIMER_STATUS0_ADDRESS)
369 #define CHIP_ID_ADDRESS           (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
370 #define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
371 #define SOC_CHIP_ID_REVISION_LSB  (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
372 #define SOC_CHIP_ID_VERSION_MASK  (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
373 #define SOC_CHIP_ID_VERSION_LSB   (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
380 #define SR_WR_INDEX_ADDRESS     (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
381 #define DST_WATERMARK_ADDRESS   (scn->targetdef->d_DST_WATERMARK_ADDRESS)
382 #define SOC_POWER_REG_OFFSET    (scn->targetdef->d_SOC_POWER_REG_OFFSET)
388 #define EFUSE_OFFSET              (scn->targetdef->d_EFUSE_OFFSET)
389 #define EFUSE_XTAL_SEL_MSB        (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
390 #define EFUSE_XTAL_SEL_LSB        (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
391 #define EFUSE_XTAL_SEL_MASK       (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
392 #define BB_PLL_CONFIG_OFFSET      (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
393 #define BB_PLL_CONFIG_OUTDIV_MSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
394 #define BB_PLL_CONFIG_OUTDIV_LSB  (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
395 #define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
396 #define BB_PLL_CONFIG_FRAC_MSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
397 #define BB_PLL_CONFIG_FRAC_LSB    (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
398 #define BB_PLL_CONFIG_FRAC_MASK   (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
399 #define WLAN_PLL_SETTLE_TIME_MSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
400 #define WLAN_PLL_SETTLE_TIME_LSB  (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
401 #define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
402 #define WLAN_PLL_SETTLE_OFFSET    (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
403 #define WLAN_PLL_SETTLE_SW_MASK   (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
404 #define WLAN_PLL_SETTLE_RSTMASK   (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
405 #define WLAN_PLL_SETTLE_RESET     (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
407 	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
409 	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
411 	(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
413 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
415 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
417 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
419 	(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
421 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
423 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
425 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
427 	(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
429 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
431 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
433 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
435 	(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
436 #define WLAN_PLL_CONTROL_DIV_MSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
437 #define WLAN_PLL_CONTROL_DIV_LSB   (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
438 #define WLAN_PLL_CONTROL_DIV_MASK  (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
440 	(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
441 #define WLAN_PLL_CONTROL_OFFSET    (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
442 #define WLAN_PLL_CONTROL_SW_MASK   (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
443 #define WLAN_PLL_CONTROL_RSTMASK   (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
444 #define WLAN_PLL_CONTROL_RESET     (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
445 #define SOC_CORE_CLK_CTRL_OFFSET   (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
446 #define SOC_CORE_CLK_CTRL_DIV_MSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
447 #define SOC_CORE_CLK_CTRL_DIV_LSB  (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
449 	(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
451 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
453 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
455 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
457 	(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
458 #define RTC_SYNC_STATUS_OFFSET      (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
459 #define SOC_CPU_CLOCK_OFFSET        (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
461 	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
463 	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
465 	(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
549 	(scn->targetdef->d_Q6_ENABLE_REGISTER_0)
551 	(scn->targetdef->d_Q6_ENABLE_REGISTER_1)
553 	(scn->targetdef->d_Q6_CAUSE_REGISTER_0)
555 	(scn->targetdef->d_Q6_CAUSE_REGISTER_1)
557 	(scn->targetdef->d_Q6_CLEAR_REGISTER_0)
559 	(scn->targetdef->d_Q6_CLEAR_REGISTER_1)