686 	uint32_t regval;  in hif_ahb_irq_enable()  local
697 			regval = hif_read32_mb(scn, mem + reg_offset);  in hif_ahb_irq_enable()
698 			regval |= HOST_IE_REG1_CE_BIT(ce_id);  in hif_ahb_irq_enable()
699 			hif_write32_mb(scn, mem + reg_offset, regval);  in hif_ahb_irq_enable()
705 			regval = hif_read32_mb(scn, mem + reg_offset);  in hif_ahb_irq_enable()
706 			regval |= HOST_IE_REG2_CE_BIT(ce_id);  in hif_ahb_irq_enable()
707 			hif_write32_mb(scn, mem + reg_offset, regval);  in hif_ahb_irq_enable()
717 				regval = hif_read32_mb(scn, mem +  in hif_ahb_irq_enable()
719 				regval |= HOST_IE_REG3_CE_BIT(ce_id);  in hif_ahb_irq_enable()
722 					       HOST_IE_ADDRESS_3, regval);  in hif_ahb_irq_enable()
740 	uint32_t regval;  in hif_ahb_irq_disable()  local
751 			regval = hif_read32_mb(scn, mem + reg_offset);  in hif_ahb_irq_disable()
752 			regval &= ~HOST_IE_REG1_CE_BIT(ce_id);  in hif_ahb_irq_disable()
753 			hif_write32_mb(scn, mem + reg_offset, regval);  in hif_ahb_irq_disable()
759 			regval = hif_read32_mb(scn, mem + reg_offset);  in hif_ahb_irq_disable()
760 			regval &= ~HOST_IE_REG2_CE_BIT(ce_id);  in hif_ahb_irq_disable()
761 			hif_write32_mb(scn, mem + reg_offset, regval);  in hif_ahb_irq_disable()
771 				regval = hif_read32_mb(scn, mem +  in hif_ahb_irq_disable()
773 				regval &= ~HOST_IE_REG3_CE_BIT(ce_id);  in hif_ahb_irq_disable()
776 					       HOST_IE_ADDRESS_3, regval);  in hif_ahb_irq_disable()
831 	uint32_t regval;  in hif_display_ahb_irq_regs()  local
841 		regval = hif_read32_mb(scn, mem + HOST_IE_ADDRESS);  in hif_display_ahb_irq_regs()
842 		hif_nofl_err("IRQ enable register value 0x%08x", regval);  in hif_display_ahb_irq_regs()
844 		regval = hif_read32_mb(scn, mem + HOST_IE_ADDRESS_2);  in hif_display_ahb_irq_regs()
845 		hif_nofl_err("IRQ enable register 2 value 0x%08x", regval);  in hif_display_ahb_irq_regs()
853 			regval = hif_read32_mb(scn, mem +  in hif_display_ahb_irq_regs()
856 				     regval);  in hif_display_ahb_irq_regs()