/* * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the * above copyright notice and this permission notice appear in all * copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ /////////////////////////////////////////////////////////////////////////////////////////////// // // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.1 10/27/2016 // User Name:kanalas // // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. // /////////////////////////////////////////////////////////////////////////////////////////////// #ifndef __WCSS_SEQ_BASE_H__ #define __WCSS_SEQ_BASE_H__ #ifdef SCALE_INCLUDES #include "../../../include/HALhwio.h" #else #include "msmhwio.h" #endif /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block wcss /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_WCSS_ECAHB_OFFSET 0x00008400 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 #define SEQ_WCSS_MPSS_OFFSET 0x00200000 #define SEQ_WCSS_MPSS_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00200000 #define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_OFFSET 0x00280000 #define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00281800 #define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00281c00 #define SEQ_WCSS_PHYA_OFFSET 0x00400000 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00480000 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00480400 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00480800 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00480c00 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00481000 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00481400 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00484000 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x00488000 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00500000 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x00520000 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x00528000 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00530000 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x005a0000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x005c0000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_OTP_OFFSET 0x005c0000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_TLMM_OFFSET 0x005c4000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x005c8000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4400 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4800 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x005d6080 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d60e0 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6100 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6140 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d6180 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x005d6880 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d68e0 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d6900 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6940 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d6980 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x005e1000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x005e1200 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x005e9000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x005e9200 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x005f0000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x005f0400 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x005f0800 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x005f1000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x005f1200 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x005f2000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x005f8000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x005f8400 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x005f8800 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x005f9000 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x005f9200 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x005fa000 #define SEQ_WCSS_PHYB_OFFSET 0x00600000 #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00600000 #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00680000 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00680400 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00680800 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00680c00 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00681000 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00681400 #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00684000 #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00688000 #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00700000 #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00720000 #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00728000 #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00730000 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x007a0000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x007c0000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x007c0000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OTP_OFFSET 0x007c0000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_TLMM_OFFSET 0x007c4000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x007c8000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x007d4000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4400 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4800 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x007d6000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x007d6040 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x007d6080 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x007d60e0 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x007d6100 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x007d6140 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x007d6180 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x007d6800 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x007d6840 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x007d6880 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x007d68e0 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x007d6900 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x007d6940 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x007d6980 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x007e0000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x007e0000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x007e0400 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x007e0800 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x007e1000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x007e1200 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x007e2000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x007e8000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x007e8400 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x007e8800 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x007e9000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x007e9200 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x007ea000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x007f0000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x007f0400 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x007f0800 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x007f1000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x007f1200 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x007f2000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x007f8000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x007f8400 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x007f8800 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x007f9000 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x007f9200 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x007fa000 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 #define SEQ_WCSS_UMAC_MAC_CCE_REG_OFFSET 0x00a4a000 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 #define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 #define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET 0x00ab9000 #define SEQ_WCSS_WMAC1_OFFSET 0x00b00000 #define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00b00000 #define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00b03000 #define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00b06000 #define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00b09000 #define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00b0c000 #define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00b0f000 #define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00b12000 #define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00b15000 #define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 #define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00b1b000 #define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00b1e000 #define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 #define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00b24000 #define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00b27000 #define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00b2a000 #define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00b30000 #define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00b33000 #define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00b36000 #define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00b39000 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 #define SEQ_WCSS_WCMN_OFFSET 0x00b50000 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 #define SEQ_WCSS_PMM_OFFSET 0x00b70000 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 #define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00b94000 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00b98000 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00b99000 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000 #define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x00b9a000 #define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x00b9b000 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET 0x00b9c000 #define SEQ_WCSS_DBG_UMAC_NOC_UMAC_NOC_OFFSET 0x00ba0000 #define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb0000 #define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00bb1000 #define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000 #define SEQ_WCSS_DBG_PHYA_CPU0_M3_AHB_AP_OFFSET 0x00bbe000 #define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000 #define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00bc1000 #define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000 #define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x00bce000 #define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00bf0000 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00bf1000 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 #define SEQ_WCSS_CC_OFFSET 0x00c30000 #define SEQ_WCSS_ACMT_OFFSET 0x00c40000 #define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 #define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 #define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x00d80000 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x00d90000 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x00da1000 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x00da2000 #define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x00da3000 #define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block mpss_top /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_MPSS_TOP_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00000000 #define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_OFFSET 0x00080000 #define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00081800 #define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00081c00 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block wfax_top /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00084000 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x00088000 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00100000 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x00120000 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x00128000 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_NPRA_REG_MAP_OFFSET 0x00130000 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x001a0000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x001c0000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_OFFSET 0x001c0000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_OTP_OFFSET 0x001c0000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_TLMM_OFFSET 0x001c4000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4800 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x001d6080 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d60e0 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d6100 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6140 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6180 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x001d6880 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d68e0 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d6900 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6940 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6980 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x001e0000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x001e1000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x001e1200 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x001e9000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x001e9200 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x001f1000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x001f1200 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x001f9000 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x001f9200 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block iron2g /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_IRON2G_RFA_DIG_OFFSET 0x00000000 #define SEQ_IRON2G_RFA_DIG_OTP_OFFSET 0x00000000 #define SEQ_IRON2G_RFA_DIG_TLMM_OFFSET 0x00004000 #define SEQ_IRON2G_RFA_DIG_SYSCTRL_OFFSET 0x00008000 #define SEQ_IRON2G_RFA_CMN_OFFSET 0x00014000 #define SEQ_IRON2G_RFA_CMN_AON_OFFSET 0x00014000 #define SEQ_IRON2G_RFA_CMN_CLKGEN_OFFSET 0x00014400 #define SEQ_IRON2G_RFA_CMN_RFFE_M_OFFSET 0x00014800 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x00016080 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x000160e0 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016100 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016140 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00016180 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x00016880 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x000168e0 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00016900 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016940 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016980 #define SEQ_IRON2G_RFA_WL_OFFSET 0x00020000 #define SEQ_IRON2G_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 #define SEQ_IRON2G_RFA_WL_WL_TXFE_CH0_OFFSET 0x00021000 #define SEQ_IRON2G_RFA_WL_WL_RXFE_CH0_OFFSET 0x00021200 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 #define SEQ_IRON2G_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 #define SEQ_IRON2G_RFA_WL_WL_TXFE_CH1_OFFSET 0x00029000 #define SEQ_IRON2G_RFA_WL_WL_RXFE_CH1_OFFSET 0x00029200 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 #define SEQ_IRON2G_RFA_WL_WL_MC_CH2_OFFSET 0x00030000 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH2_OFFSET 0x00030400 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH2_OFFSET 0x00030800 #define SEQ_IRON2G_RFA_WL_WL_TXFE_CH2_OFFSET 0x00031000 #define SEQ_IRON2G_RFA_WL_WL_RXFE_CH2_OFFSET 0x00031200 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH2_OFFSET 0x00032000 #define SEQ_IRON2G_RFA_WL_WL_MC_CH3_OFFSET 0x00038000 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH3_OFFSET 0x00038400 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH3_OFFSET 0x00038800 #define SEQ_IRON2G_RFA_WL_WL_TXFE_CH3_OFFSET 0x00039000 #define SEQ_IRON2G_RFA_WL_WL_RXFE_CH3_OFFSET 0x00039200 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH3_OFFSET 0x0003a000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block rfa_dig /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_RFA_DIG_OTP_OFFSET 0x00000000 #define SEQ_RFA_DIG_TLMM_OFFSET 0x00004000 #define SEQ_RFA_DIG_SYSCTRL_OFFSET 0x00008000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block rfa_cmn /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000400 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000800 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 #define SEQ_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x00002080 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x000020e0 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002100 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002140 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00002180 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 #define SEQ_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x00002880 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x000028e0 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00002900 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002940 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002980 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block rfa_wl /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 #define SEQ_RFA_WL_WL_TXFE_CH0_OFFSET 0x00001000 #define SEQ_RFA_WL_WL_RXFE_CH0_OFFSET 0x00001200 #define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 #define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 #define SEQ_RFA_WL_WL_TXFE_CH1_OFFSET 0x00009000 #define SEQ_RFA_WL_WL_RXFE_CH1_OFFSET 0x00009200 #define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 #define SEQ_RFA_WL_WL_MC_CH2_OFFSET 0x00010000 #define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET 0x00010400 #define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET 0x00010800 #define SEQ_RFA_WL_WL_TXFE_CH2_OFFSET 0x00011000 #define SEQ_RFA_WL_WL_RXFE_CH2_OFFSET 0x00011200 #define SEQ_RFA_WL_WL_TPC_CH2_OFFSET 0x00012000 #define SEQ_RFA_WL_WL_MC_CH3_OFFSET 0x00018000 #define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET 0x00018400 #define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET 0x00018800 #define SEQ_RFA_WL_WL_TXFE_CH3_OFFSET 0x00019000 #define SEQ_RFA_WL_WL_RXFE_CH3_OFFSET 0x00019200 #define SEQ_RFA_WL_WL_TPC_CH3_OFFSET 0x0001a000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block wfax_top_b /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 #define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00100000 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_NPRB_B_REG_MAP_OFFSET 0x00130000 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x001c0000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OTP_OFFSET 0x001c0000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_TLMM_OFFSET 0x001c4000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4400 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4800 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PAL_OFFSET 0x001d6080 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d60e0 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d6100 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6140 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6180 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PAL_OFFSET 0x001d6880 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d68e0 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d6900 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6940 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6980 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x001e1000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x001e1200 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x001e9000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x001e9200 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH2_OFFSET 0x001f1000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH2_OFFSET 0x001f1200 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_CH3_OFFSET 0x001f9000 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE_CH3_OFFSET 0x001f9200 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block umac_top_reg /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 #define SEQ_UMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0004a000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block wfss_ce_reg /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 #define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block cxc_top_reg /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block wmac_top_reg_28lp /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_WMAC_TOP_REG_28LP_MAC_PDG_REG_OFFSET 0x00000000 #define SEQ_WMAC_TOP_REG_28LP_MAC_TXDMA_REG_OFFSET 0x00003000 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA_REG_OFFSET 0x00006000 #define SEQ_WMAC_TOP_REG_28LP_MAC_MCMN_REG_OFFSET 0x00009000 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXPCU_REG_OFFSET 0x0000c000 #define SEQ_WMAC_TOP_REG_28LP_MAC_TXPCU_REG_OFFSET 0x0000f000 #define SEQ_WMAC_TOP_REG_28LP_MAC_AMPI_REG_OFFSET 0x00012000 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_REG_OFFSET 0x00015000 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 #define SEQ_WMAC_TOP_REG_28LP_MAC_CCE_REG_OFFSET 0x0001b000 #define SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_REG_OFFSET 0x0001e000 #define SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 #define SEQ_WMAC_TOP_REG_28LP_MAC_RRI_REG_OFFSET 0x00024000 #define SEQ_WMAC_TOP_REG_28LP_MAC_CRYPTO_REG_OFFSET 0x00027000 #define SEQ_WMAC_TOP_REG_28LP_MAC_HWSCH_REG_OFFSET 0x0002a000 #define SEQ_WMAC_TOP_REG_28LP_MAC_MXI_REG_OFFSET 0x00030000 #define SEQ_WMAC_TOP_REG_28LP_MAC_SFM_REG_OFFSET 0x00033000 #define SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA1_REG_OFFSET 0x00036000 #define SEQ_WMAC_TOP_REG_28LP_MAC_LPEC_REG_OFFSET 0x00039000 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_PDG_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXDMA_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_MCMN_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXPCU_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXPCU_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_AMPI_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXOLE_PARSER_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_CCE_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXOLE_PARSER_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RRI_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_CRYPTO_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_HWSCH_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_MXI_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_SFM_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA1_REG_OFFSET #define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_LPEC_REG_OFFSET /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block wcssdbg_napier /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_WCSSDBG_NAPIER_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 #define SEQ_WCSSDBG_NAPIER_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 #define SEQ_WCSSDBG_NAPIER_TSGEN_CXTSGEN_OFFSET 0x00002000 #define SEQ_WCSSDBG_NAPIER_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 #define SEQ_WCSSDBG_NAPIER_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 #define SEQ_WCSSDBG_NAPIER_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 #define SEQ_WCSSDBG_NAPIER_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 #define SEQ_WCSSDBG_NAPIER_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 #define SEQ_WCSSDBG_NAPIER_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 #define SEQ_WCSSDBG_NAPIER_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 #define SEQ_WCSSDBG_NAPIER_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 #define SEQ_WCSSDBG_NAPIER_UMAC_NOC_UMAC_NOC_OFFSET 0x00010000 #define SEQ_WCSSDBG_NAPIER_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000 #define SEQ_WCSSDBG_NAPIER_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000 #define SEQ_WCSSDBG_NAPIER_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000 #define SEQ_WCSSDBG_NAPIER_PHYA_CPU0_M3_AHB_AP_OFFSET 0x0002e000 #define SEQ_WCSSDBG_NAPIER_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000 #define SEQ_WCSSDBG_NAPIER_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000 #define SEQ_WCSSDBG_NAPIER_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000 #define SEQ_WCSSDBG_NAPIER_PHYB_CPU0_M3_AHB_AP_OFFSET 0x0003e000 #define SEQ_WCSSDBG_NAPIER_UMAC_CPU_M3_AHB_AP_OFFSET 0x00060000 #define SEQ_WCSSDBG_NAPIER_BUS_TIMEOUT_OFFSET 0x00061000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block qdsp6ss_public /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET 0x00000000 /////////////////////////////////////////////////////////////////////////////////////////////// // Instance Relative Offsets from Block qdsp6ss_private /////////////////////////////////////////////////////////////////////////////////////////////// #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET 0x00000000 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET 0x00010000 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 #define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 #define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 #define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 #define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET 0x00030000 #endif