/* * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the * above copyright notice and this permission notice appear in all * copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #include "hal_li_hw_headers.h" #include "hal_internal.h" #include "hal_api.h" #include "target_type.h" #include "wcss_version.h" #include "qdf_module.h" #include "hal_9000_rx.h" #include "hal_api_mon.h" #include "hal_flow.h" #include "rx_flow_search_entry.h" #include "hal_rx_flow_info.h" #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ STATUS_HEADER_REO_STATUS_NUMBER #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ STATUS_HEADER_TIMESTAMP #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB #define CE_WINDOW_ADDRESS_9000 \ ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) #define UMAC_WINDOW_ADDRESS_9000 \ ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) #define WINDOW_CONFIGURATION_VALUE_9000 \ ((CE_WINDOW_ADDRESS_9000 << 6) |\ (UMAC_WINDOW_ADDRESS_9000 << 12) | \ WINDOW_ENABLE_BIT) #include "hal_9000_tx.h" #include #include "hal_li_rx.h" #include "hal_li_api.h" #include "hal_li_generic_api.h" /** * hal_rx_sw_mon_desc_info_get_9000() - API to read the sw monitor ring * descriptor * @rxdma_dst_ring_desc: sw monitor ring descriptor * @desc_info_buf: Descriptor info buffer to which sw monitor ring descriptor is * populated to * * Return: void */ static void hal_rx_sw_mon_desc_info_get_9000(hal_ring_desc_t rxdma_dst_ring_desc, hal_rx_mon_desc_info_t desc_info_buf) { struct sw_monitor_ring *sw_mon_ring = (struct sw_monitor_ring *)rxdma_dst_ring_desc; struct buffer_addr_info *buf_addr_info; uint32_t *mpdu_info; uint32_t loop_cnt; struct hal_rx_mon_desc_info *desc_info; desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf; mpdu_info = (uint32_t *)&sw_mon_ring-> reo_level_mpdu_frame_info.rx_mpdu_desc_info_details; loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT); desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info); /* Get msdu link descriptor buf_addr_info */ buf_addr_info = &sw_mon_ring-> reo_level_mpdu_frame_info.msdu_link_desc_addr_info; desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET( buf_addr_info)) << 32); desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); buf_addr_info = &sw_mon_ring->status_buff_addr_info; desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) | ((uint64_t) (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32); desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_6, END_OF_PPDU); desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_6, STATUS_BUF_COUNT); desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_6, RXDMA_PUSH_REASON); desc_info->rxdma_error_code = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_6, RXDMA_ERROR_CODE); desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, PHY_PPDU_ID); } /** * hal_rx_msdu_start_nss_get_9000() - API to get the NSS from rx_msdu_start * @buf: pointer to the start of RX PKT TLV header * * Return: uint32_t(nss) */ static uint32_t hal_rx_msdu_start_nss_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; uint8_t mimo_ss_bitmap; mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); return qdf_get_hweight8(mimo_ss_bitmap); } /** * hal_rx_msdu_start_get_len_9000() - API to get the MSDU length from * rx_msdu_start TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: (uint32_t)msdu length */ static uint32_t hal_rx_msdu_start_get_len_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; uint32_t msdu_len; msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); return msdu_len; } /** * hal_rx_mon_hw_desc_get_mpdu_status_9000() - Retrieve MPDU status * @hw_desc_addr: Start address of Rx HW TLVs * @rs: Status for monitor mode * * Return: void */ static void hal_rx_mon_hw_desc_get_mpdu_status_9000(void *hw_desc_addr, struct mon_rx_status *rs) { struct rx_msdu_start *rx_msdu_start; struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; uint32_t reg_value; const uint32_t sgi_hw_to_cdp[] = { CDP_SGI_0_8_US, CDP_SGI_0_4_US, CDP_SGI_1_6_US, CDP_SGI_3_2_US, }; rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, USER_RSSI); rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); rs->sgi = sgi_hw_to_cdp[reg_value]; reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; /* TODO: rs->beamformed should be set for SU beamforming also */ } #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) /** * hal_get_link_desc_size_9000() - API to get the link desc size * * Return: uint32_t */ static uint32_t hal_get_link_desc_size_9000(void) { return LINK_DESC_SIZE; } /** * hal_rx_get_tlv_9000() - API to get the tlv * @rx_tlv: TLV data extracted from the rx packet * * Return: uint8_t */ static uint8_t hal_rx_get_tlv_9000(void *rx_tlv) { return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); } /** * hal_rx_mpdu_start_tlv_tag_valid_9000() - API to check if RX_MPDU_START tlv * tag is valid * @rx_tlv_hdr: start address of rx_pkt_tlvs * * Return: true if RX_MPDU_START is valid, else false. */ uint8_t hal_rx_mpdu_start_tlv_tag_valid_9000(void *rx_tlv_hdr) { struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; uint32_t tlv_tag; tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); return tlv_tag == WIFIRX_MPDU_START_E ? true : false; } /** * hal_rx_wbm_err_msdu_continuation_get_9000() - API to check if WBM msdu * continuation bit is set * @wbm_desc: wbm release ring descriptor * * Return: true if msdu continuation bit is set. */ uint8_t hal_rx_wbm_err_msdu_continuation_get_9000(void *wbm_desc) { uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) + WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; } /** * hal_rx_proc_phyrx_other_receive_info_tlv_9000() - API to get tlv info * @rx_tlv_hdr: RX TLV header * @ppdu_info_hdl: handle to PPDU info rto fill * * Return: None */ static inline void hal_rx_proc_phyrx_other_receive_info_tlv_9000(void *rx_tlv_hdr, void *ppdu_info_hdl) { } #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) static inline void hal_rx_get_bb_info_9000(void *rx_tlv, void *ppdu_info_hdl) { struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; ppdu_info->cfr_info.bb_captured_channel = HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); ppdu_info->cfr_info.bb_captured_timeout = HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); ppdu_info->cfr_info.bb_captured_reason = HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); } static inline void hal_rx_get_rtt_info_9000(void *rx_tlv, void *ppdu_info_hdl) { struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; ppdu_info->cfr_info.rx_location_info_valid = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, RTT_CHE_BUFFER_POINTER_LOW32); ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, RTT_CHE_BUFFER_POINTER_HIGH8); ppdu_info->cfr_info.chan_capture_status = GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv); ppdu_info->cfr_info.rx_start_ts = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, RX_START_TS); ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, RTT_CFO_MEASUREMENT); ppdu_info->cfr_info.agc_gain_info0 = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_1_RX_PKT_END_DETAILS, PHY_TIMESTAMP_1_LOWER_32); ppdu_info->cfr_info.agc_gain_info1 = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_2_RX_PKT_END_DETAILS, PHY_TIMESTAMP_1_UPPER_32); ppdu_info->cfr_info.agc_gain_info2 = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_3_RX_PKT_END_DETAILS, PHY_TIMESTAMP_2_LOWER_32); ppdu_info->cfr_info.agc_gain_info3 = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_4_RX_PKT_END_DETAILS, PHY_TIMESTAMP_2_UPPER_32); ppdu_info->cfr_info.mcs_rate = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, RTT_MCS_RATE); ppdu_info->cfr_info.gi_type = HAL_RX_GET(rx_tlv, PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, RTT_GI_TYPE); } #endif /** * hal_rx_dump_msdu_start_tlv_9000() - dump RX msdu_start TLV in structured * human readable format. * @pkttlvs: pointer to the pkttlvs. * @dbg_level: log level. * * Return: void */ static void hal_rx_dump_msdu_start_tlv_9000(void *pkttlvs, uint8_t dbg_level) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs; struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, "rx_msdu_start tlv - " "rxpcu_mpdu_filter_in_category: %d " "sw_frame_group_id: %d " "phy_ppdu_id: %d " "msdu_length: %d " "ipsec_esp: %d " "l3_offset: %d " "ipsec_ah: %d " "l4_offset: %d " "msdu_number: %d " "decap_format: %d " "ipv4_proto: %d " "ipv6_proto: %d " "tcp_proto: %d " "udp_proto: %d " "ip_frag: %d " "tcp_only_ack: %d " "da_is_bcast_mcast: %d " "ip4_protocol_ip6_next_header: %d " "toeplitz_hash_2_or_4: %d " "flow_id_toeplitz: %d " "user_rssi: %d " "pkt_type: %d " "stbc: %d " "sgi: %d " "rate_mcs: %d " "receive_bandwidth: %d " "reception_type: %d " "ppdu_start_timestamp: %d " "sw_phy_meta_data: %d ", msdu_start->rxpcu_mpdu_filter_in_category, msdu_start->sw_frame_group_id, msdu_start->phy_ppdu_id, msdu_start->msdu_length, msdu_start->ipsec_esp, msdu_start->l3_offset, msdu_start->ipsec_ah, msdu_start->l4_offset, msdu_start->msdu_number, msdu_start->decap_format, msdu_start->ipv4_proto, msdu_start->ipv6_proto, msdu_start->tcp_proto, msdu_start->udp_proto, msdu_start->ip_frag, msdu_start->tcp_only_ack, msdu_start->da_is_bcast_mcast, msdu_start->ip4_protocol_ip6_next_header, msdu_start->toeplitz_hash_2_or_4, msdu_start->flow_id_toeplitz, msdu_start->user_rssi, msdu_start->pkt_type, msdu_start->stbc, msdu_start->sgi, msdu_start->rate_mcs, msdu_start->receive_bandwidth, msdu_start->reception_type, msdu_start->ppdu_start_timestamp, msdu_start->sw_phy_meta_data); } /** * hal_rx_dump_msdu_end_tlv_9000() - dump RX msdu_end TLV in structured * human readable format. * @pkttlvs: pointer to the pkttlvs. * @dbg_level: log level. * * Return: void */ static void hal_rx_dump_msdu_end_tlv_9000(void *pkttlvs, uint8_t dbg_level) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, "rx_msdu_end tlv - " "rxpcu_mpdu_filter_in_category: %d " "sw_frame_group_id: %d " "phy_ppdu_id: %d " "ip_hdr_chksum: %d " "reported_mpdu_length: %d " "key_id_octet: %d " "cce_super_rule: %d " "cce_classify_not_done_truncat: %d " "cce_classify_not_done_cce_dis: %d " "rule_indication_31_0: %d " "rule_indication_63_32: %d " "da_offset: %d " "sa_offset: %d " "da_offset_valid: %d " "sa_offset_valid: %d " "ipv6_options_crc: %d " "tcp_seq_number: %d " "tcp_ack_number: %d " "tcp_flag: %d " "lro_eligible: %d " "window_size: %d " "tcp_udp_chksum: %d " "sa_idx_timeout: %d " "da_idx_timeout: %d " "msdu_limit_error: %d " "flow_idx_timeout: %d " "flow_idx_invalid: %d " "wifi_parser_error: %d " "amsdu_parser_error: %d " "sa_is_valid: %d " "da_is_valid: %d " "da_is_mcbc: %d " "l3_header_padding: %d " "first_msdu: %d " "last_msdu: %d " "sa_idx: %d " "msdu_drop: %d " "reo_destination_indication: %d " "flow_idx: %d " "fse_metadata: %d " "cce_metadata: %d " "sa_sw_peer_id: %d ", msdu_end->rxpcu_mpdu_filter_in_category, msdu_end->sw_frame_group_id, msdu_end->phy_ppdu_id, msdu_end->ip_hdr_chksum, msdu_end->reported_mpdu_length, msdu_end->key_id_octet, msdu_end->cce_super_rule, msdu_end->cce_classify_not_done_truncate, msdu_end->cce_classify_not_done_cce_dis, msdu_end->rule_indication_31_0, msdu_end->rule_indication_63_32, msdu_end->da_offset, msdu_end->sa_offset, msdu_end->da_offset_valid, msdu_end->sa_offset_valid, msdu_end->ipv6_options_crc, msdu_end->tcp_seq_number, msdu_end->tcp_ack_number, msdu_end->tcp_flag, msdu_end->lro_eligible, msdu_end->window_size, msdu_end->tcp_udp_chksum, msdu_end->sa_idx_timeout, msdu_end->da_idx_timeout, msdu_end->msdu_limit_error, msdu_end->flow_idx_timeout, msdu_end->flow_idx_invalid, msdu_end->wifi_parser_error, msdu_end->amsdu_parser_error, msdu_end->sa_is_valid, msdu_end->da_is_valid, msdu_end->da_is_mcbc, msdu_end->l3_header_padding, msdu_end->first_msdu, msdu_end->last_msdu, msdu_end->sa_idx, msdu_end->msdu_drop, msdu_end->reo_destination_indication, msdu_end->flow_idx, msdu_end->fse_metadata, msdu_end->cce_metadata, msdu_end->sa_sw_peer_id); } /** * hal_rx_mpdu_start_tid_get_9000() - API to get tid from rx_msdu_start * @buf: pointer to the start of RX PKT TLV header * * Return: uint32_t(tid value) */ static uint32_t hal_rx_mpdu_start_tid_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; uint32_t tid; tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); return tid; } /** * hal_rx_msdu_start_reception_type_get_9000() - API to get the reception type * from rx_msdu_start * @buf: pointer to the start of RX PKT TLV header * * Return: uint32_t(reception_type) */ static uint32_t hal_rx_msdu_start_reception_type_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start; uint32_t reception_type; reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); return reception_type; } /** * hal_rx_msdu_end_da_idx_get_9000() - API to get da_idx from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: da index */ static uint16_t hal_rx_msdu_end_da_idx_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; uint16_t da_idx; da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); return da_idx; } /** * hal_rx_get_rx_fragment_number_9000() - Function to retrieve rx fragment * number * @buf: Network buffer * * Return: rx fragment number */ static uint8_t hal_rx_get_rx_fragment_number_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); /* Return first 4 bits as fragment number */ return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & DOT11_SEQ_FRAG_MASK); } /** * hal_rx_msdu_end_da_is_mcbc_get_9000() - API to check if pkt is MCBC from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: da_is_mcbc */ static uint8_t hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); } /** * hal_rx_msdu_end_sa_is_valid_get_9000() - API to get the sa_is_valid bit * from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: sa_is_valid bit */ static uint8_t hal_rx_msdu_end_sa_is_valid_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; uint8_t sa_is_valid; sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); return sa_is_valid; } /** * hal_rx_msdu_end_sa_idx_get_9000() - API to get the sa_idx from rx_msdu_end * TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: sa_idx (SA AST index) */ static uint16_t hal_rx_msdu_end_sa_idx_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; uint16_t sa_idx; sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); return sa_idx; } /** * hal_rx_desc_is_first_msdu_9000() - Check if first msdu * @hw_desc_addr: hardware descriptor address * * Return: 0 - success/ non-zero failure */ static uint32_t hal_rx_desc_is_first_msdu_9000(void *hw_desc_addr) { struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); } /** * hal_rx_msdu_end_l3_hdr_padding_get_9000() - API to get the l3_header padding * from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: number of l3 header padding bytes */ static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; uint32_t l3_header_padding; l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); return l3_header_padding; } /** * hal_rx_encryption_info_valid_9000() - Returns encryption type. * @buf: rx_tlv_hdr of the received packet * * Return: encryption type */ inline uint32_t hal_rx_encryption_info_valid_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); return encryption_info; } /** * hal_rx_print_pn_9000() - Prints the PN of rx packet. * @buf: rx_tlv_hdr of the received packet * * Return: void */ static void hal_rx_print_pn_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x", pn_127_96, pn_95_64, pn_63_32, pn_31_0); } /** * hal_rx_msdu_end_first_msdu_get_9000() - API to get first msdu status from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: first_msdu */ static uint8_t hal_rx_msdu_end_first_msdu_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; uint8_t first_msdu; first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); return first_msdu; } /** * hal_rx_msdu_end_da_is_valid_get_9000() - API to check if da is valid from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: da_is_valid */ static uint8_t hal_rx_msdu_end_da_is_valid_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; uint8_t da_is_valid; da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); return da_is_valid; } /** * hal_rx_msdu_end_last_msdu_get_9000() - API to get last msdu status from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: last_msdu */ static uint8_t hal_rx_msdu_end_last_msdu_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; uint8_t last_msdu; last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); return last_msdu; } /** * hal_rx_get_mpdu_mac_ad4_valid_9000() - Retrieves if mpdu 4th addr is valid * @buf: Network buffer * * Return: value of mpdu 4th address valid field */ inline bool hal_rx_get_mpdu_mac_ad4_valid_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); bool ad4_valid = 0; ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); return ad4_valid; } /** * hal_rx_mpdu_start_sw_peer_id_get_9000() - Retrieve sw peer_id * @buf: network buffer * * Return: sw peer_id */ static uint32_t hal_rx_mpdu_start_sw_peer_id_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( &mpdu_start->rx_mpdu_info_details); } /** * hal_rx_mpdu_get_to_ds_9000() - API to get the tods info from rx_mpdu_start * @buf: pointer to the start of RX PKT TLV header * * Return: uint32_t(to_ds) */ static uint32_t hal_rx_mpdu_get_to_ds_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; return HAL_RX_MPDU_GET_TODS(mpdu_info); } /** * hal_rx_mpdu_get_fr_ds_9000() - API to get the from ds info from rx_mpdu_start * @buf: pointer to the start of RX PKT TLV header * * Return: uint32_t(fr_ds) */ static uint32_t hal_rx_mpdu_get_fr_ds_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; return HAL_RX_MPDU_GET_FROMDS(mpdu_info); } /** * hal_rx_get_mpdu_frame_control_valid_9000() - Retrieves mpdu frame control * valid * @buf: Network buffer * * Return: value of frame control valid field */ static uint8_t hal_rx_get_mpdu_frame_control_valid_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); } /** * hal_rx_get_mpdu_frame_control_field_9000() - Function to retrieve frame * control field * @buf: Network buffer * * Return: value of frame control field * */ static uint16_t hal_rx_get_mpdu_frame_control_field_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); uint16_t frame_ctrl = 0; frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); return frame_ctrl; } /** * hal_rx_mpdu_get_addr1_9000() - API to check get address1 of the mpdu * @buf: pointer to the start of RX PKT TLV headera * @mac_addr: pointer to mac address * * Return: success/failure */ static QDF_STATUS hal_rx_mpdu_get_addr1_9000(uint8_t *buf, uint8_t *mac_addr) { struct __attribute__((__packed__)) hal_addr1 { uint32_t ad1_31_0; uint16_t ad1_47_32; }; struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; uint32_t mac_addr_ad1_valid; mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); if (mac_addr_ad1_valid) { addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); return QDF_STATUS_SUCCESS; } return QDF_STATUS_E_FAILURE; } /** * hal_rx_mpdu_get_addr2_9000() - API to check get address2 of the mpdu in the * packet * @buf: pointer to the start of RX PKT TLV header * @mac_addr: pointer to mac address * * Return: success/failure */ static QDF_STATUS hal_rx_mpdu_get_addr2_9000(uint8_t *buf, uint8_t *mac_addr) { struct __attribute__((__packed__)) hal_addr2 { uint16_t ad2_15_0; uint32_t ad2_47_16; }; struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; uint32_t mac_addr_ad2_valid; mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); if (mac_addr_ad2_valid) { addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); return QDF_STATUS_SUCCESS; } return QDF_STATUS_E_FAILURE; } /** * hal_rx_mpdu_get_addr3_9000() - API to get address3 of the mpdu in the packet * @buf: pointer to the start of RX PKT TLV header * @mac_addr: pointer to mac address * * Return: success/failure */ static QDF_STATUS hal_rx_mpdu_get_addr3_9000(uint8_t *buf, uint8_t *mac_addr) { struct __attribute__((__packed__)) hal_addr3 { uint32_t ad3_31_0; uint16_t ad3_47_32; }; struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; uint32_t mac_addr_ad3_valid; mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); if (mac_addr_ad3_valid) { addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); return QDF_STATUS_SUCCESS; } return QDF_STATUS_E_FAILURE; } /** * hal_rx_mpdu_get_addr4_9000() - API to get address4 of the mpdu in the packet * @buf: pointer to the start of RX PKT TLV header * @mac_addr: pointer to mac address * * Return: success/failure */ static QDF_STATUS hal_rx_mpdu_get_addr4_9000(uint8_t *buf, uint8_t *mac_addr) { struct __attribute__((__packed__)) hal_addr4 { uint32_t ad4_31_0; uint16_t ad4_47_32; }; struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; uint32_t mac_addr_ad4_valid; mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); if (mac_addr_ad4_valid) { addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); return QDF_STATUS_SUCCESS; } return QDF_STATUS_E_FAILURE; } /** * hal_rx_get_mpdu_sequence_control_valid_9000() - Get mpdu sequence control * valid * @buf: Network buffer * * Return: value of sequence control valid field */ static uint8_t hal_rx_get_mpdu_sequence_control_valid_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); } /** * hal_rx_is_unicast_9000() - check packet is unicast frame or not. * @buf: pointer to rx pkt TLV. * * Return: true on unicast. */ static bool hal_rx_is_unicast_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; uint32_t grp_id; uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; } /** * hal_rx_tid_get_9000() - get tid based on qos control valid. * @hal_soc_hdl: hal soc handle * @buf: pointer to rx pkt TLV. * * Return: tid */ static uint32_t hal_rx_tid_get_9000(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; uint8_t qos_control_valid = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); if (qos_control_valid) return hal_rx_mpdu_start_tid_get_9000(buf); return HAL_RX_NON_QOS_TID; } /** * hal_rx_hw_desc_get_ppduid_get_9000() - retrieve ppdu id * @rx_tlv_hdr: rx tlv header * @rxdma_dst_ring_desc: rxdma HW descriptor * * Return: ppdu id */ static uint32_t hal_rx_hw_desc_get_ppduid_get_9000(void *rx_tlv_hdr, void *rxdma_dst_ring_desc) { struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; return reo_ent->phy_ppdu_id; } /** * hal_reo_status_get_header_9000() - Process reo desc info * @ring_desc: REO status ring descriptor * @b: tlv type info * @h1: Pointer to hal_reo_status_header where info to be stored * * Return: none. * */ static void hal_reo_status_get_header_9000(hal_ring_desc_t ring_desc, int b, void *h1) { uint32_t *d = (uint32_t *)ring_desc; uint32_t val1 = 0; struct hal_reo_status_header *h = (struct hal_reo_status_header *)h1; /* Offsets of descriptor fields defined in HW headers start * from the field after TLV header */ d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); switch (b) { case HAL_REO_QUEUE_STATS_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; break; case HAL_REO_FLUSH_QUEUE_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; break; case HAL_REO_FLUSH_CACHE_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; break; case HAL_REO_UNBLK_CACHE_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; break; case HAL_REO_TIMOUT_LIST_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; break; case HAL_REO_DESC_THRES_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; break; case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; break; default: qdf_nofl_err("ERROR: Unknown tlv\n"); break; } h->cmd_num = HAL_GET_FIELD( UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, val1); h->exec_time = HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, CMD_EXECUTION_TIME, val1); h->status = HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, REO_CMD_EXECUTION_STATUS, val1); switch (b) { case HAL_REO_QUEUE_STATS_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; break; case HAL_REO_FLUSH_QUEUE_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; break; case HAL_REO_FLUSH_CACHE_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; break; case HAL_REO_UNBLK_CACHE_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; break; case HAL_REO_TIMOUT_LIST_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; break; case HAL_REO_DESC_THRES_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; break; case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; break; default: qdf_nofl_err("ERROR: Unknown tlv\n"); break; } h->tstamp = HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); } /** * hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000() - Retrieve qos control * valid bit from the tlv. * @buf: pointer to rx pkt TLV. * * Return: qos control value. */ static inline uint32_t hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_mpdu_start *mpdu_start = &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( &mpdu_start->rx_mpdu_info_details); } /** * hal_rx_msdu_end_sa_sw_peer_id_get_9000() - API to get the sa_sw_peer_id from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: sa_sw_peer_id index */ static inline uint32_t hal_rx_msdu_end_sa_sw_peer_id_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); } /** * hal_tx_desc_set_mesh_en_9000() - Set mesh_enable flag in Tx descriptor * @desc: Handle to Tx Descriptor * @en: For raw WiFi frames, this indicates transmission to a mesh STA, * enabling the interpretation of the 'Mesh Control Present' bit * (bit 8) of QoS Control (otherwise this bit is ignored), * For native WiFi frames, this indicates that a 'Mesh Control' field * is present between the header and the LLC. * * Return: void */ static inline void hal_tx_desc_set_mesh_en_9000(void *desc, uint8_t en) { HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); } static void *hal_rx_msdu0_buffer_addr_lsb_9000(void *link_desc_va) { return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); } static void *hal_rx_msdu_desc_info_ptr_get_9000(void *msdu0) { return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); } static void *hal_ent_mpdu_desc_info_9000(void *ent_ring_desc) { return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); } static void *hal_dst_mpdu_desc_info_9000(void *dst_ring_desc) { return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); } static uint8_t hal_rx_get_fc_valid_9000(uint8_t *buf) { return HAL_RX_GET_FC_VALID(buf); } static uint8_t hal_rx_get_to_ds_flag_9000(uint8_t *buf) { return HAL_RX_GET_TO_DS_FLAG(buf); } static uint8_t hal_rx_get_mac_addr2_valid_9000(uint8_t *buf) { return HAL_RX_GET_MAC_ADDR2_VALID(buf); } static uint8_t hal_rx_get_filter_category_9000(uint8_t *buf) { return HAL_RX_GET_FILTER_CATEGORY(buf); } static uint32_t hal_rx_get_ppdu_id_9000(uint8_t *buf) { struct rx_mpdu_info *rx_mpdu_info; struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; rx_mpdu_info = &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; return HAL_RX_GET_PPDU_ID(rx_mpdu_info); } /** * hal_reo_config_9000() - Set reo config parameters * @soc: hal soc handle * @reg_val: value to be set * @reo_params: reo parameters * * Return: void */ static void hal_reo_config_9000(struct hal_soc *soc, uint32_t reg_val, struct hal_reo_params *reo_params) { HAL_REO_R0_CONFIG(soc, reg_val, reo_params); } /** * hal_rx_msdu_desc_info_get_ptr_9000() - Get msdu desc info ptr * @msdu_details_ptr: Pointer to msdu_details_ptr * * Return: Pointer to rx_msdu_desc_info structure. * */ static void *hal_rx_msdu_desc_info_get_ptr_9000(void *msdu_details_ptr) { return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); } /** * hal_rx_link_desc_msdu0_ptr_9000() - Get pointer to rx_msdu details * @link_desc: Pointer to link desc * * Return: Pointer to rx_msdu_details structure * */ static void *hal_rx_link_desc_msdu0_ptr_9000(void *link_desc) { return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); } /** * hal_rx_msdu_flow_idx_get_9000() - API to get flow index from rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: flow index value from MSDU END TLV */ static inline uint32_t hal_rx_msdu_flow_idx_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); } /** * hal_rx_msdu_flow_idx_invalid_9000() - API to get flow index invalid from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: flow index invalid value from MSDU END TLV */ static bool hal_rx_msdu_flow_idx_invalid_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); } /** * hal_rx_msdu_flow_idx_timeout_9000() - API to get flow index timeout from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: flow index timeout value from MSDU END TLV */ static bool hal_rx_msdu_flow_idx_timeout_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); } /** * hal_rx_msdu_fse_metadata_get_9000() - API to get FSE metadata from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: fse metadata value from MSDU END TLV */ static uint32_t hal_rx_msdu_fse_metadata_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); } /** * hal_rx_msdu_cce_metadata_get_9000() - API to get CCE metadata from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * * Return: cce_metadata */ static uint16_t hal_rx_msdu_cce_metadata_get_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); } /** * hal_rx_msdu_get_flow_params_9000() - API to get flow index, flow index * invalid and flow index timeout from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * @flow_invalid: pointer to return value of flow_idx_valid * @flow_timeout: pointer to return value of flow_idx_timeout * @flow_index: pointer to return value of flow_idx * * Return: none */ static inline void hal_rx_msdu_get_flow_params_9000(uint8_t *buf, bool *flow_invalid, bool *flow_timeout, uint32_t *flow_index) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); } /** * hal_rx_tlv_get_tcp_chksum_9000() - API to get tcp checksum * @buf: rx_tlv_hdr * * Return: tcp checksum */ static uint16_t hal_rx_tlv_get_tcp_chksum_9000(uint8_t *buf) { return HAL_RX_TLV_GET_TCP_CHKSUM(buf); } /** * hal_rx_get_rx_sequence_9000() - Function to retrieve rx sequence number * @buf: Network buffer * * Return: rx sequence number */ static uint16_t hal_rx_get_rx_sequence_9000(uint8_t *buf) { struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); } /** * hal_get_window_address_9000() - Function to get hp/tp address * @hal_soc: Pointer to hal_soc * @addr: address offset of register * * Return: modified address offset of register */ static inline qdf_iomem_t hal_get_window_address_9000(struct hal_soc *hal_soc, qdf_iomem_t addr) { uint32_t offset = addr - hal_soc->dev_base_addr; qdf_iomem_t new_offset; /* * If offset lies within DP register range, use 3rd window to write * into DP region. */ if ((offset ^ SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) { new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) + (offset & WINDOW_RANGE_MASK)); /* * If offset lies within CE register range, use 2nd window to write * into CE region. */ } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + (offset & WINDOW_RANGE_MASK)); } else { QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, "%s: ERROR: Accessing Wrong register\n", __func__); qdf_assert_always(0); return 0; } return new_offset; } static inline void hal_write_window_register(struct hal_soc *hal_soc) { /* Write value into window configuration register */ qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, WINDOW_CONFIGURATION_VALUE_9000); } /** * hal_rx_msdu_packet_metadata_get_9000() - API to get the msdu information from * rx_msdu_end TLV * @buf: pointer to the start of RX PKT TLV headers * @msdu_pkt_metadata: pointer to the msdu info structure */ static void hal_rx_msdu_packet_metadata_get_9000(uint8_t *buf, void *msdu_pkt_metadata) { struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; struct hal_rx_msdu_metadata *msdu_metadata = (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; msdu_metadata->l3_hdr_pad = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); msdu_metadata->sa_sw_peer_id = HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); } /** * hal_rx_flow_setup_fse_9000() - Setup a flow search entry in HW FST * @rx_fst: Pointer to the Rx Flow Search Table * @table_offset: offset into the table where the flow is to be setup * @rx_flow: Flow Parameters * * Return: Success/Failure */ static void * hal_rx_flow_setup_fse_9000(uint8_t *rx_fst, uint32_t table_offset, uint8_t *rx_flow) { struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; uint8_t *fse; bool fse_valid; if (table_offset >= fst->max_entries) { QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, "HAL FSE table offset %u exceeds max entries %u", table_offset, fst->max_entries); return NULL; } fse = (uint8_t *)fst->base_vaddr + (table_offset * HAL_RX_FST_ENTRY_SIZE); fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); if (fse_valid) { QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, "HAL FSE %pK already valid", fse); return NULL; } HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, qdf_htonl(flow->tuple_info.src_ip_127_96)); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, qdf_htonl(flow->tuple_info.src_ip_95_64)); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, qdf_htonl(flow->tuple_info.src_ip_63_32)); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, qdf_htonl(flow->tuple_info.src_ip_31_0)); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, qdf_htonl(flow->tuple_info.dest_ip_127_96)); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, qdf_htonl(flow->tuple_info.dest_ip_95_64)); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, qdf_htonl(flow->tuple_info.dest_ip_63_32)); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, qdf_htonl(flow->tuple_info.dest_ip_31_0)); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, (flow->tuple_info.dest_port)); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, (flow->tuple_info.src_port)); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, flow->tuple_info.l4_protocol); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, flow->reo_destination_handler); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, flow->fse_metadata); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION, flow->reo_destination_indication); /* Reset all the other fields in FSE */ HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); return fse; } static void hal_compute_reo_remap_ix2_ix3_9000(uint32_t *ring, uint32_t num_rings, uint32_t *remap1, uint32_t *remap2) { switch (num_rings) { case 1: *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | HAL_REO_REMAP_IX2(ring[0], 17) | HAL_REO_REMAP_IX2(ring[0], 18) | HAL_REO_REMAP_IX2(ring[0], 19) | HAL_REO_REMAP_IX2(ring[0], 20) | HAL_REO_REMAP_IX2(ring[0], 21) | HAL_REO_REMAP_IX2(ring[0], 22) | HAL_REO_REMAP_IX2(ring[0], 23); *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | HAL_REO_REMAP_IX3(ring[0], 25) | HAL_REO_REMAP_IX3(ring[0], 26) | HAL_REO_REMAP_IX3(ring[0], 27) | HAL_REO_REMAP_IX3(ring[0], 28) | HAL_REO_REMAP_IX3(ring[0], 29) | HAL_REO_REMAP_IX3(ring[0], 30) | HAL_REO_REMAP_IX3(ring[0], 31); break; case 2: *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | HAL_REO_REMAP_IX2(ring[0], 17) | HAL_REO_REMAP_IX2(ring[1], 18) | HAL_REO_REMAP_IX2(ring[1], 19) | HAL_REO_REMAP_IX2(ring[0], 20) | HAL_REO_REMAP_IX2(ring[0], 21) | HAL_REO_REMAP_IX2(ring[1], 22) | HAL_REO_REMAP_IX2(ring[1], 23); *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | HAL_REO_REMAP_IX3(ring[0], 25) | HAL_REO_REMAP_IX3(ring[1], 26) | HAL_REO_REMAP_IX3(ring[1], 27) | HAL_REO_REMAP_IX3(ring[0], 28) | HAL_REO_REMAP_IX3(ring[0], 29) | HAL_REO_REMAP_IX3(ring[1], 30) | HAL_REO_REMAP_IX3(ring[1], 31); break; case 3: *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | HAL_REO_REMAP_IX2(ring[1], 17) | HAL_REO_REMAP_IX2(ring[2], 18) | HAL_REO_REMAP_IX2(ring[0], 19) | HAL_REO_REMAP_IX2(ring[1], 20) | HAL_REO_REMAP_IX2(ring[2], 21) | HAL_REO_REMAP_IX2(ring[0], 22) | HAL_REO_REMAP_IX2(ring[1], 23); *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | HAL_REO_REMAP_IX3(ring[0], 25) | HAL_REO_REMAP_IX3(ring[1], 26) | HAL_REO_REMAP_IX3(ring[2], 27) | HAL_REO_REMAP_IX3(ring[0], 28) | HAL_REO_REMAP_IX3(ring[1], 29) | HAL_REO_REMAP_IX3(ring[2], 30) | HAL_REO_REMAP_IX3(ring[0], 31); break; case 4: *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | HAL_REO_REMAP_IX2(ring[1], 17) | HAL_REO_REMAP_IX2(ring[2], 18) | HAL_REO_REMAP_IX2(ring[3], 19) | HAL_REO_REMAP_IX2(ring[0], 20) | HAL_REO_REMAP_IX2(ring[1], 21) | HAL_REO_REMAP_IX2(ring[2], 22) | HAL_REO_REMAP_IX2(ring[3], 23); *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | HAL_REO_REMAP_IX3(ring[1], 25) | HAL_REO_REMAP_IX3(ring[2], 26) | HAL_REO_REMAP_IX3(ring[3], 27) | HAL_REO_REMAP_IX3(ring[0], 28) | HAL_REO_REMAP_IX3(ring[1], 29) | HAL_REO_REMAP_IX3(ring[2], 30) | HAL_REO_REMAP_IX3(ring[3], 31); break; } } static void hal_hw_txrx_ops_attach_qcn9000(struct hal_soc *hal_soc) { /* init and setup */ hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; hal_soc->ops->hal_get_window_address = hal_get_window_address_9000; /* tx */ hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = hal_tx_desc_set_dscp_tid_table_id_9000; hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9000; hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9000; hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_9000; hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic_li; hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic_li; hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic_li; hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic_li; hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic_li; hal_soc->ops->hal_tx_comp_get_release_reason = hal_tx_comp_get_release_reason_generic_li; hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic_li; hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_9000; hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_9000; /* rx */ hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_9000; hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = hal_rx_mon_hw_desc_get_mpdu_status_9000; hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9000; hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = hal_rx_proc_phyrx_other_receive_info_tlv_9000; hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9000; hal_soc->ops->hal_rx_dump_rx_attention_tlv = hal_rx_dump_rx_attention_tlv_generic_li; hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_9000; hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic_li; hal_soc->ops->hal_rx_dump_mpdu_end_tlv = hal_rx_dump_mpdu_end_tlv_generic_li; hal_soc->ops->hal_rx_dump_pkt_hdr_tlv = hal_rx_dump_pkt_hdr_tlv_generic_li; hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9000; hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_9000; hal_soc->ops->hal_rx_msdu_start_reception_type_get = hal_rx_msdu_start_reception_type_get_9000; hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_9000; hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_9000; hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_9000; hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_9000; hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic_li; hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic_li; hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic_li; hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic_li; hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic_li; hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_9000; hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_9000; hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_9000; hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_9000; hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_9000; hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = hal_rx_msdu_end_l3_hdr_padding_get_9000; hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_9000; hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_9000; hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_9000; hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_9000; hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_9000; hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_9000; hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = hal_rx_mpdu_start_sw_peer_id_get_9000; hal_soc->ops->hal_rx_tlv_peer_meta_data_get = hal_rx_mpdu_peer_meta_data_get_li; hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_9000; hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_9000; hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = hal_rx_get_mpdu_frame_control_valid_9000; hal_soc->ops->hal_rx_get_frame_ctrl_field = hal_rx_get_mpdu_frame_control_field_9000; hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_9000; hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_9000; hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_9000; hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_9000; hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = hal_rx_get_mpdu_sequence_control_valid_9000; hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_9000; hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_9000; hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_9000; hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000; hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = hal_rx_msdu_end_sa_sw_peer_id_get_9000; hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_9000; hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_9000; hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9000; hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9000; hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_9000; hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_9000; hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_9000; hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_9000; hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_9000; hal_soc->ops->hal_reo_config = hal_reo_config_9000; hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_9000; hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_9000; hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_9000; hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_9000; hal_soc->ops->hal_rx_msdu_cce_match_get = hal_rx_msdu_cce_match_get_li; hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_9000; hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_9000; hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_9000; hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_9000; #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9000; hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9000; #endif /* rx - msdu fast path info fields */ hal_soc->ops->hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_9000; hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_9000; hal_soc->ops->hal_rx_sw_mon_desc_info_get = hal_rx_sw_mon_desc_info_get_9000; hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = hal_rx_wbm_err_msdu_continuation_get_9000; /* rx - TLV struct offsets */ hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic; hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic; hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic; hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic; #ifndef NO_RX_PKT_HDR_TLV hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic; #endif hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9000; hal_soc->ops->hal_rx_flow_get_tuple_info = hal_rx_flow_get_tuple_info_li; hal_soc->ops->hal_rx_flow_delete_entry = hal_rx_flow_delete_entry_li; hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_9000; hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic_li; hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li; hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li; hal_soc->ops->hal_rx_tlv_decrypt_err_get = hal_rx_tlv_decrypt_err_get_li; hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags = hal_rx_tlv_get_pkt_capture_flags_li; hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = hal_rx_mpdu_info_ampdu_flag_get_li; hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; hal_soc->ops->hal_rx_tlv_msdu_len_get = hal_rx_msdu_start_get_len_9000; }; struct hal_hw_srng_config hw_srng_table_9000[] = { /* TODO: max_rings can populated by querying HW capabilities */ { /* REO_DST */ .start_ring_id = HAL_SRNG_REO2SW1, .max_rings = 4, .entry_size = sizeof(struct reo_destination_ring) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_DST_RING, .reg_start = { HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET), HWIO_REO_R2_REO2SW1_RING_HP_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET) }, .reg_size = { HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), }, .max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* REO_EXCEPTION */ /* Designating REO2TCL ring as exception ring. This ring is * similar to other REO2SW rings though it is named as REO2TCL. * Any of theREO2SW rings can be used as exception ring. */ .start_ring_id = HAL_SRNG_REO2TCL, .max_rings = 1, .entry_size = sizeof(struct reo_destination_ring) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_DST_RING, .reg_start = { HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET), HWIO_REO_R2_REO2TCL_RING_HP_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET) }, /* Single ring - provide ring size if multiple rings of this * type are supported */ .reg_size = {}, .max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* REO_REINJECT */ .start_ring_id = HAL_SRNG_SW2REO, .max_rings = 1, .entry_size = sizeof(struct reo_entrance_ring) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, .reg_start = { HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET), HWIO_REO_R2_SW2REO_RING_HP_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET) }, /* Single ring - provide ring size if multiple rings of this * type are supported */ .reg_size = {}, .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* REO_CMD */ .start_ring_id = HAL_SRNG_REO_CMD, .max_rings = 1, .entry_size = (sizeof(struct tlv_32_hdr) + sizeof(struct reo_get_queue_stats)) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, .reg_start = { HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET), HWIO_REO_R2_REO_CMD_RING_HP_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET), }, /* Single ring - provide ring size if multiple rings of this * type are supported */ .reg_size = {}, .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* REO_STATUS */ .start_ring_id = HAL_SRNG_REO_STATUS, .max_rings = 1, .entry_size = (sizeof(struct tlv_32_hdr) + sizeof(struct reo_get_queue_stats_status)) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_DST_RING, .reg_start = { HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET), HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( SEQ_WCSS_UMAC_REO_REG_OFFSET), }, /* Single ring - provide ring size if multiple rings of this * type are supported */ .reg_size = {}, .max_size = HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* TCL_DATA */ .start_ring_id = HAL_SRNG_SW2TCL1, .max_rings = 3, .entry_size = (sizeof(struct tlv_32_hdr) + sizeof(struct tcl_data_cmd)) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, .reg_start = { HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), }, .reg_size = { HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), }, .max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* TCL_CMD/CREDIT */ /* qca8074v2 and qcn9000 uses this ring for data commands */ .start_ring_id = HAL_SRNG_SW2TCL_CMD, .max_rings = 1, .entry_size = (sizeof(struct tlv_32_hdr) + sizeof(struct tcl_data_cmd)) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, .reg_start = { HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), }, /* Single ring - provide ring size if multiple rings of this * type are supported */ .reg_size = {}, .max_size = HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* TCL_STATUS */ .start_ring_id = HAL_SRNG_TCL_STATUS, .max_rings = 1, .entry_size = (sizeof(struct tlv_32_hdr) + sizeof(struct tcl_status_ring)) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_DST_RING, .reg_start = { HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), }, /* Single ring - provide ring size if multiple rings of this * type are supported */ .reg_size = {}, .max_size = HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* CE_SRC */ .start_ring_id = HAL_SRNG_CE_0_SRC, .max_rings = 12, .entry_size = sizeof(struct ce_src_desc) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, .reg_start = { HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), }, .reg_size = { SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, }, .max_size = HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* CE_DST */ .start_ring_id = HAL_SRNG_CE_0_DST, .max_rings = 12, .entry_size = 8 >> 2, /*TODO: entry_size above should actually be * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition * of struct ce_dst_desc in HW header files */ .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, .reg_start = { HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), }, .reg_size = { SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, }, .max_size = HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* CE_DST_STATUS */ .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, .max_rings = 12, .entry_size = sizeof(struct ce_stat_desc) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_DST_RING, .reg_start = { HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), }, /* TODO: check destination status ring registers */ .reg_size = { SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, }, .max_size = HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* WBM_IDLE_LINK */ .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, .max_rings = 1, .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, .reg_start = { HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), }, /* Single ring - provide ring size if multiple rings of this * type are supported */ .reg_size = {}, .max_size = HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* SW2WBM_RELEASE */ .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, .max_rings = 1, .entry_size = sizeof(struct wbm_release_ring) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, .reg_start = { HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), }, /* Single ring - provide ring size if multiple rings of this * type are supported */ .reg_size = {}, .max_size = HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* WBM2SW_RELEASE */ .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, .max_rings = 5, .entry_size = sizeof(struct wbm_release_ring) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_DST_RING, .reg_start = { HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), }, .reg_size = { HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), }, .max_size = HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, }, { /* RXDMA_BUF */ .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, #ifdef IPA_OFFLOAD #ifdef IPA_WDI3_VLAN_SUPPORT .max_rings = 4, #else .max_rings = 3, #endif #else .max_rings = 2, #endif .entry_size = sizeof(struct wbm_buffer_ring) >> 2, .lmac_ring = TRUE, .ring_dir = HAL_SRNG_SRC_RING, /* reg_start is not set because LMAC rings are not accessed * from host */ .reg_start = {}, .reg_size = {}, .max_size = HAL_RXDMA_MAX_RING_SIZE, }, { /* RXDMA_DST */ .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, .max_rings = 1, .entry_size = sizeof(struct reo_entrance_ring) >> 2, .lmac_ring = TRUE, .ring_dir = HAL_SRNG_DST_RING, /* reg_start is not set because LMAC rings are not accessed * from host */ .reg_start = {}, .reg_size = {}, .max_size = HAL_RXDMA_MAX_RING_SIZE, }, { /* RXDMA_MONITOR_BUF */ .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, .max_rings = 1, .entry_size = sizeof(struct wbm_buffer_ring) >> 2, .lmac_ring = TRUE, .ring_dir = HAL_SRNG_SRC_RING, /* reg_start is not set because LMAC rings are not accessed * from host */ .reg_start = {}, .reg_size = {}, .max_size = HAL_RXDMA_MAX_RING_SIZE, }, { /* RXDMA_MONITOR_STATUS */ .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, .max_rings = 1, .entry_size = sizeof(struct wbm_buffer_ring) >> 2, .lmac_ring = TRUE, .ring_dir = HAL_SRNG_SRC_RING, /* reg_start is not set because LMAC rings are not accessed * from host */ .reg_start = {}, .reg_size = {}, .max_size = HAL_RXDMA_MAX_RING_SIZE, }, { /* RXDMA_MONITOR_DST */ .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, .max_rings = 1, .entry_size = sizeof(struct sw_monitor_ring) >> 2, .lmac_ring = TRUE, .ring_dir = HAL_SRNG_DST_RING, /* reg_start is not set because LMAC rings are not accessed * from host */ .reg_start = {}, .reg_size = {}, .max_size = HAL_RXDMA_MAX_RING_SIZE, }, { /* RXDMA_MONITOR_DESC */ .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, .max_rings = 1, .entry_size = sizeof(struct wbm_buffer_ring) >> 2, .lmac_ring = TRUE, .ring_dir = HAL_SRNG_SRC_RING, /* reg_start is not set because LMAC rings are not accessed * from host */ .reg_start = {}, .reg_size = {}, .max_size = HAL_RXDMA_MAX_RING_SIZE, }, { /* DIR_BUF_RX_DMA_SRC */ .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, /* one ring for spectral and one ring for cfr */ .max_rings = 2, .entry_size = 2, .lmac_ring = TRUE, .ring_dir = HAL_SRNG_SRC_RING, /* reg_start is not set because LMAC rings are not accessed * from host */ .reg_start = {}, .reg_size = {}, .max_size = HAL_RXDMA_MAX_RING_SIZE, }, #ifdef WLAN_FEATURE_CIF_CFR { /* WIFI_POS_SRC */ .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, .max_rings = 1, .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, .lmac_ring = TRUE, .ring_dir = HAL_SRNG_SRC_RING, /* reg_start is not set because LMAC rings are not accessed * from host */ .reg_start = {}, .reg_size = {}, .max_size = HAL_RXDMA_MAX_RING_SIZE, }, #endif { /* REO2PPE */ 0}, { /* PPE2TCL */ 0}, { /* PPE_RELEASE */ 0}, { /* TX_MONITOR_BUF */ 0}, { /* TX_MONITOR_DST */ 0}, { /* SW2RXDMA_NEW */ 0}, { /* SW2RXDMA_LINK_RELEASE */ 0}, }; /** * hal_qcn9000_attach()- Attach 9000 target specific hal_soc ops, offset and * srng table * @hal_soc: HAL SoC context * * Return: void */ void hal_qcn9000_attach(struct hal_soc *hal_soc) { hal_soc->hw_srng_table = hw_srng_table_9000; hal_srng_hw_reg_offset_init_generic(hal_soc); hal_hw_txrx_default_ops_attach_li(hal_soc); hal_hw_txrx_ops_attach_qcn9000(hal_soc); if (hal_soc->static_window_map) hal_write_window_register(hal_soc); }