1 /*
2  * ADF4350/ADF4351 SPI PLL driver
3  *
4  * Copyright 2012-2013 Analog Devices Inc.
5  *
6  * Licensed under the GPL-2.
7  */
8 
9 #ifndef IIO_PLL_ADF4350_H_
10 #define IIO_PLL_ADF4350_H_
11 
12 /* Registers */
13 #define ADF4350_REG0	0
14 #define ADF4350_REG1	1
15 #define ADF4350_REG2	2
16 #define ADF4350_REG3	3
17 #define ADF4350_REG4	4
18 #define ADF4350_REG5	5
19 
20 /* REG0 Bit Definitions */
21 #define ADF4350_REG0_FRACT(x)			(((x) & 0xFFF) << 3)
22 #define ADF4350_REG0_INT(x)			(((x) & 0xFFFF) << 15)
23 
24 /* REG1 Bit Definitions */
25 #define ADF4350_REG1_MOD(x)			(((x) & 0xFFF) << 3)
26 #define ADF4350_REG1_PHASE(x)			(((x) & 0xFFF) << 15)
27 #define ADF4350_REG1_PRESCALER			(1 << 27)
28 
29 /* REG2 Bit Definitions */
30 #define ADF4350_REG2_COUNTER_RESET_EN		(1 << 3)
31 #define ADF4350_REG2_CP_THREESTATE_EN		(1 << 4)
32 #define ADF4350_REG2_POWER_DOWN_EN		(1 << 5)
33 #define ADF4350_REG2_PD_POLARITY_POS		(1 << 6)
34 #define ADF4350_REG2_LDP_6ns			(1 << 7)
35 #define ADF4350_REG2_LDP_10ns			(0 << 7)
36 #define ADF4350_REG2_LDF_FRACT_N		(0 << 8)
37 #define ADF4350_REG2_LDF_INT_N			(1 << 8)
38 #define ADF4350_REG2_CHARGE_PUMP_CURR_uA(x)	(((((x)-312) / 312) & 0xF) << 9)
39 #define ADF4350_REG2_DOUBLE_BUFF_EN		(1 << 13)
40 #define ADF4350_REG2_10BIT_R_CNT(x)		((x) << 14)
41 #define ADF4350_REG2_RDIV2_EN			(1 << 24)
42 #define ADF4350_REG2_RMULT2_EN			(1 << 25)
43 #define ADF4350_REG2_MUXOUT(x)			((x) << 26)
44 #define ADF4350_REG2_NOISE_MODE(x)		(((unsigned)(x)) << 29)
45 #define ADF4350_MUXOUT_THREESTATE		0
46 #define ADF4350_MUXOUT_DVDD			1
47 #define ADF4350_MUXOUT_GND			2
48 #define ADF4350_MUXOUT_R_DIV_OUT		3
49 #define ADF4350_MUXOUT_N_DIV_OUT		4
50 #define ADF4350_MUXOUT_ANALOG_LOCK_DETECT	5
51 #define ADF4350_MUXOUT_DIGITAL_LOCK_DETECT	6
52 
53 /* REG3 Bit Definitions */
54 #define ADF4350_REG3_12BIT_CLKDIV(x)		((x) << 3)
55 #define ADF4350_REG3_12BIT_CLKDIV_MODE(x)	((x) << 16)
56 #define ADF4350_REG3_12BIT_CSR_EN		(1 << 18)
57 #define ADF4351_REG3_CHARGE_CANCELLATION_EN	(1 << 21)
58 #define ADF4351_REG3_ANTI_BACKLASH_3ns_EN	(1 << 22)
59 #define ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH	(1 << 23)
60 
61 /* REG4 Bit Definitions */
62 #define ADF4350_REG4_OUTPUT_PWR(x)		((x) << 3)
63 #define ADF4350_REG4_RF_OUT_EN			(1 << 5)
64 #define ADF4350_REG4_AUX_OUTPUT_PWR(x)		((x) << 6)
65 #define ADF4350_REG4_AUX_OUTPUT_EN		(1 << 8)
66 #define ADF4350_REG4_AUX_OUTPUT_FUND		(1 << 9)
67 #define ADF4350_REG4_AUX_OUTPUT_DIV		(0 << 9)
68 #define ADF4350_REG4_MUTE_TILL_LOCK_EN		(1 << 10)
69 #define ADF4350_REG4_VCO_PWRDOWN_EN		(1 << 11)
70 #define ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(x)	((x) << 12)
71 #define ADF4350_REG4_RF_DIV_SEL(x)		((x) << 20)
72 #define ADF4350_REG4_FEEDBACK_DIVIDED		(0 << 23)
73 #define ADF4350_REG4_FEEDBACK_FUND		(1 << 23)
74 
75 /* REG5 Bit Definitions */
76 #define ADF4350_REG5_LD_PIN_MODE_LOW		(0 << 22)
77 #define ADF4350_REG5_LD_PIN_MODE_DIGITAL	(1 << 22)
78 #define ADF4350_REG5_LD_PIN_MODE_HIGH		(3 << 22)
79 
80 /* Specifications */
81 #define ADF4350_MAX_OUT_FREQ		4400000000ULL /* Hz */
82 #define ADF4350_MIN_OUT_FREQ		137500000 /* Hz */
83 #define ADF4351_MIN_OUT_FREQ		34375000 /* Hz */
84 #define ADF4350_MIN_VCO_FREQ		2200000000ULL /* Hz */
85 #define ADF4350_MAX_FREQ_45_PRESC	3000000000ULL /* Hz */
86 #define ADF4350_MAX_FREQ_PFD		32000000 /* Hz */
87 #define ADF4350_MAX_BANDSEL_CLK		125000 /* Hz */
88 #define ADF4350_MAX_FREQ_REFIN		250000000 /* Hz */
89 #define ADF4350_MAX_MODULUS		4095
90 #define ADF4350_MAX_R_CNT		1023
91 
92 
93 /**
94  * struct adf4350_platform_data - platform specific information
95  * @name:		Optional device name.
96  * @clkin:		REFin frequency in Hz.
97  * @channel_spacing:	Channel spacing in Hz (influences MODULUS).
98  * @power_up_frequency:	Optional, If set in Hz the PLL tunes to the desired
99  *			frequency on probe.
100  * @ref_div_factor:	Optional, if set the driver skips dynamic calculation
101  *			and uses this default value instead.
102  * @ref_doubler_en:	Enables reference doubler.
103  * @ref_div2_en:	Enables reference divider.
104  * @r2_user_settings:	User defined settings for ADF4350/1 REGISTER_2.
105  * @r3_user_settings:	User defined settings for ADF4350/1 REGISTER_3.
106  * @r4_user_settings:	User defined settings for ADF4350/1 REGISTER_4.
107  * @gpio_lock_detect:	Optional, if set with a valid GPIO number,
108  *			pll lock state is tested upon read.
109  *			If not used - set to -1.
110  */
111 
112 struct adf4350_platform_data {
113 	char			name[32];
114 	unsigned long		clkin;
115 	unsigned long		channel_spacing;
116 	unsigned long long	power_up_frequency;
117 
118 	unsigned short		ref_div_factor; /* 10-bit R counter */
119 	bool			ref_doubler_en;
120 	bool			ref_div2_en;
121 
122 	unsigned		r2_user_settings;
123 	unsigned		r3_user_settings;
124 	unsigned		r4_user_settings;
125 	int			gpio_lock_detect;
126 };
127 
128 #endif /* IIO_PLL_ADF4350_H_ */
129