xref: /wlan-driver/qca-wifi-host-cmn/hif/src/ar900Bdef.c (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2010, 2016-2018 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for
5  * any purpose with or without fee is hereby granted, provided that the
6  * above copyright notice and this permission notice appear in all
7  * copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10  * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11  * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12  * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16  * PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #include "qdf_module.h"
20 
21 #if defined(AR900B_HEADERS_DEF)
22 #define AR900B 1
23 
24 #define WLAN_HEADERS 1
25 #include "common_drv.h"
26 #include "AR900B/soc_addrs.h"
27 #include "AR900B/extra/hw/apb_map.h"
28 #include "AR900B/hw/gpio_athr_wlan_reg.h"
29 #ifdef WLAN_HEADERS
30 #include "AR900B/extra/hw/wifi_top_reg_map.h"
31 #include "AR900B/hw/rtc_soc_reg.h"
32 #endif
33 #include "AR900B/hw/si_reg.h"
34 #include "AR900B/extra/hw/pcie_local_reg.h"
35 #include "AR900B/hw/ce_wrapper_reg_csr.h"
36 /* TODO
37  * #include "hw/soc_core_reg.h"
38  * #include "hw/soc_pcie_reg.h"
39  * #include "hw/ce_reg_csr.h"
40  */
41 
42 #include "AR900B/extra/hw/soc_core_reg.h"
43 #include "AR900B/hw/soc_pcie_reg.h"
44 #include "AR900B/extra/hw/ce_reg_csr.h"
45 #include <AR900B/hw/interface/rx_location_info.h>
46 #include <AR900B/hw/interface/rx_pkt_end.h>
47 #include <AR900B/hw/interface/rx_phy_ppdu_end.h>
48 #include <AR900B/hw/interface/rx_timing_offset.h>
49 #include <AR900B/hw/interface/rx_location_info.h>
50 #include <AR900B/hw/tlv/rx_ppdu_start.h>
51 #include <AR900B/hw/tlv/rx_ppdu_end.h>
52 #include <AR900B/hw/tlv/rx_mpdu_start.h>
53 #include <AR900B/hw/tlv/rx_mpdu_end.h>
54 #include <AR900B/hw/tlv/rx_msdu_start.h>
55 #include <AR900B/hw/tlv/rx_msdu_end.h>
56 #include <AR900B/hw/tlv/rx_attention.h>
57 #include <AR900B/hw/tlv/rx_frag_info.h>
58 #include <AR900B/hw/datastruct/msdu_link_ext.h>
59 #include <AR900B/hw/emu_phy_reg.h>
60 
61 /* Base address is defined in pcie_local_reg.h. Macros which access the
62  * registers include the base address in their definition.
63  */
64 #define PCIE_LOCAL_BASE_ADDRESS 0
65 
66 #define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS)
67 #define DRAM_BASE_ADDRESS TARG_DRAM_START
68 
69 /* Backwards compatibility -- TBDXXX */
70 
71 #define MISSING 0
72 
73 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB WIFI_SYSTEM_SLEEP_DISABLE_LSB
74 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK WIFI_SYSTEM_SLEEP_DISABLE_MASK
75 #define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK
76 #define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK
77 #define SOC_CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_ADDRESS
78 #define SOC_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_ADDRESS
79 #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_ADDRESS
80 #define SOC_LPO_CAL_OFFSET SOC_LPO_CAL_ADDRESS
81 #define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK
82 #define WLAN_SYSTEM_SLEEP_OFFSET WIFI_SYSTEM_SLEEP_ADDRESS
83 #define WLAN_RESET_CONTROL_OFFSET WIFI_RESET_CONTROL_ADDRESS
84 #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
85 #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
86 #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
87 #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
88 #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
89 #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
90 #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
91 #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
92 #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
93 #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
94 #define LOCAL_SCRATCH_OFFSET 0x18
95 #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
96 #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
97 #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
98 #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
99 #define SI_CONFIG_OFFSET SI_CONFIG_ADDRESS
100 #define SI_TX_DATA0_OFFSET SI_TX_DATA0_ADDRESS
101 #define SI_TX_DATA1_OFFSET SI_TX_DATA1_ADDRESS
102 #define SI_RX_DATA0_OFFSET SI_RX_DATA0_ADDRESS
103 #define SI_RX_DATA1_OFFSET SI_RX_DATA1_ADDRESS
104 #define SI_CS_OFFSET SI_CS_ADDRESS
105 #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
106 #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
107 #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
108 #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
109 #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
110 #define MBOX_BASE_ADDRESS MISSING
111 #define INT_STATUS_ENABLE_ERROR_LSB MISSING
112 #define INT_STATUS_ENABLE_ERROR_MASK MISSING
113 #define INT_STATUS_ENABLE_CPU_LSB MISSING
114 #define INT_STATUS_ENABLE_CPU_MASK MISSING
115 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING
116 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING
117 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
118 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
119 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
120 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
121 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
122 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
123 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
124 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
125 #define INT_STATUS_ENABLE_ADDRESS MISSING
126 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
127 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
128 #define HOST_INT_STATUS_ADDRESS MISSING
129 #define CPU_INT_STATUS_ADDRESS MISSING
130 #define ERROR_INT_STATUS_ADDRESS MISSING
131 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING
132 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING
133 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
134 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
135 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
136 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
137 #define COUNT_DEC_ADDRESS MISSING
138 #define HOST_INT_STATUS_CPU_MASK MISSING
139 #define HOST_INT_STATUS_CPU_LSB MISSING
140 #define HOST_INT_STATUS_ERROR_MASK MISSING
141 #define HOST_INT_STATUS_ERROR_LSB MISSING
142 #define HOST_INT_STATUS_COUNTER_MASK MISSING
143 #define HOST_INT_STATUS_COUNTER_LSB MISSING
144 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING
145 #define WINDOW_DATA_ADDRESS MISSING
146 #define WINDOW_READ_ADDR_ADDRESS MISSING
147 #define WINDOW_WRITE_ADDR_ADDRESS MISSING
148 /* MAC Descriptor */
149 #define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2)
150 /* GPIO Register */
151 #define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS
152 #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB
153 #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB
154 #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK
155 /* CE descriptor */
156 #define CE_SRC_DESC_SIZE_DWORD 2
157 #define CE_DEST_DESC_SIZE_DWORD 2
158 #define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0
159 #define CE_SRC_DESC_INFO_OFFSET_DWORD 1
160 #define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0
161 #define CE_DEST_DESC_INFO_OFFSET_DWORD 1
162 #if _BYTE_ORDER == _BIG_ENDIAN
163 #define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000
164 #define CE_SRC_DESC_INFO_NBYTES_SHIFT 16
165 #define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000
166 #define CE_SRC_DESC_INFO_GATHER_SHIFT 15
167 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000
168 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14
169 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK     0x00002000
170 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT    13
171 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK   0x00001000
172 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT  12
173 #define CE_SRC_DESC_INFO_META_DATA_MASK            0x00000FFF
174 #define CE_SRC_DESC_INFO_META_DATA_SHIFT           0
175 #else
176 #define CE_SRC_DESC_INFO_NBYTES_MASK               0x0000FFFF
177 #define CE_SRC_DESC_INFO_NBYTES_SHIFT              0
178 #define CE_SRC_DESC_INFO_GATHER_MASK               0x00010000
179 #define CE_SRC_DESC_INFO_GATHER_SHIFT              16
180 #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK            0x00020000
181 #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT           17
182 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK     0x00040000
183 #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT    18
184 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK   0x00080000
185 #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT  19
186 #define CE_SRC_DESC_INFO_META_DATA_MASK            0xFFF00000
187 #define CE_SRC_DESC_INFO_META_DATA_SHIFT           20
188 #endif
189 #if _BYTE_ORDER == _BIG_ENDIAN
190 #define CE_DEST_DESC_INFO_NBYTES_MASK              0xFFFF0000
191 #define CE_DEST_DESC_INFO_NBYTES_SHIFT             16
192 #define CE_DEST_DESC_INFO_GATHER_MASK              0x00008000
193 #define CE_DEST_DESC_INFO_GATHER_SHIFT             15
194 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK           0x00004000
195 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT          14
196 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK    0x00002000
197 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT   13
198 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK  0x00001000
199 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12
200 #define CE_DEST_DESC_INFO_META_DATA_MASK           0x00000FFF
201 #define CE_DEST_DESC_INFO_META_DATA_SHIFT          0
202 #else
203 #define CE_DEST_DESC_INFO_NBYTES_MASK              0x0000FFFF
204 #define CE_DEST_DESC_INFO_NBYTES_SHIFT             0
205 #define CE_DEST_DESC_INFO_GATHER_MASK              0x00010000
206 #define CE_DEST_DESC_INFO_GATHER_SHIFT             16
207 #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK           0x00020000
208 #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT          17
209 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK    0x00040000
210 #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT   18
211 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK  0x00080000
212 #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19
213 #define CE_DEST_DESC_INFO_META_DATA_MASK           0xFFF00000
214 #define CE_DEST_DESC_INFO_META_DATA_SHIFT          20
215 #endif
216 
217 #define MY_TARGET_DEF AR900B_TARGETdef
218 #define MY_HOST_DEF AR900B_HOSTdef
219 #define MY_CEREG_DEF AR900B_CE_TARGETdef
220 #define MY_TARGET_BOARD_DATA_SZ AR900B_BOARD_DATA_SZ
221 #define MY_TARGET_BOARD_EXT_DATA_SZ AR900B_BOARD_EXT_DATA_SZ
222 #include "targetdef.h"
223 #include "hostdef.h"
224 qdf_export_symbol(AR900B_CE_TARGETdef);
225 #else
226 #include "common_drv.h"
227 #include "targetdef.h"
228 #include "hostdef.h"
229 struct targetdef_s *AR900B_TARGETdef;
230 struct hostdef_s *AR900B_HOSTdef;
231 #endif /*AR900B_HEADERS_DEF */
232 qdf_export_symbol(AR900B_TARGETdef);
233 qdf_export_symbol(AR900B_HOSTdef);
234