1 /* 2 * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: This file contains centralized definitions of converged configuration. 22 */ 23 24 #ifndef __CFG_MLME_HE_CAPS_H 25 #define __CFG_MLME_HE_CAPS_H 26 27 #define CFG_HE_CONTROL CFG_BOOL( \ 28 "he_control", \ 29 0, \ 30 "HE Control") 31 32 #define CFG_HE_FRAGMENTATION CFG_UINT( \ 33 "he_fragmentation", \ 34 0, \ 35 3, \ 36 0, \ 37 CFG_VALUE_OR_DEFAULT, \ 38 "HE Fragmentation") 39 40 #define CFG_HE_MAX_FRAG_MSDU CFG_UINT( \ 41 "he_max_frag_msdu", \ 42 0, \ 43 7, \ 44 0, \ 45 CFG_VALUE_OR_DEFAULT, \ 46 "HE Max Frag Msdu") 47 48 #define CFG_HE_MIN_FRAG_SIZE CFG_UINT( \ 49 "he_min_frag_size", \ 50 0, \ 51 3, \ 52 0, \ 53 CFG_VALUE_OR_DEFAULT, \ 54 "HE Min Frag Size") 55 56 #define CFG_HE_TRIG_PAD CFG_UINT( \ 57 "he_trig_pad", \ 58 0, \ 59 2, \ 60 2, \ 61 CFG_VALUE_OR_DEFAULT, \ 62 "HE Trig Pad") 63 64 #define CFG_HE_MTID_AGGR_RX CFG_UINT( \ 65 "he_mtid_aggr_rx", \ 66 0, \ 67 7, \ 68 0, \ 69 CFG_VALUE_OR_DEFAULT, \ 70 "HE Mtid Aggr") 71 72 #define CFG_HE_LINK_ADAPTATION CFG_UINT( \ 73 "he_link_adaptation", \ 74 0, \ 75 3, \ 76 0, \ 77 CFG_VALUE_OR_DEFAULT, \ 78 "HE Link Adaptation") 79 80 #define CFG_HE_ALL_ACK CFG_BOOL( \ 81 "he_all_ack", \ 82 0, \ 83 "HE All Ack") 84 85 #define CFG_HE_TRIGD_RSP_SCHEDULING CFG_BOOL( \ 86 "he_trigd_rsp_scheduling", \ 87 0, \ 88 "HE Trigd Rsp Scheduling") 89 90 #define CFG_HE_BUFFER_STATUS_RPT CFG_BOOL( \ 91 "he_buffer_status_rpt", \ 92 0, \ 93 "HE Buffer Status Rpt") 94 95 #define CFG_HE_BA_32BIT CFG_BOOL( \ 96 "he_ba_32bit", \ 97 0, \ 98 "HE BA 32Bit") 99 100 #define CFG_HE_MU_CASCADING CFG_BOOL( \ 101 "he_mu_cascading", \ 102 0, \ 103 "HE Mu Cascading") 104 105 #define CFG_HE_MULTI_TID CFG_BOOL( \ 106 "he_multi_tid", \ 107 0, \ 108 "HE Multi Tid") 109 110 #define CFG_HE_OMI CFG_BOOL( \ 111 "he_omi", \ 112 0, \ 113 "HE Omi") 114 115 #define CFG_HE_OFDMA_RA CFG_BOOL( \ 116 "he_ofdma_ra", \ 117 0, \ 118 "HE Ofdma Ra") 119 120 #define CFG_HE_MAX_AMPDU_LEN CFG_INI_UINT( \ 121 "he_max_ampdu_len", \ 122 0, \ 123 3, \ 124 3, \ 125 CFG_VALUE_OR_DEFAULT, \ 126 "HE Max Ampdu Len") 127 128 #define CFG_HE_AMSDU_FRAG CFG_BOOL( \ 129 "he_amspdu_frag", \ 130 0, \ 131 "HE Amsdu Frag") 132 133 #define CFG_HE_FLEX_TWT_SCHED CFG_BOOL( \ 134 "he_flex_twt_sched", \ 135 0, \ 136 "HE Flex Twt Sched") 137 138 #define CFG_HE_RX_CTRL CFG_BOOL( \ 139 "he_rx_ctrl", \ 140 0, \ 141 "HE Rx Ctrl") 142 143 #define CFG_HE_BSRP_AMPDU_AGGR CFG_BOOL( \ 144 "he_bsrp_ampdu_aggr", \ 145 0, \ 146 "He Bspr Ampdu Aggr") 147 148 #define CFG_HE_QTP CFG_BOOL( \ 149 "he_qtp", \ 150 0, \ 151 "He Qtp") 152 153 #define CFG_HE_A_BQR CFG_BOOL( \ 154 "he_a_bqr", \ 155 0, \ 156 "He A Bqr") 157 158 #define CFG_HE_SR_RESPONDER CFG_BOOL( \ 159 "he_sr_responder", \ 160 0, \ 161 "He Sr Responder") 162 163 #define CFG_HE_NDP_FEEDBACK_SUPP CFG_BOOL( \ 164 "he_ndp_feedback_supp", \ 165 0, \ 166 "He Ndp Feedback Supp") 167 168 #define CFG_HE_OPS_SUPP CFG_BOOL( \ 169 "he_ops_supp", \ 170 0, \ 171 "He Ops Supp") 172 173 #define CFG_HE_AMSDU_IN_AMPDU CFG_BOOL( \ 174 "he_amsdu_in_ampdu", \ 175 0, \ 176 "He Amsdu In Ampdu") 177 178 #define CFG_HE_MTID_AGGR_TX CFG_UINT( \ 179 "he_mtid_aggr_tx", \ 180 0, \ 181 0x7, \ 182 0, \ 183 CFG_VALUE_OR_DEFAULT, \ 184 "He MTid Aggr Tx") 185 186 #define CFG_HE_SUB_CH_SEL_TX CFG_BOOL( \ 187 "he_sub_ch_sel_tx", \ 188 0, \ 189 "He Sub cg sel tx") 190 191 #define CFG_HE_UL_2X996_RU CFG_BOOL( \ 192 "he_ul_2x996_ru", \ 193 0, \ 194 "He Ul 2x996 Ru") 195 196 #define CFG_HE_OM_CTRL_UL_MU_DIS_RX CFG_BOOL( \ 197 "he_om_ctrl_ul_mu_dis_rx", \ 198 0, \ 199 "He Om Ctrl Ul My Dis Rx") 200 201 #define CFG_HE_DYNAMIC_SMPS CFG_BOOL( \ 202 "he_dynamic_smps", \ 203 0, \ 204 "He Dynamic SMPS") 205 206 #define CFG_HE_PUNCTURED_SOUNDING CFG_BOOL( \ 207 "he_punctured_sounding", \ 208 0, \ 209 "He Punctured Sounding") 210 211 #define CFG_HE_HT_VHT_TRG_FRM_RX CFG_BOOL( \ 212 "ht_vht_trg_frm_rx", \ 213 0, \ 214 "HT VHT Trigger frame Rx") 215 216 #define CFG_HE_CHAN_WIDTH CFG_UINT( \ 217 "he_chan_width", \ 218 0, \ 219 0x3F, \ 220 0, \ 221 CFG_VALUE_OR_DEFAULT, \ 222 "He Chan Width") 223 224 #define CFG_HE_RX_PREAM_PUNC CFG_INI_UINT( \ 225 "he_rx_pream_punc", \ 226 0, \ 227 0xF, \ 228 0x3, \ 229 CFG_VALUE_OR_DEFAULT, \ 230 "He Rx Pream Punc") 231 232 #define CFG_HE_CLASS_OF_DEVICE CFG_BOOL( \ 233 "he_class_of_device", \ 234 0, \ 235 "He Class Of Device") 236 237 #define CFG_HE_LDPC CFG_BOOL( \ 238 "he_ldpc", \ 239 0, \ 240 "He Ldpc") 241 242 #define CFG_HE_LTF_PPDU CFG_UINT( \ 243 "he_ltf_ppdu", \ 244 0, \ 245 3, \ 246 0, \ 247 CFG_VALUE_OR_DEFAULT, \ 248 "He Ltf Ppdu") 249 250 #define CFG_HE_MIDAMBLE_RX_MAX_NSTS CFG_UINT( \ 251 "he_midamble_rx_max_nsts", \ 252 0, \ 253 3, \ 254 0, \ 255 CFG_VALUE_OR_DEFAULT, \ 256 "He Midamble Rx Max Nsts") 257 258 #define CFG_HE_LTF_NDP CFG_UINT( \ 259 "he_ltf_ndp", \ 260 0, \ 261 3, \ 262 0, \ 263 CFG_VALUE_OR_DEFAULT, \ 264 "He Ltf Ndp") 265 266 #define CFG_HE_TX_STBC_LT80 CFG_BOOL( \ 267 "he_tx_stbc_lt80_sta", \ 268 0, \ 269 "He Tx Stbc Lt80") 270 271 #define CFG_HE_RX_STBC_LT80 CFG_BOOL( \ 272 "he_rx_stbc_lt80", \ 273 0, \ 274 "He Rx Stbc Lt80") 275 276 #define CFG_HE_DOPPLER CFG_UINT( \ 277 "he_doppler", \ 278 0, \ 279 3, \ 280 0, \ 281 CFG_VALUE_OR_DEFAULT, \ 282 "He Doppler") 283 284 #define CFG_HE_DCM_TX CFG_UINT( \ 285 "he_dcm_tx", \ 286 0, \ 287 7, \ 288 0, \ 289 CFG_VALUE_OR_DEFAULT, \ 290 "He Dcm Tx") 291 292 #define CFG_HE_DCM_RX CFG_UINT( \ 293 "he_dcm_rx", \ 294 0, \ 295 7, \ 296 0, \ 297 CFG_VALUE_OR_DEFAULT, \ 298 "He Dcm Rx") 299 300 #define CFG_HE_MU_PPDU CFG_BOOL( \ 301 "he_mu_ppdu", \ 302 0, \ 303 "He Mu Ppdu") 304 305 #define CFG_HE_SU_BEAMFORMER CFG_BOOL( \ 306 "he_su_beamformer", \ 307 0, \ 308 "He Su Beamformer") 309 310 #define CFG_HE_SU_BEAMFORMEE CFG_BOOL( \ 311 "he_su_beamformee", \ 312 0, \ 313 "He Su Beamformee") 314 315 #define CFG_HE_MU_BEAMFORMER CFG_BOOL( \ 316 "he_mu_beamformer", \ 317 0, \ 318 "He Mu Beamformer") 319 320 #define CFG_HE_BFEE_STS_LT80 CFG_UINT( \ 321 "he_bfee_sts_lt80", \ 322 0, \ 323 7, \ 324 0, \ 325 CFG_VALUE_OR_DEFAULT, \ 326 "He Mu Bfee Sts Lt80") 327 328 #define CFG_HE_BFEE_STS_GT80 CFG_UINT( \ 329 "he_bfee_sts_lt80", \ 330 0, \ 331 7, \ 332 0, \ 333 CFG_VALUE_OR_DEFAULT, \ 334 "He Mu Bfee Sts Gt80") 335 336 #define CFG_HE_NUM_SOUND_LT80 CFG_UINT( \ 337 "he_num_sound_lt80", \ 338 0, \ 339 7, \ 340 0, \ 341 CFG_VALUE_OR_DEFAULT, \ 342 "He Num Sound Lt80") 343 344 #define CFG_HE_NUM_SOUND_GT80 CFG_UINT( \ 345 "he_num_sound_gt80", \ 346 0, \ 347 7, \ 348 0, \ 349 CFG_VALUE_OR_DEFAULT, \ 350 "He Num Sound Gt80") 351 352 #define CFG_HE_SU_FEED_TONE16 CFG_BOOL( \ 353 "he_su_feed_tone16", \ 354 0, \ 355 "He Su Feed Tone16") 356 357 #define CFG_HE_MU_FEED_TONE16 CFG_BOOL( \ 358 "he_mu_feed_tone16", \ 359 0, \ 360 "He Mu Feed Tone16") 361 362 #define CFG_HE_CODEBOOK_SU CFG_BOOL( \ 363 "he_codebook_su", \ 364 0, \ 365 "He Codebook Su") 366 367 #define CFG_HE_CODEBOOK_MU CFG_BOOL( \ 368 "he_codebook_mu", \ 369 0, \ 370 "He Codebook Mu") 371 372 #define CFG_HE_BFRM_FEED CFG_UINT( \ 373 "he_bfrm_feed", \ 374 0, \ 375 7, \ 376 0, \ 377 CFG_VALUE_OR_DEFAULT, \ 378 "He Bfrm Feed") 379 380 #define CFG_HE_ER_SU_PPDU CFG_BOOL( \ 381 "he_bfrm_feed", \ 382 0, \ 383 "He Er Su Ppdu") 384 385 #define CFG_HE_DL_PART_BW CFG_BOOL( \ 386 "he_dl_part_bw", \ 387 0, \ 388 "He Dl Part Bw") 389 390 #define CFG_HE_PPET_PRESENT CFG_BOOL( \ 391 "he_ppet_present", \ 392 0, \ 393 "He Pper Present") 394 395 #define CFG_HE_SRP CFG_BOOL( \ 396 "he_srp", \ 397 0, \ 398 "He Srp") 399 400 #define CFG_HE_POWER_BOOST CFG_BOOL( \ 401 "he_power_boost", \ 402 0, \ 403 "He Power Boost") 404 405 #define CFG_HE_4x_LTF_GI CFG_BOOL( \ 406 "he_4x_ltf_gi", \ 407 0, \ 408 "He 4x Ltf Gi") 409 410 #define CFG_HE_MAX_NC CFG_UINT( \ 411 "he_max_nc", \ 412 0, \ 413 7, \ 414 0, \ 415 CFG_VALUE_OR_DEFAULT, \ 416 "He Max Nc") 417 418 #define CFG_HE_RX_STBC_GT80 CFG_BOOL( \ 419 "he_rx_stbc_gt80", \ 420 0, \ 421 "He Rx Stbc Gt80") 422 423 #define CFG_HE_TX_STBC_GT80 CFG_BOOL( \ 424 "he_Tx_stbc_gt80", \ 425 0, \ 426 "He Tx Stbc Gt80") 427 428 #define CFG_HE_ER_4x_LTF_GI CFG_BOOL( \ 429 "he_er_4x_ltf_gi", \ 430 0, \ 431 "He Er 4x Ltf Gi") 432 433 #define CFG_HE_PPDU_20_IN_40MHZ_2G CFG_BOOL( \ 434 "he_ppdu_20_in_40mhz_2g", \ 435 0, \ 436 "He Ppdu 20 In 40Mhz 2g") 437 438 #define CFG_HE_PPDU_20_IN_160_80P80MHZ CFG_BOOL( \ 439 "he_ppdu_20_in_160_80p80mhz", \ 440 0, \ 441 "He Ppdu 20 In 160 80p80mhz") 442 443 #define CFG_HE_PPDU_80_IN_160_80P80MHZ CFG_BOOL( \ 444 "he_ppdu_80_in_160_80p80mhz", \ 445 0, \ 446 "He Ppdu 80 In 160 80p80mhz") 447 448 #define CFG_HE_ER_1X_HE_LTF_GI CFG_BOOL( \ 449 "he_er_1x_he_ltf_gi", \ 450 0, \ 451 "He Er 1x He Ltf Gi") 452 453 #define CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF CFG_BOOL( \ 454 "he_midamble_txrx_1x_he_ltf", \ 455 0, \ 456 "He Midamble Tx Rx 1x He Ltf") 457 458 #define CFG_HE_DCM_MAX_BW CFG_UINT( \ 459 "he_dcm_max_bw", \ 460 0, \ 461 3, \ 462 0, \ 463 CFG_VALUE_OR_DEFAULT, \ 464 "He Dcm Max Bw") 465 466 #define CFG_HE_LONGER_16_SIGB_OFDM_SYM CFG_BOOL( \ 467 "he_longer_16_sigb_ofdm_sys", \ 468 0, \ 469 "He Longer 16 Sigb Ofdm Sys") 470 471 #define CFG_HE_NON_TRIG_CQI_FEEDBACK CFG_BOOL( \ 472 "he_rx_mcs_map_lt_80", \ 473 0, \ 474 "He Non Trig Cqi Feedback") 475 476 #define CFG_HE_TX_1024_QAM_LT_242_RU CFG_BOOL( \ 477 "he_tx_1024_qam_lt_242_ru", \ 478 0, \ 479 "He Tx 1024 Qam Lt 242 Ru") 480 481 #define CFG_HE_RX_1024_QAM_LT_242_RU CFG_BOOL( \ 482 "he_rx_1024_qam_lt_242_ru", \ 483 0, \ 484 "He Rx 1024 Qam Lt 242 Ru") 485 486 #define CFG_HE_RX_FULL_BW_MU_CMPR_SIGB CFG_BOOL( \ 487 "he_rx_full_bw_cmpr_sigb", \ 488 0, \ 489 "He Rx Full Bw Mu Cmpr Sigb") 490 491 #define CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB CFG_BOOL( \ 492 "he_rx_full_bw_mu_non_cmpr_sigb", \ 493 0, \ 494 "He Rx Full Bw Mu Non Cmpr Sigb") 495 496 /* 11AX related INI configuration */ 497 /* 498 * <ini> 499 * he_rx_mcs_map_lt_80 - configure Rx HE-MCS Map for ≤ 80 MHz 500 * @Min: 0 501 * @Max: 0xFFFF 502 * @Default: 0xFFFA 503 * 504 * This ini is used to configure Rx HE-MCS Map for ≤ 80 MHz 505 * 0:1 Max HE-MCS For 1 SS 506 * 2:3 Max HE-MCS For 2 SS 507 * 4:5 Max HE-MCS For 3 SS 508 * 6:7 Max HE-MCS For 4 SS 509 * 8:9 Max HE-MCS For 5 SS 510 * 10:11 Max HE-MCS For 6 SS 511 * 12:13 Max HE-MCS For 7 SS 512 * 14:15 Max HE-MCS For 8 SS 513 * 514 * 0 indicates support for HE-MCS 0-7 for n spatial streams 515 * 1 indicates support for HE-MCS 0-9 for n spatial streams 516 * 2 indicates support for HE-MCS 0-11 for n spatial streams 517 * 3 indicates that n spatial streams is not supported for HE PPDUs 518 * 519 * Related: NA 520 * 521 * Supported Feature: 11AX 522 * 523 * Usage: External 524 * 525 * </ini> 526 */ 527 #define CFG_HE_RX_MCS_MAP_LT_80 CFG_INI_UINT( \ 528 "he_rx_mcs_map_lt_80", \ 529 0, \ 530 0xFFFF, \ 531 0xFFFA, \ 532 CFG_VALUE_OR_DEFAULT, \ 533 "He Rx Mcs Map Lt 80") 534 535 /* 11AX related INI configuration */ 536 /* 537 * <ini> 538 * he_tx_mcs_map_lt_80 - configure Tx HE-MCS Map for ≤ 80 MHz 539 * @Min: 0 540 * @Max: 0xFFFF 541 * @Default: 0xFFFA 542 * 543 * This ini is used to configure Tx HE-MCS Map for ≤ 80 MHz 544 * 0:1 Max HE-MCS For 1 SS 545 * 2:3 Max HE-MCS For 2 SS 546 * 4:5 Max HE-MCS For 3 SS 547 * 6:7 Max HE-MCS For 4 SS 548 * 8:9 Max HE-MCS For 5 SS 549 * 10:11 Max HE-MCS For 6 SS 550 * 12:13 Max HE-MCS For 7 SS 551 * 14:15 Max HE-MCS For 8 SS 552 * 553 * 0 indicates support for HE-MCS 0-7 for n spatial streams 554 * 1 indicates support for HE-MCS 0-9 for n spatial streams 555 * 2 indicates support for HE-MCS 0-11 for n spatial streams 556 * 3 indicates that n spatial streams is not supported for HE PPDUs 557 * 558 * Related: NA 559 * 560 * Supported Feature: 11AX 561 * 562 * Usage: External 563 * 564 * </ini> 565 */ 566 #define CFG_HE_TX_MCS_MAP_LT_80 CFG_INI_UINT( \ 567 "he_tx_mcs_map_lt_80", \ 568 0, \ 569 0xFFFF, \ 570 0xFFFA, \ 571 CFG_VALUE_OR_DEFAULT, \ 572 "He Tx Mcs Map Lt 80") 573 /* 11AX related INI configuration */ 574 /* 575 * <ini> 576 * he_rx_mcs_map_160 - configure Rx HE-MCS Map for 160 MHz 577 * @Min: 0 578 * @Max: 0xFFFF 579 * @Default: 0xFFFA 580 * 581 * This ini is used to configure Rx HE-MCS Map for 160 MHz 582 * 0:1 Max HE-MCS For 1 SS 583 * 2:3 Max HE-MCS For 2 SS 584 * 4:5 Max HE-MCS For 3 SS 585 * 6:7 Max HE-MCS For 4 SS 586 * 8:9 Max HE-MCS For 5 SS 587 * 10:11 Max HE-MCS For 6 SS 588 * 12:13 Max HE-MCS For 7 SS 589 * 14:15 Max HE-MCS For 8 SS 590 * 591 * 0 indicates support for HE-MCS 0-7 for n spatial streams 592 * 1 indicates support for HE-MCS 0-9 for n spatial streams 593 * 2 indicates support for HE-MCS 0-11 for n spatial streams 594 * 3 indicates that n spatial streams is not supported for HE PPDUs 595 * 596 * Related: NA 597 * 598 * Supported Feature: 11AX 599 * 600 * Usage: External 601 * 602 * </ini> 603 */ 604 #define CFG_HE_RX_MCS_MAP_160 CFG_INI_UINT( \ 605 "he_rx_mcs_map_160", \ 606 0, \ 607 0xFFFF, \ 608 0xFFFA, \ 609 CFG_VALUE_OR_DEFAULT, \ 610 "He Rx Mcs Map 160") 611 612 /* 11AX related INI configuration */ 613 /* 614 * <ini> 615 * he_tx_mcs_map_160 - configure Tx HE-MCS Map for 160 MHz 616 * @Min: 0 617 * @Max: 0xFFFF 618 * @Default: 0xFFFA 619 * 620 * This ini is used to configure Tx HE-MCS Map for 160 MHz 621 * 0:1 Max HE-MCS For 1 SS 622 * 2:3 Max HE-MCS For 2 SS 623 * 4:5 Max HE-MCS For 3 SS 624 * 6:7 Max HE-MCS For 4 SS 625 * 8:9 Max HE-MCS For 5 SS 626 * 10:11 Max HE-MCS For 6 SS 627 * 12:13 Max HE-MCS For 7 SS 628 * 14:15 Max HE-MCS For 8 SS 629 * 630 * 0 indicates support for HE-MCS 0-7 for n spatial streams 631 * 1 indicates support for HE-MCS 0-9 for n spatial streams 632 * 2 indicates support for HE-MCS 0-11 for n spatial streams 633 * 3 indicates that n spatial streams is not supported for HE PPDUs 634 * 635 * Related: NA 636 * 637 * Supported Feature: 11AX 638 * 639 * Usage: External 640 * 641 * </ini> 642 */ 643 #define CFG_HE_TX_MCS_MAP_160 CFG_INI_UINT( \ 644 "he_tx_mcs_map_160", \ 645 0, \ 646 0xFFFF, \ 647 0xFFFA, \ 648 CFG_VALUE_OR_DEFAULT, \ 649 "He Tx Mcs Map 160") 650 651 #define CFG_HE_RX_MCS_MAP_80_80 CFG_UINT( \ 652 "he_rx_mcs_map_80_80", \ 653 0, \ 654 0xFFFF, \ 655 0xFFF0, \ 656 CFG_VALUE_OR_DEFAULT, \ 657 "He Rx Mcs Map 80 80") 658 659 #define CFG_HE_TX_MCS_MAP_80_80 CFG_UINT( \ 660 "he_tx_mcs_map_80_80", \ 661 0, \ 662 0xFFFF, \ 663 0xFFF0, \ 664 CFG_VALUE_OR_DEFAULT, \ 665 "He tx Mcs Map 80 80") 666 667 #define CFG_HE_OPS_BASIC_MCS_NSS CFG_UINT( \ 668 "cfg_he_ops_basic_mcs_nss", \ 669 0x0000, \ 670 0xFFFF, \ 671 0xFFFC, \ 672 CFG_VALUE_OR_DEFAULT, \ 673 "He Ops Basic Mcs NSS") 674 675 /* 11AX related INI configuration */ 676 /* 677 * <ini> 678 * he_ul_mumimo - configure ul mu capabilities 679 * @Min: 0 680 * @Max: 3 681 * @Default: 0 682 * 683 * This ini is used to configure capabilities of ul mu-mimo 684 * 0-> no support 685 * 1-> full bandwidth support 686 * 2-> partial bandwidth support 687 * 3-> full and partial bandwidth support 688 * 689 * Related: NA 690 * 691 * Supported Feature: 11AX 692 * 693 * Usage: Internal/External 694 * 695 * </ini> 696 */ 697 #define CFG_HE_UL_MUMIMO CFG_INI_UINT( \ 698 "he_ul_mumimo", \ 699 0, \ 700 3, \ 701 0, \ 702 CFG_VALUE_OR_DEFAULT, \ 703 "He Ul Mumimo") 704 705 /* 11AX related INI configuration */ 706 /* 707 * <ini> 708 * he_dynamic_frag_support - configure dynamic fragmentation 709 * @Min: 0 710 * @Max: 3 711 * @Default: 0 712 * 713 * This ini is used to configure dynamic fragmentation. 714 * 715 * Related: NA 716 * 717 * Supported Feature: 11AX 718 * 719 * Usage: Internal/External 720 * 721 * </ini> 722 */ 723 #define CFG_HE_DYNAMIC_FRAGMENTATION CFG_INI_UINT( \ 724 "he_dynamic_frag_support", \ 725 0, \ 726 3, \ 727 0, \ 728 CFG_VALUE_OR_DEFAULT, \ 729 "HE Dynamic Fragmentation") 730 731 732 /* 733 * <ini> 734 * enable_ul_mimo- Enable UL MIMO. 735 * @Min: 0 736 * @Max: 1 737 * @Default: 1 738 * 739 * This ini is used to enable or disable UL MIMO. 740 * 741 * Related: NA 742 * 743 * Supported Feature: 11AX 744 * 745 * Usage: External 746 * 747 * </ini> 748 */ 749 #define CFG_ENABLE_UL_MIMO CFG_INI_BOOL( \ 750 "enable_ul_mimo", \ 751 1, \ 752 "He Enable Ul Mimo Name") 753 754 /* 755 * <ini> 756 * enable_ul_ofdma- Enable UL OFDMA. 757 * @Min: 0 758 * @Max: 1 759 * @Default: 1 760 * 761 * This ini is used to enable or disable UL OFDMA. 762 * 763 * Related: NA 764 * 765 * Supported Feature: 11AX 766 * 767 * Usage: External 768 * 769 * </ini> 770 */ 771 772 #define CFG_ENABLE_UL_OFDMA CFG_INI_BOOL( \ 773 "enable_ul_ofdma", \ 774 1, \ 775 "He Enable Ul Ofdma Name") 776 777 /* 778 * <ini> 779 * he_sta_obsspd- 11AX HE OBSS PD bit field 780 * @Min: 0 781 * @Max: uin32_t max 782 * @Default: 0x15b8c2ae 783 * 784 * 4 Byte value with each byte representing a signed value for following params: 785 * Param Bit position Default 786 * OBSS_PD min (primary) 7:0 -82 (0xae) 787 * OBSS_PD max (primary) 15:8 -62 (0xc2) 788 * Secondary channel Ed 23:16 -72 (0xb8) 789 * TX_PWR(ref) 31:24 21 (0x15) 790 * This bit field value is directly applied to FW 791 * 792 * Related: NA 793 * 794 * Supported Feature: 11AX 795 * 796 * Usage: External 797 * 798 * </ini> 799 */ 800 #define CFG_HE_STA_OBSSPD CFG_INI_UINT( \ 801 "he_sta_obsspd", \ 802 0, \ 803 0xFFFFFFFF, \ 804 0x15b8c2ae, \ 805 CFG_VALUE_OR_DEFAULT, \ 806 "He Mu Bfee Sts Gt80") 807 808 /* 809 * <ini> 810 * he_mcs_12_13_support - Bit mask to enable MCS 12 and 13 support 811 * @Min: 0x0 812 * @Max: 0xffffffff 813 * @Default: 0xffffffff 814 * 815 * This ini is used to set MCS 12 and 13 for 2.4Ghz and 5Ghz. first 16 816 * bits(0-15) is for 2.4ghz and next 16 bits is for 5Ghz. Of 16 bits the lower 817 * 8 bits represent BW less than or equal 80Mhz (<= 80Mhz) and higher 8 bits 818 * represent BW greater than 80Mhz (> 80Mhz). nth bit in octet represent support 819 * for nth NSS [n=1:8]. Def value is 0xFFFFFFFF which enable MCS 12 and 13 for 820 * all NSS and BW. 821 * 822 * Bits Band 823 * BIT[0:15] 2.4Ghz support for MCS 12 and 13, for NSS n[1:8] and BW <= 80Mhz 824 * first 8 bits should be used (0-7) and for NSS n[1:8] and BW > 825 * 80 Mhz, next 8 bits (8-15) should be used. 826 * 827 * BIT[16:31] 5Ghz support for MCS 12 and 13, for NSS n[1:8] and BW < 80Mhz, 828 * bits 16-23 should be used and for BW > 80Mhz, next 8 bits 829 * (24-31) 830 * 831 * Some Possible values are as below 832 * 0 - MCS 12 and 13 disabled for 2.4Ghz and 5Ghz for all nss and 833 * BW > 80Mz and <= 80Mhz 834 * 0x3030303 - MCS 12 and 13 enabled for 2.4Ghz and 5Ghz for NSS 1 and 2 for 835 * BW > 80Mhz and <= 80Mhz 836 * 0x0303 - MCS 12 and 13 enabled for 2.4Ghz NSS 1 and 2 for BW > 80Mhz and 837 * <= 80Mhz but disabled for 5Ghz 838 * 0x3030000 - MCS 12 and 13 enabled for 5Ghz NSS 1 and 2 for BW > 80Mhz and 839 * <= 80Mhz but disabled for 2.4Ghz 840 * 0x30000 - MCS 12 and 13 enabled for 5Ghz NSS 1 and 2 for BW <= 80Mhz and 841 * disabled for BW > 80Mhz. And disabled for 2.4Ghz 842 * 0x3 MCS 12 and 13 enabled for 2.4Ghz NSS 1 and 2 for BW <= 80Mhz and 843 * disabled for all 844 * 845 * Related: None 846 * 847 * Supported Feature: HE MCS 12 and 13 848 * 849 * Usage: Internal 850 * 851 * </ini> 852 */ 853 #define CFG_HE_MCS_12_13_SUPPORT CFG_INI_UINT("he_mcs_12_13_support", \ 854 0, 0xffffffff, 0xffffffff, \ 855 CFG_VALUE_OR_DEFAULT, \ 856 "He Configure MCS_12_13 bits") 857 858 /* 859 * <ini> 860 * disable_mcs_12_13_sap - Bitmask to disable HE MCS 12 13 support for SAP 861 * @Min: 0 862 * @Max: 4095 863 * @Default: 0 864 * 865 * This ini is used to disable HE MCS_12_13 for SAP. 866 * Currently only support is present to disable 2.4 GHz 40 MHz SAP for value 867 * 2 i.e. 2nd bit set. 868 * 869 * Related: NA 870 * 871 * Usage: External 872 * 873 * </ini> 874 */ 875 #define CFG_DISABLE_MCS_12_13_SAP CFG_INI_UINT( \ 876 "disable_mcs_12_13_sap", \ 877 0, 4095, 0, \ 878 CFG_VALUE_OR_DEFAULT, \ 879 "Disable HE MCS_12_13 for SAP") 880 881 #define CFG_HE_CAPS_ALL \ 882 CFG(CFG_HE_CONTROL) \ 883 CFG(CFG_HE_FRAGMENTATION) \ 884 CFG(CFG_HE_MAX_FRAG_MSDU) \ 885 CFG(CFG_HE_MIN_FRAG_SIZE) \ 886 CFG(CFG_HE_TRIG_PAD) \ 887 CFG(CFG_HE_MTID_AGGR_RX) \ 888 CFG(CFG_HE_LINK_ADAPTATION) \ 889 CFG(CFG_HE_ALL_ACK) \ 890 CFG(CFG_HE_TRIGD_RSP_SCHEDULING) \ 891 CFG(CFG_HE_BUFFER_STATUS_RPT) \ 892 CFG(CFG_HE_BA_32BIT) \ 893 CFG(CFG_HE_MU_CASCADING) \ 894 CFG(CFG_HE_MULTI_TID) \ 895 CFG(CFG_HE_OMI) \ 896 CFG(CFG_HE_OFDMA_RA) \ 897 CFG(CFG_HE_MAX_AMPDU_LEN) \ 898 CFG(CFG_HE_AMSDU_FRAG) \ 899 CFG(CFG_HE_FLEX_TWT_SCHED) \ 900 CFG(CFG_HE_RX_CTRL) \ 901 CFG(CFG_HE_BSRP_AMPDU_AGGR) \ 902 CFG(CFG_HE_QTP) \ 903 CFG(CFG_HE_A_BQR) \ 904 CFG(CFG_HE_SR_RESPONDER) \ 905 CFG(CFG_HE_NDP_FEEDBACK_SUPP) \ 906 CFG(CFG_HE_OPS_SUPP) \ 907 CFG(CFG_HE_AMSDU_IN_AMPDU) \ 908 CFG(CFG_HE_CHAN_WIDTH) \ 909 CFG(CFG_HE_MTID_AGGR_TX) \ 910 CFG(CFG_HE_SUB_CH_SEL_TX) \ 911 CFG(CFG_HE_UL_2X996_RU) \ 912 CFG(CFG_HE_OM_CTRL_UL_MU_DIS_RX) \ 913 CFG(CFG_HE_RX_PREAM_PUNC) \ 914 CFG(CFG_HE_CLASS_OF_DEVICE) \ 915 CFG(CFG_HE_LDPC) \ 916 CFG(CFG_HE_LTF_PPDU) \ 917 CFG(CFG_HE_MIDAMBLE_RX_MAX_NSTS) \ 918 CFG(CFG_HE_LTF_NDP) \ 919 CFG(CFG_HE_TX_STBC_LT80) \ 920 CFG(CFG_HE_RX_STBC_LT80) \ 921 CFG(CFG_HE_DOPPLER) \ 922 CFG(CFG_HE_UL_MUMIMO) \ 923 CFG(CFG_HE_DCM_TX) \ 924 CFG(CFG_HE_DCM_RX) \ 925 CFG(CFG_HE_MU_PPDU) \ 926 CFG(CFG_HE_SU_BEAMFORMER) \ 927 CFG(CFG_HE_SU_BEAMFORMEE) \ 928 CFG(CFG_HE_MU_BEAMFORMER) \ 929 CFG(CFG_HE_BFEE_STS_LT80) \ 930 CFG(CFG_HE_BFEE_STS_GT80) \ 931 CFG(CFG_HE_NUM_SOUND_LT80) \ 932 CFG(CFG_HE_NUM_SOUND_GT80) \ 933 CFG(CFG_HE_SU_FEED_TONE16) \ 934 CFG(CFG_HE_MU_FEED_TONE16) \ 935 CFG(CFG_HE_CODEBOOK_SU) \ 936 CFG(CFG_HE_CODEBOOK_MU) \ 937 CFG(CFG_HE_BFRM_FEED) \ 938 CFG(CFG_HE_ER_SU_PPDU) \ 939 CFG(CFG_HE_DL_PART_BW) \ 940 CFG(CFG_HE_PPET_PRESENT) \ 941 CFG(CFG_HE_SRP) \ 942 CFG(CFG_HE_POWER_BOOST) \ 943 CFG(CFG_HE_4x_LTF_GI) \ 944 CFG(CFG_HE_MAX_NC) \ 945 CFG(CFG_HE_RX_STBC_GT80) \ 946 CFG(CFG_HE_TX_STBC_GT80) \ 947 CFG(CFG_HE_ER_4x_LTF_GI) \ 948 CFG(CFG_HE_PPDU_20_IN_40MHZ_2G) \ 949 CFG(CFG_HE_PPDU_20_IN_160_80P80MHZ) \ 950 CFG(CFG_HE_PPDU_80_IN_160_80P80MHZ) \ 951 CFG(CFG_HE_ER_1X_HE_LTF_GI) \ 952 CFG(CFG_HE_MIDAMBLE_TXRX_1X_HE_LTF) \ 953 CFG(CFG_HE_DCM_MAX_BW) \ 954 CFG(CFG_HE_LONGER_16_SIGB_OFDM_SYM) \ 955 CFG(CFG_HE_NON_TRIG_CQI_FEEDBACK) \ 956 CFG(CFG_HE_TX_1024_QAM_LT_242_RU) \ 957 CFG(CFG_HE_RX_1024_QAM_LT_242_RU) \ 958 CFG(CFG_HE_RX_FULL_BW_MU_CMPR_SIGB) \ 959 CFG(CFG_HE_RX_FULL_BW_MU_NON_CMPR_SIGB) \ 960 CFG(CFG_HE_RX_MCS_MAP_LT_80) \ 961 CFG(CFG_HE_TX_MCS_MAP_LT_80) \ 962 CFG(CFG_HE_RX_MCS_MAP_160) \ 963 CFG(CFG_HE_TX_MCS_MAP_160) \ 964 CFG(CFG_HE_RX_MCS_MAP_80_80) \ 965 CFG(CFG_HE_TX_MCS_MAP_80_80) \ 966 CFG(CFG_HE_OPS_BASIC_MCS_NSS) \ 967 CFG(CFG_HE_DYNAMIC_FRAGMENTATION) \ 968 CFG(CFG_ENABLE_UL_MIMO) \ 969 CFG(CFG_ENABLE_UL_OFDMA) \ 970 CFG(CFG_HE_STA_OBSSPD) \ 971 CFG(CFG_HE_MCS_12_13_SUPPORT) \ 972 CFG(CFG_DISABLE_MCS_12_13_SAP) 973 974 #endif /* __CFG_MLME_HE_CAPS_H */ 975 976