1 /* 2 * Copyright (c) 2012-2019, 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: This file contains centralized definitions of converged configuration. 22 */ 23 24 #ifndef __CFG_CHAINMASK_H 25 #define __CFG_CHAINMASK_H 26 27 /* 28 * <ini> 29 * gSetTxChainmask1x1 - Sets Transmit chain mask. 30 * @Min: 0 31 * @Max: 3 32 * @Default: 1 33 * 34 * This ini Sets Transmit chain mask. 35 * 36 * If gEnable2x2 is disabled, gSetTxChainmask1x1 and gSetRxChainmask1x1 values 37 * are taken into account. If chainmask value exceeds the maximum number of 38 * chains supported by target, the max number of chains is used. By default, 39 * chain0 is selected for both Tx and Rx. 40 * gSetTxChainmask1x1=1 or gSetRxChainmask1x1=1 to select chain0. 41 * gSetTxChainmask1x1=2 or gSetRxChainmask1x1=2 to select chain1. 42 * gSetTxChainmask1x1=3 or gSetRxChainmask1x1=3 to select both chains. 43 * 44 * Supported Feature: 11AC 45 * 46 * Usage: External 47 * 48 * </ini> 49 */ 50 #define CFG_VHT_ENABLE_1x1_TX_CHAINMASK CFG_INI_UINT( \ 51 "gSetTxChainmask1x1", \ 52 0, \ 53 3, \ 54 1, \ 55 CFG_VALUE_OR_DEFAULT, \ 56 "1x1 VHT Tx Chainmask") 57 58 /* 59 * <ini> 60 * gSetRxChainmask1x1 - Sets Receive chain mask. 61 * @Min: 0 62 * @Max: 3 63 * @Default: 1 64 * 65 * This ini is used to set Receive chain mask. 66 * 67 * If gEnable2x2 is disabled, gSetTxChainmask1x1 and gSetRxChainmask1x1 values 68 * are taken into account. If chainmask value exceeds the maximum number of 69 * chains supported by target, the max number of chains is used. By default, 70 * chain0 is selected for both Tx and Rx. 71 * gSetTxChainmask1x1=1 or gSetRxChainmask1x1=1 to select chain0. 72 * gSetTxChainmask1x1=2 or gSetRxChainmask1x1=2 to select chain1. 73 * gSetTxChainmask1x1=3 or gSetRxChainmask1x1=3 to select both chains. 74 * 75 * Supported Feature: 11AC 76 * 77 * Usage: External 78 * 79 * </ini> 80 */ 81 #define CFG_VHT_ENABLE_1x1_RX_CHAINMASK CFG_INI_UINT( \ 82 "gSetRxChainmask1x1", \ 83 0, \ 84 3, \ 85 1, \ 86 CFG_VALUE_OR_DEFAULT, \ 87 "1x1 VHT Rx Chainmask") 88 89 /* 90 * <ini> 91 * gCckChainMaskEnable - Used to enable/disable Cck ChainMask 92 * @Min: 0 93 * @Max: 1 94 * @Default: 0 95 * 96 * This ini is used to set default Cck ChainMask 97 * 0: disable the cck tx chain mask (default) 98 * 1: enable the cck tx chain mask 99 * 100 * Related: None 101 * 102 * Supported Feature: STA 103 * 104 * Usage: Internal/External 105 * 106 * </ini> 107 */ 108 #define CFG_TX_CHAIN_MASK_CCK CFG_INI_BOOL( \ 109 "gCckChainMaskEnable", \ 110 0, \ 111 "Set default CCK Tx Chainmask") 112 113 /* 114 * <ini> 115 * gTxChainMask1ss - Enables/disables tx chain mask1ss, used by Rome 116 * @Min: 0 117 * @Max: 3 118 * @Default: 0 119 * 120 * This ini is used to set default tx chain mask for 1ss 121 * 122 * gTxChainMask1ss=0 : 1ss data tx chain mask set to 3 and self gen chain mask 123 * set to 3. This is default setting of fw side. For 1x1 case, WIFI will 124 * using chain0 to sent 1ss data and selfgen packets. 2x2 case, WIFI will 125 * using chain0 and chain1 to sent 1ss data and selfgen packets. 126 * 127 * gTxChainMask1ss=1 : 1ss data tx chain mask set to 2 and self gen chain mask 128 * set to 2. This setting can work only when 2x2 case, WIFI will use chain1 129 * to sent 1ss data packets and selfgen packets, this can improve BTC 130 * performance a little, but have side affect when chain0 and chain1 RSSI 131 * is unbalance or green AP is enabled. So we recommend not using it. 132 * 133 * gTxChainMask1ss=2 : 1ss data tx chain mask set to 3 and self gen chain mask 134 * set to 2. This setting never used before. 135 * 136 * gTxChainMask1ss=3 : 1ss data tx chain mask set to 2 and self gen chain mask 137 * set to 3. This setting never used before. 138 * 139 * Related: None 140 * 141 * Supported Feature: STA/SAP 142 * 143 * Usage: Internal/External 144 * 145 * </ini> 146 */ 147 #define CFG_TX_CHAIN_MASK_1SS CFG_INI_UINT( \ 148 "gTxChainMask1ss", \ 149 0, \ 150 3, \ 151 0, \ 152 CFG_VALUE_OR_DEFAULT, \ 153 "1SS Tx Chainmask") 154 155 /* 156 * <ini> 157 * g11bNumTxChains - Number of Tx Chanins in 11b mode 158 * @Min: 0 159 * @Max: 2 160 * @Default: 0 161 * 162 * Number of Tx Chanins in 11b mode 163 * 164 * 165 * Related: None 166 * 167 * Supported Feature: connection 168 * 169 * Usage: External 170 * 171 * </ini> 172 */ 173 #define CFG_11B_NUM_TX_CHAIN CFG_INI_UINT( \ 174 "g11bNumTxChains", \ 175 0, \ 176 2, \ 177 0, \ 178 CFG_VALUE_OR_DEFAULT, \ 179 "11b Num Tx chains") 180 181 /* 182 * <ini> 183 * g11agNumTxChains - Number of Tx Chanins in 11ag mode 184 * @Min: 0 185 * @Max: 2 186 * @Default: 0 187 * 188 * Number of Tx Chanins in 11ag mode 189 * 190 * 191 * Related: None 192 * 193 * Supported Feature: connection 194 * 195 * Usage: External 196 * 197 * </ini> 198 */ 199 #define CFG_11AG_NUM_TX_CHAIN CFG_INI_UINT( \ 200 "g11agNumTxChains", \ 201 0, \ 202 2, \ 203 0, \ 204 CFG_VALUE_OR_DEFAULT, \ 205 "11ag Num Tx chains") 206 207 /* 208 * <ini> 209 * tx_chain_mask_2g - tx chain mask for 2g 210 * @Min: 0 211 * @Max: 4 212 * @Default: 0 213 * 214 * This ini will set tx chain mask for 2g. To use the ini, make sure: 215 * gSetTxChainmask1x1/gSetRxChainmask1x1 = 0, 216 * gDualMacFeatureDisable = 1 217 * gEnable2x2 = 0 218 * 219 * tx_chain_mask_2g=0 : don't care 220 * tx_chain_mask_2g=1 : for 2g tx use chain 0 221 * tx_chain_mask_2g=2 : for 2g tx use chain 1 222 * tx_chain_mask_2g=3 : for 2g tx can use either chain 223 * 224 * QCN7605 DBS chip has 3 RF chains. 225 * Chain0 for 2G, Chain1 for 2G/5G, Chain2 for 5G. 226 * DBS mode need 3 bits to map chainmask and halphy. 227 * In HW design, PHYA0 always Connects to shared RF chain1. 228 * tx_chain_mask_2g=4 : for 2g tx chain use PHYB and chain 0 229 * 230 * Related: None 231 * 232 * Supported Feature: All profiles 233 * 234 * Usage: External 235 * 236 * </ini> 237 */ 238 #define CFG_TX_CHAIN_MASK_2G CFG_INI_UINT( \ 239 "tx_chain_mask_2g", \ 240 0, \ 241 4, \ 242 0, \ 243 CFG_VALUE_OR_DEFAULT, \ 244 "2.4G Tx Chainmask") 245 246 /* 247 * <ini> 248 * rx_chain_mask_2g - rx chain mask for 2g 249 * @Min: 0 250 * @Max: 4 251 * @Default: 0 252 * 253 * This ini will set rx chain mask for 2g. To use the ini, make sure: 254 * gSetTxChainmask1x1/gSetRxChainmask1x1 = 0, 255 * gDualMacFeatureDisable = 1 256 * gEnable2x2 = 0 257 * 258 * rx_chain_mask_2g=0 : don't care 259 * rx_chain_mask_2g=1 : for 2g rx use chain 0 260 * rx_chain_mask_2g=2 : for 2g rx use chain 1 261 * rx_chain_mask_2g=3 : for 2g rx can use either chain 262 * 263 * QCN7605 DBS chip has 3 RF chains. 264 * Chain0 for 2G, Chain1 for 2G/5G, Chain2 for 5G. 265 * DBS mode need 3 bits to map chainmask and halphy. 266 * In HW design, PHYA0 always Connects to shared RF chain1. 267 * rx_chain_mask_2g=4 : for 2g rx chain use PHYB and chain 0 268 * 269 * Related: None 270 * 271 * Supported Feature: All profiles 272 * 273 * Usage: External 274 * 275 * </ini> 276 */ 277 #define CFG_RX_CHAIN_MASK_2G CFG_INI_UINT( \ 278 "rx_chain_mask_2g", \ 279 0, \ 280 4, \ 281 0, \ 282 CFG_VALUE_OR_DEFAULT, \ 283 "2.4G Rx Chainmask") 284 285 /* 286 * <ini> 287 * tx_chain_mask_5g - tx chain mask for 5g 288 * @Min: 0 289 * @Max: 6 290 * @Default: 0 291 * 292 * This ini will set tx chain mask for 5g. To use the ini, make sure: 293 * gSetTxChainmask1x1/gSetRxChainmask1x1 = 0, 294 * gDualMacFeatureDisable = 1 295 * gEnable2x2 = 0 296 * 297 * tx_chain_mask_5g=0 : don't care 298 * tx_chain_mask_5g=1 : for 5g tx use chain 0, Genoa use chain 1 299 * tx_chain_mask_5g=2 : for 5g tx use chain 1, Genoa use chain 2 300 * tx_chain_mask_5g=3 : for 5g tx can use either chain 301 * 302 * QCN7605 DBS chip has 3 RF chains. 303 * Chain0 for 2G, Chain1 for 2G/5G, Chain2 for 5G. 304 * DBS mode need 3 bits to map chainmask and halphy. 305 * In HW design, PHYA0 always Connects to shared RF chain1. 306 * tx_chain_mask_5g=4 : for 5g tx chain use PHYB and chain 2 307 * tx_chain_mask_5g=5 : for 5g tx chain use PHYA and chain 1 308 * tx_chain_mask_5g=6 : for 5g tx chain use PHYA and chain 2 309 * 310 * Related: None 311 * 312 * Supported Feature: All profiles 313 * 314 * Usage: External 315 * 316 * </ini> 317 */ 318 #define CFG_TX_CHAIN_MASK_5G CFG_INI_UINT( \ 319 "tx_chain_mask_5g", \ 320 0, \ 321 6, \ 322 0, \ 323 CFG_VALUE_OR_DEFAULT, \ 324 "5Ghz Tx Chainmask") 325 326 /* 327 * <ini> 328 * rx_chain_mask_5g - rx chain mask for 5g 329 * @Min: 0 330 * @Max: 6 331 * @Default: 0 332 * 333 * This ini will set rx chain mask for 5g. To use the ini, make sure: 334 * gSetTxChainmask1x1/gSetRxChainmask1x1 = 0, 335 * gDualMacFeatureDisable = 1 336 * gEnable2x2 = 0 337 * 338 * rx_chain_mask_5g=0 : don't care 339 * rx_chain_mask_5g=1 : for 5g rx use chain 0, Genoa use chain 1 340 * rx_chain_mask_5g=2 : for 5g rx use chain 1, Genoa use chain 2 341 * rx_chain_mask_5g=3 : for 5g rx can use either chain 342 * 343 * QCN7605 DBS chip has 3 RF chains. 344 * Chain0 for 2G, Chain1 for 2G/5G, Chain2 for 5G. 345 * DBS mode need 3 bits to map halphy and chain. 346 * HW design, PHYA0 always Connects to shared RF chain1. 347 * rx_chain_mask_5g=4 : for 5g rx chain use PHYB and chain 2 348 * rx_chain_mask_5g=5 : for 5g rx chain use PHYA and chain 1 349 * rx_chain_mask_5g=6 : for 5g rx chain use PHYB and chain 2 350 * 351 * Related: None 352 * 353 * Supported Feature: All profiles 354 * 355 * Usage: External 356 * 357 * </ini> 358 */ 359 #define CFG_RX_CHAIN_MASK_5G CFG_INI_UINT( \ 360 "rx_chain_mask_5g", \ 361 0, \ 362 6, \ 363 0, \ 364 CFG_VALUE_OR_DEFAULT, \ 365 "5Ghz Rx Chainmask") 366 367 /* 368 * <ini> 369 * enable_bt_chain_separation - Enables/disables bt /wlan chainmask assignment 370 * @Min: 0 371 * @Max: 1 372 * @Default: 0 373 * 374 * This ini disables/enables chainmask setting on 2x2, mainly used for ROME 375 * BT/WLAN chainmask assignment. 376 * 377 * 0, Disable 378 * 1, Enable 379 * 380 * Related: NA 381 * 382 * Supported Feature: 11n/11ac 383 * 384 * Usage: External 385 * 386 * </ini> 387 */ 388 #define CFG_ENABLE_BT_CHAIN_SEPARATION CFG_INI_BOOL( \ 389 "enableBTChainSeparation", \ 390 0, \ 391 "Enable/disable BT chainmask assignment") 392 393 #define CFG_CHAINMASK_ALL \ 394 CFG(CFG_VHT_ENABLE_1x1_TX_CHAINMASK) \ 395 CFG(CFG_VHT_ENABLE_1x1_RX_CHAINMASK) \ 396 CFG(CFG_TX_CHAIN_MASK_CCK) \ 397 CFG(CFG_TX_CHAIN_MASK_1SS) \ 398 CFG(CFG_11B_NUM_TX_CHAIN) \ 399 CFG(CFG_11AG_NUM_TX_CHAIN) \ 400 CFG(CFG_TX_CHAIN_MASK_2G) \ 401 CFG(CFG_RX_CHAIN_MASK_2G) \ 402 CFG(CFG_TX_CHAIN_MASK_5G) \ 403 CFG(CFG_RX_CHAIN_MASK_5G) \ 404 CFG(CFG_ENABLE_BT_CHAIN_SEPARATION) 405 406 #endif /* __CFG_CHAINMASK_H */ 407