1 /* 2 * Copyright 2016 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _CCU_SUN8I_A23_A33_H_ 18 #define _CCU_SUN8I_A23_A33_H_ 19 20 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> 21 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> 22 23 #define CLK_PLL_CPUX 0 24 #define CLK_PLL_AUDIO_BASE 1 25 #define CLK_PLL_AUDIO 2 26 #define CLK_PLL_AUDIO_2X 3 27 #define CLK_PLL_AUDIO_4X 4 28 #define CLK_PLL_AUDIO_8X 5 29 #define CLK_PLL_VIDEO 6 30 #define CLK_PLL_VIDEO_2X 7 31 #define CLK_PLL_VE 8 32 #define CLK_PLL_DDR0 9 33 #define CLK_PLL_PERIPH 10 34 #define CLK_PLL_PERIPH_2X 11 35 #define CLK_PLL_GPU 12 36 #define CLK_PLL_MIPI 13 37 #define CLK_PLL_HSIC 14 38 #define CLK_PLL_DE 15 39 #define CLK_PLL_DDR1 16 40 #define CLK_PLL_DDR 17 41 42 /* The CPUX clock is exported */ 43 44 #define CLK_AXI 19 45 #define CLK_AHB1 20 46 #define CLK_APB1 21 47 #define CLK_APB2 22 48 49 /* All the bus gates are exported */ 50 51 /* The first part of the mod clocks is exported */ 52 53 #define CLK_DRAM 79 54 55 /* Some more module clocks are exported */ 56 57 #define CLK_MBUS 95 58 59 /* And the last module clocks are exported */ 60 61 #define CLK_NUMBER (CLK_ATS + 1) 62 63 #endif /* _CCU_SUN8I_A23_A33_H_ */ 64