1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef _CNSS_MAIN_H
8 #define _CNSS_MAIN_H
9
10 #if IS_ENABLED(CONFIG_ARM) || IS_ENABLED(CONFIG_ARM64)
11 #include <asm/arch_timer.h>
12 #endif
13 #if IS_ENABLED(CONFIG_ESOC)
14 #include <linux/esoc_client.h>
15 #endif
16 #include <linux/etherdevice.h>
17 #include <linux/firmware.h>
18 #if IS_ENABLED(CONFIG_INTERCONNECT)
19 #include <linux/interconnect.h>
20 #endif
21 #include <linux/mailbox_client.h>
22 #include <linux/pm_qos.h>
23 #include <linux/of.h>
24 #include <linux/platform_device.h>
25 #include <linux/time64.h>
26 #if IS_ENABLED(CONFIG_MSM_QMP)
27 #include <linux/mailbox/qmp.h>
28 #endif
29 #ifdef CONFIG_CNSS_OUT_OF_TREE
30 #include "cnss2.h"
31 #else
32 #include <net/cnss2.h>
33 #endif
34 #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2) || IS_ENABLED(CONFIG_QCOM_MINIDUMP)
35 #include <soc/qcom/memory_dump.h>
36 #endif
37 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART) || \
38 IS_ENABLED(CONFIG_QCOM_RAMDUMP)
39 #include <soc/qcom/qcom_ramdump.h>
40 #endif
41 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
42 #include <soc/qcom/subsystem_notif.h>
43 #include <soc/qcom/subsystem_restart.h>
44 #endif
45 #include <linux/iommu.h>
46 #include "qmi.h"
47 #include "cnss_prealloc.h"
48 #include "cnss_common.h"
49
50 #define MAX_NO_OF_MAC_ADDR 4
51 #define QMI_WLFW_MAX_TIMESTAMP_LEN 32
52 #define QMI_WLFW_MAX_BUILD_ID_LEN 128
53 #define CNSS_RDDM_TIMEOUT_MS 20000
54 #define RECOVERY_TIMEOUT 60000
55 #define WLAN_WD_TIMEOUT_MS 60000
56 #define WLAN_COLD_BOOT_CAL_TIMEOUT 60000
57 #define WLAN_MISSION_MODE_TIMEOUT 30000
58 #define TIME_CLOCK_FREQ_HZ 19200000
59 #define CNSS_RAMDUMP_MAGIC 0x574C414E
60 #define CNSS_RAMDUMP_VERSION 0
61 #define MAX_FIRMWARE_NAME_LEN 40
62 #define FW_V1_NUMBER 1
63 #define FW_V2_NUMBER 2
64 #ifdef CONFIG_CNSS_SUPPORT_DUAL_DEV
65 #define POWER_ON_RETRY_MAX_TIMES 2
66 #else
67 #define POWER_ON_RETRY_MAX_TIMES 4
68 #endif
69 #define POWER_ON_RETRY_DELAY_MS 500
70 #define CNSS_FS_NAME "cnss"
71 #define CNSS_FS_NAME_SIZE 15
72 #define CNSS_DEVICE_NAME_SIZE 16
73 #define QRTR_NODE_FW_ID_BASE 7
74
75 #define POWER_ON_RETRY_DELAY_MS 500
76 #define WLFW_MAX_HANG_EVENT_DATA_SIZE 384
77
78 #define CNSS_EVENT_SYNC BIT(0)
79 #define CNSS_EVENT_UNINTERRUPTIBLE BIT(1)
80 #define CNSS_EVENT_UNKILLABLE BIT(2)
81 #define CNSS_EVENT_SYNC_UNINTERRUPTIBLE (CNSS_EVENT_SYNC | \
82 CNSS_EVENT_UNINTERRUPTIBLE)
83 #define CNSS_EVENT_SYNC_UNKILLABLE (CNSS_EVENT_SYNC | CNSS_EVENT_UNKILLABLE)
84 #define QMI_WLFW_MAX_TME_OPT_FILE_NUM 3
85 #define TME_OEM_FUSE_FILE_NAME "peach_sec.dat"
86 #define TME_RPR_FILE_NAME "peach_rpr.bin"
87 #define TME_DPR_FILE_NAME "peach_dpr.bin"
88
89 enum cnss_dt_type {
90 CNSS_DTT_LEGACY = 0,
91 CNSS_DTT_CONVERGED = 1,
92 CNSS_DTT_MULTIEXCHG = 2
93 };
94
95 enum cnss_dev_bus_type {
96 CNSS_BUS_NONE = -1,
97 CNSS_BUS_PCI,
98 CNSS_BUS_MAX
99 };
100
101 struct cnss_vreg_cfg {
102 const char *name;
103 u32 min_uv;
104 u32 max_uv;
105 u32 load_ua;
106 u32 delay_us;
107 u32 need_unvote;
108 };
109
110 struct cnss_vreg_info {
111 struct list_head list;
112 struct regulator *reg;
113 struct cnss_vreg_cfg cfg;
114 u32 enabled;
115 };
116
117 enum cnss_vreg_type {
118 CNSS_VREG_PRIM,
119 };
120
121 struct cnss_clk_cfg {
122 const char *name;
123 u32 freq;
124 u32 required;
125 };
126
127 struct cnss_clk_info {
128 struct list_head list;
129 struct clk *clk;
130 struct cnss_clk_cfg cfg;
131 u32 enabled;
132 };
133
134 struct cnss_pinctrl_info {
135 struct pinctrl *pinctrl;
136 struct pinctrl_state *bootstrap_active;
137 struct pinctrl_state *sol_default;
138 struct pinctrl_state *wlan_en_active;
139 struct pinctrl_state *wlan_en_sleep;
140 struct pinctrl_state *sw_ctrl;
141 struct pinctrl_state *sw_ctrl_wl_cx;
142 int bt_en_gpio;
143 int wlan_en_gpio;
144 int xo_clk_gpio; /*qca6490 only */
145 int sw_ctrl_gpio;
146 int wlan_sw_ctrl_gpio;
147 };
148
149 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
150 struct cnss_subsys_info {
151 struct subsys_device *subsys_device;
152 struct subsys_desc subsys_desc;
153 void *subsys_handle;
154 };
155 #endif
156
157 struct cnss_ramdump_info {
158 void *ramdump_dev;
159 unsigned long ramdump_size;
160 void *ramdump_va;
161 phys_addr_t ramdump_pa;
162 #if IS_ENABLED(CONFIG_QCOM_MEMORY_DUMP_V2)
163 struct msm_dump_data dump_data;
164 #endif
165 };
166
167 struct cnss_dump_seg {
168 unsigned long address;
169 void *v_address;
170 unsigned long size;
171 u32 type;
172 };
173
174 struct cnss_dump_data {
175 u32 version;
176 u32 magic;
177 char name[32];
178 phys_addr_t paddr;
179 int nentries;
180 u32 seg_version;
181 };
182
183 struct cnss_ramdump_info_v2 {
184 void *ramdump_dev;
185 unsigned long ramdump_size;
186 void *dump_data_vaddr;
187 u8 dump_data_valid;
188 struct cnss_dump_data dump_data;
189 };
190
191 #if IS_ENABLED(CONFIG_ESOC)
192 struct cnss_esoc_info {
193 struct esoc_desc *esoc_desc;
194 u8 notify_modem_status;
195 void *modem_notify_handler;
196 int modem_current_status;
197 };
198 #endif
199
200 #if IS_ENABLED(CONFIG_INTERCONNECT)
201 /**
202 * struct cnss_bus_bw_cfg - Interconnect vote data
203 * @avg_bw: Vote for average bandwidth
204 * @peak_bw: Vote for peak bandwidth
205 */
206 struct cnss_bus_bw_cfg {
207 u32 avg_bw;
208 u32 peak_bw;
209 };
210
211 /* Number of bw votes (avg, peak) entries that ICC requires */
212 #define CNSS_ICC_VOTE_MAX 2
213
214 /**
215 * struct cnss_bus_bw_info - Bus bandwidth config for interconnect path
216 * @list: Kernel linked list
217 * @icc_name: Name of interconnect path as defined in Device tree
218 * @icc_path: Interconnect path data structure
219 * @cfg_table: Interconnect vote data for average and peak bandwidth
220 */
221 struct cnss_bus_bw_info {
222 struct list_head list;
223 const char *icc_name;
224 struct icc_path *icc_path;
225 struct cnss_bus_bw_cfg *cfg_table;
226 };
227 #endif
228
229 /**
230 * struct cnss_interconnect_cfg - CNSS platform interconnect config
231 * @list_head: List of interconnect path bandwidth configs
232 * @path_count: Count of interconnect path configured in device tree
233 * @current_bw_vote: WLAN driver provided bandwidth vote
234 * @bus_bw_cfg_count: Number of bandwidth configs for voting. It is the array
235 * size of struct cnss_bus_bw_info.cfg_table
236 */
237 struct cnss_interconnect_cfg {
238 struct list_head list_head;
239 u32 path_count;
240 int current_bw_vote;
241 u32 bus_bw_cfg_count;
242 };
243
244 struct cnss_fw_mem {
245 size_t size;
246 void *va;
247 phys_addr_t pa;
248 u8 valid;
249 u32 type;
250 unsigned long attrs;
251 };
252
253 struct wlfw_rf_chip_info {
254 u32 chip_id;
255 u32 chip_family;
256 };
257
258 struct wlfw_rf_board_info {
259 u32 board_id;
260 };
261
262 struct wlfw_soc_info {
263 u32 soc_id;
264 };
265
266 struct wlfw_fw_version_info {
267 u32 fw_version;
268 char fw_build_timestamp[QMI_WLFW_MAX_TIMESTAMP_LEN + 1];
269 };
270
271 enum cnss_mem_type {
272 CNSS_MEM_TYPE_MSA,
273 CNSS_MEM_TYPE_DDR,
274 CNSS_MEM_BDF,
275 CNSS_MEM_M3,
276 CNSS_MEM_CAL_V01,
277 CNSS_MEM_DPD_V01,
278 CNSS_MEM_AUX,
279 };
280
281 enum cnss_fw_dump_type {
282 CNSS_FW_IMAGE,
283 CNSS_FW_RDDM,
284 CNSS_FW_REMOTE_HEAP,
285 CNSS_FW_CAL,
286 CNSS_FW_DUMP_TYPE_MAX,
287 };
288
289 struct cnss_dump_entry {
290 int type;
291 u32 entry_start;
292 u32 entry_num;
293 };
294
295 struct cnss_dump_meta_info {
296 u32 magic;
297 u32 version;
298 u32 chipset;
299 u32 total_entries;
300 struct cnss_dump_entry entry[CNSS_FW_DUMP_TYPE_MAX];
301 };
302
303 struct cnss_host_dump_meta_info {
304 u32 magic;
305 u32 version;
306 u32 chipset;
307 u32 total_entries;
308 struct cnss_dump_entry entry[CNSS_HOST_DUMP_TYPE_MAX];
309 };
310
311 enum cnss_driver_event_type {
312 CNSS_DRIVER_EVENT_SERVER_ARRIVE,
313 CNSS_DRIVER_EVENT_SERVER_EXIT,
314 CNSS_DRIVER_EVENT_REQUEST_MEM,
315 CNSS_DRIVER_EVENT_FW_MEM_READY,
316 CNSS_DRIVER_EVENT_FW_READY,
317 CNSS_DRIVER_EVENT_COLD_BOOT_CAL_START,
318 CNSS_DRIVER_EVENT_COLD_BOOT_CAL_DONE,
319 CNSS_DRIVER_EVENT_REGISTER_DRIVER,
320 CNSS_DRIVER_EVENT_UNREGISTER_DRIVER,
321 CNSS_DRIVER_EVENT_RECOVERY,
322 CNSS_DRIVER_EVENT_FORCE_FW_ASSERT,
323 CNSS_DRIVER_EVENT_POWER_UP,
324 CNSS_DRIVER_EVENT_POWER_DOWN,
325 CNSS_DRIVER_EVENT_IDLE_RESTART,
326 CNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
327 CNSS_DRIVER_EVENT_IMS_WFC_CALL_IND,
328 CNSS_DRIVER_EVENT_WLFW_TWT_CFG_IND,
329 CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
330 CNSS_DRIVER_EVENT_FW_MEM_FILE_SAVE,
331 CNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
332 CNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
333 CNSS_DRIVER_EVENT_MAX,
334 };
335
336 enum cnss_driver_state {
337 CNSS_QMI_WLFW_CONNECTED = 0,
338 CNSS_FW_MEM_READY,
339 CNSS_FW_READY,
340 CNSS_IN_COLD_BOOT_CAL,
341 CNSS_DRIVER_LOADING,
342 CNSS_DRIVER_UNLOADING = 5,
343 CNSS_DRIVER_IDLE_RESTART,
344 CNSS_DRIVER_IDLE_SHUTDOWN,
345 CNSS_DRIVER_PROBED,
346 CNSS_DRIVER_RECOVERY,
347 CNSS_FW_BOOT_RECOVERY = 10,
348 CNSS_DEV_ERR_NOTIFY,
349 CNSS_DRIVER_DEBUG,
350 CNSS_COEX_CONNECTED,
351 CNSS_IMS_CONNECTED,
352 CNSS_IN_SUSPEND_RESUME = 15,
353 CNSS_IN_REBOOT,
354 CNSS_COLD_BOOT_CAL_DONE,
355 CNSS_IN_PANIC,
356 CNSS_QMI_DEL_SERVER,
357 CNSS_QMI_DMS_CONNECTED = 20,
358 CNSS_DAEMON_CONNECTED,
359 CNSS_PCI_PROBE_DONE,
360 CNSS_DRIVER_REGISTER,
361 CNSS_WLAN_HW_DISABLED,
362 CNSS_FS_READY = 25,
363 CNSS_DRIVER_REGISTERED,
364 CNSS_DMS_DEL_SERVER,
365 CNSS_POWER_OFF,
366 };
367
368 struct cnss_recovery_data {
369 enum cnss_recovery_reason reason;
370 };
371
372 enum cnss_pins {
373 CNSS_WLAN_EN,
374 CNSS_PCIE_TXP,
375 CNSS_PCIE_TXN,
376 CNSS_PCIE_RXP,
377 CNSS_PCIE_RXN,
378 CNSS_PCIE_REFCLKP,
379 CNSS_PCIE_REFCLKN,
380 CNSS_PCIE_RST,
381 CNSS_PCIE_WAKE,
382 };
383
384 struct cnss_pin_connect_result {
385 u32 fw_pwr_pin_result;
386 u32 fw_phy_io_pin_result;
387 u32 fw_rf_pin_result;
388 u32 host_pin_result;
389 };
390
391 enum cnss_debug_quirks {
392 LINK_DOWN_SELF_RECOVERY,
393 SKIP_DEVICE_BOOT,
394 USE_CORE_ONLY_FW,
395 SKIP_RECOVERY,
396 QMI_BYPASS,
397 ENABLE_WALTEST,
398 ENABLE_PCI_LINK_DOWN_PANIC,
399 FBC_BYPASS,
400 ENABLE_DAEMON_SUPPORT,
401 DISABLE_DRV,
402 DISABLE_IO_COHERENCY,
403 IGNORE_PCI_LINK_FAILURE,
404 DISABLE_TIME_SYNC,
405 FORCE_ONE_MSI,
406 QUIRK_MAX_VALUE
407 };
408
409 enum cnss_bdf_type {
410 CNSS_BDF_BIN,
411 CNSS_BDF_ELF,
412 CNSS_BDF_REGDB = 4,
413 CNSS_BDF_HDS = 6,
414 };
415
416 enum cnss_cal_status {
417 CNSS_CAL_DONE,
418 CNSS_CAL_TIMEOUT,
419 CNSS_CAL_FAILURE,
420 };
421
422 struct cnss_cal_info {
423 enum cnss_cal_status cal_status;
424 };
425
426 /**
427 * enum cnss_time_sync_period_vote - to get per vote time sync period
428 * @TIME_SYNC_VOTE_WLAN: WLAN Driver vote
429 * @TIME_SYNC_VOTE_CNSS: sys config vote
430 * @TIME_SYNC_VOTE_MAX
431 */
432 enum cnss_time_sync_period_vote {
433 TIME_SYNC_VOTE_WLAN,
434 TIME_SYNC_VOTE_CNSS,
435 TIME_SYNC_VOTE_MAX,
436 };
437
438 struct cnss_control_params {
439 unsigned long quirks;
440 unsigned int mhi_timeout;
441 unsigned int mhi_m2_timeout;
442 unsigned int qmi_timeout;
443 unsigned int bdf_type;
444 unsigned int time_sync_period;
445 unsigned int time_sync_period_vote[TIME_SYNC_VOTE_MAX];
446 };
447
448 struct cnss_tcs_info {
449 resource_size_t cmd_base_addr;
450 void __iomem *cmd_base_addr_io;
451 };
452
453 struct cnss_cpr_info {
454 resource_size_t tcs_cmd_data_addr;
455 void __iomem *tcs_cmd_data_addr_io;
456 u32 cpr_pmic_addr;
457 u32 voltage;
458 };
459
460 enum cnss_ce_index {
461 CNSS_CE_00,
462 CNSS_CE_01,
463 CNSS_CE_02,
464 CNSS_CE_03,
465 CNSS_CE_04,
466 CNSS_CE_05,
467 CNSS_CE_06,
468 CNSS_CE_07,
469 CNSS_CE_08,
470 CNSS_CE_09,
471 CNSS_CE_10,
472 CNSS_CE_11,
473 CNSS_CE_COMMON,
474 };
475
476 struct cnss_dms_data {
477 u32 mac_valid;
478 u8 mac[QMI_WLFW_MAC_ADDR_SIZE_V01];
479 };
480
481 enum cnss_timeout_type {
482 CNSS_TIMEOUT_QMI,
483 CNSS_TIMEOUT_POWER_UP,
484 CNSS_TIMEOUT_IDLE_RESTART,
485 CNSS_TIMEOUT_CALIBRATION,
486 CNSS_TIMEOUT_WLAN_WATCHDOG,
487 CNSS_TIMEOUT_RDDM,
488 CNSS_TIMEOUT_RECOVERY,
489 CNSS_TIMEOUT_DAEMON_CONNECTION,
490 };
491
492 struct cnss_sol_gpio {
493 int dev_sol_gpio;
494 int dev_sol_irq;
495 u32 dev_sol_counter;
496 int host_sol_gpio;
497 };
498
499 struct cnss_thermal_cdev {
500 struct list_head tcdev_list;
501 int tcdev_id;
502 unsigned long curr_thermal_state;
503 unsigned long max_thermal_state;
504 struct device_node *dev_node;
505 struct thermal_cooling_device *tcdev;
506 };
507
508 struct cnss_plat_data {
509 struct platform_device *plat_dev;
510 void *bus_priv;
511 enum cnss_dev_bus_type bus_type;
512 struct list_head vreg_list;
513 struct list_head clk_list;
514 struct cnss_pinctrl_info pinctrl_info;
515 struct cnss_sol_gpio sol_gpio;
516 #if IS_ENABLED(CONFIG_MSM_SUBSYSTEM_RESTART)
517 struct cnss_subsys_info subsys_info;
518 #endif
519 struct cnss_ramdump_info ramdump_info;
520 struct cnss_ramdump_info_v2 ramdump_info_v2;
521 #if IS_ENABLED(CONFIG_ESOC)
522 struct cnss_esoc_info esoc_info;
523 #endif
524 struct cnss_interconnect_cfg icc;
525 struct notifier_block modem_nb;
526 struct notifier_block reboot_nb;
527 struct notifier_block panic_nb;
528 struct cnss_platform_cap cap;
529 struct pm_qos_request qos_request;
530 struct cnss_device_version device_version;
531 u32 rc_num;
532 unsigned long device_id;
533 enum cnss_driver_status driver_status;
534 u32 recovery_count;
535 u8 recovery_enabled;
536 u8 recovery_pcss_enabled;
537 u8 hds_enabled;
538 unsigned long driver_state;
539 struct list_head event_list;
540 struct list_head cnss_tcdev_list;
541 struct mutex tcdev_lock; /* mutex for cooling devices list access */
542 spinlock_t event_lock; /* spinlock for driver work event handling */
543 struct work_struct event_work;
544 struct workqueue_struct *event_wq;
545 struct work_struct recovery_work;
546 struct delayed_work wlan_reg_driver_work;
547 struct qmi_handle qmi_wlfw;
548 struct qmi_handle qmi_dms;
549 struct wlfw_rf_chip_info chip_info;
550 struct wlfw_rf_board_info board_info;
551 struct wlfw_soc_info soc_info;
552 struct wlfw_fw_version_info fw_version_info;
553 struct cnss_dev_mem_info dev_mem_info[CNSS_MAX_DEV_MEM_NUM];
554 char fw_build_id[QMI_WLFW_MAX_BUILD_ID_LEN + 1];
555 u32 otp_version;
556 u32 fw_mem_seg_len;
557 struct cnss_fw_mem fw_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01];
558 struct cnss_fw_mem m3_mem;
559 struct cnss_fw_mem tme_lite_mem;
560 struct cnss_fw_mem tme_opt_file_mem[QMI_WLFW_MAX_TME_OPT_FILE_NUM];
561 struct cnss_fw_mem *cal_mem;
562 struct cnss_fw_mem aux_mem;
563 u64 cal_time;
564 bool cbc_file_download;
565 u32 cal_file_size;
566 struct completion daemon_connected;
567 u32 qdss_mem_seg_len;
568 struct cnss_fw_mem qdss_mem[QMI_WLFW_MAX_NUM_MEM_SEG_V01];
569 u32 *qdss_reg;
570 struct cnss_pin_connect_result pin_result;
571 struct dentry *root_dentry;
572 atomic_t pm_count;
573 struct timer_list fw_boot_timer;
574 struct completion power_up_complete;
575 struct completion cal_complete;
576 struct mutex dev_lock; /* mutex for register access through debugfs */
577 struct mutex driver_ops_lock; /* mutex for external driver ops */
578 struct cnss_wlan_driver *driver_ops;
579 u32 supported_link_speed;
580 u32 device_freq_hz;
581 u32 diag_reg_read_addr;
582 u32 diag_reg_read_mem_type;
583 u32 diag_reg_read_len;
584 u8 *diag_reg_read_buf;
585 u8 cal_done;
586 u8 powered_on;
587 u8 use_fw_path_with_prefix;
588 char firmware_name[MAX_FIRMWARE_NAME_LEN];
589 char fw_fallback_name[MAX_FIRMWARE_NAME_LEN];
590 #ifndef CONFIG_DISABLE_CNSS_SRAM_DUMP
591 u8 *sram_dump;
592 #endif
593 struct completion rddm_complete;
594 struct completion recovery_complete;
595 struct cnss_control_params ctrl_params;
596 struct cnss_cpr_info cpr_info;
597 u64 antenna;
598 u64 grant;
599 struct qmi_handle coex_qmi;
600 struct qmi_handle ims_qmi;
601 struct qmi_txn txn;
602 struct wakeup_source *recovery_ws;
603 u64 dynamic_feature;
604 void *get_info_cb_ctx;
605 int (*get_info_cb)(void *ctx, void *event, int event_len);
606 void *get_driver_async_data_ctx;
607 int (*get_driver_async_data_cb)(void *ctx, uint16_t type, void *event, int event_len);
608 bool cbc_enabled;
609 u8 use_pm_domain;
610 u8 use_nv_mac;
611 u8 set_wlaon_pwr_ctrl;
612 struct cnss_tcs_info tcs_info;
613 bool fw_pcie_gen_switch;
614 bool fw_aux_uc_support;
615 u64 fw_caps;
616 u8 pcie_gen_speed;
617 struct iommu_domain *audio_iommu_domain;
618 bool is_audio_shared_iommu_group;
619 struct cnss_dms_data dms;
620 int power_up_error;
621 u32 hw_trc_override;
622 u8 charger_mode;
623 struct mbox_client mbox_client_data;
624 struct mbox_chan *mbox_chan;
625 struct qmp *qmp;
626 const char *vreg_ol_cpr, *vreg_ipa;
627 const char **pdc_init_table, **vreg_pdc_map, **pmu_vreg_map;
628 int pdc_init_table_len, vreg_pdc_map_len, pmu_vreg_map_len;
629 bool adsp_pc_enabled;
630 u64 feature_list;
631 u32 dt_type;
632 struct kobject *wifi_kobj;
633 u16 hang_event_data_len;
634 u32 hang_data_addr_offset;
635 /* bitmap to detect FEM combination */
636 u8 hwid_bitmap;
637 uint32_t num_shadow_regs_v3;
638 bool sec_peri_feature_disable;
639 struct device_node *dev_node;
640 char device_name[CNSS_DEVICE_NAME_SIZE];
641 u32 plat_idx;
642 bool enumerate_done;
643 int qrtr_node_id;
644 unsigned int wlfw_service_instance_id;
645 const char *pld_bus_ops_name;
646 u32 on_chip_pmic_devices_count;
647 u32 *on_chip_pmic_board_ids;
648 bool no_bwscale;
649 bool sleep_clk;
650 struct wlchip_serial_id_v01 serial_id;
651 };
652
653 #if IS_ENABLED(CONFIG_ARCH_QCOM)
cnss_get_host_timestamp(struct cnss_plat_data * plat_priv)654 static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv)
655 {
656 u64 ticks = __arch_counter_get_cntvct();
657
658 do_div(ticks, TIME_CLOCK_FREQ_HZ / 100000);
659
660 return ticks * 10;
661 }
662 #else
cnss_get_host_timestamp(struct cnss_plat_data * plat_priv)663 static inline u64 cnss_get_host_timestamp(struct cnss_plat_data *plat_priv)
664 {
665 struct timespec64 ts;
666
667 ktime_get_ts64(&ts);
668
669 return (ts.tv_sec * 1000000) + (ts.tv_nsec / 1000);
670 }
671 #endif
672
673 int cnss_wlan_hw_disable_check(struct cnss_plat_data *plat_priv);
674 int cnss_wlan_hw_enable(void);
675 struct cnss_plat_data *cnss_get_plat_priv(struct platform_device *plat_dev);
676 struct cnss_plat_data *cnss_get_first_plat_priv(struct platform_device *plat_dev);
677 void cnss_pm_stay_awake(struct cnss_plat_data *plat_priv);
678 void cnss_pm_relax(struct cnss_plat_data *plat_priv);
679 struct cnss_plat_data *cnss_get_plat_priv_by_rc_num(int rc_num);
680 int cnss_get_max_plat_env_count(void);
681 struct cnss_plat_data *cnss_get_plat_env(int index);
682 void cnss_get_qrtr_info(struct cnss_plat_data *plat_priv);
683 void cnss_get_sleep_clk_supported(struct cnss_plat_data *plat_priv);
684 void cnss_get_bwscal_info(struct cnss_plat_data *plat_priv);
685 bool cnss_is_dual_wlan_enabled(void);
686 int cnss_driver_event_post(struct cnss_plat_data *plat_priv,
687 enum cnss_driver_event_type type,
688 u32 flags, void *data);
689 int cnss_get_vreg_type(struct cnss_plat_data *plat_priv,
690 enum cnss_vreg_type type);
691 void cnss_put_vreg_type(struct cnss_plat_data *plat_priv,
692 enum cnss_vreg_type type);
693 int cnss_vreg_on_type(struct cnss_plat_data *plat_priv,
694 enum cnss_vreg_type type);
695 int cnss_vreg_off_type(struct cnss_plat_data *plat_priv,
696 enum cnss_vreg_type type);
697 int cnss_get_clk(struct cnss_plat_data *plat_priv);
698 void cnss_put_clk(struct cnss_plat_data *plat_priv);
699 int cnss_vreg_unvote_type(struct cnss_plat_data *plat_priv,
700 enum cnss_vreg_type type);
701 int cnss_get_pinctrl(struct cnss_plat_data *plat_priv);
702 int cnss_get_wlan_sw_ctrl(struct cnss_plat_data *plat_priv);
703 int cnss_power_on_device(struct cnss_plat_data *plat_priv, bool reset);
704 void cnss_power_off_device(struct cnss_plat_data *plat_priv);
705 bool cnss_is_device_powered_on(struct cnss_plat_data *plat_priv);
706 int cnss_enable_dev_sol_irq(struct cnss_plat_data *plat_priv);
707 int cnss_disable_dev_sol_irq(struct cnss_plat_data *plat_priv);
708 int cnss_get_dev_sol_value(struct cnss_plat_data *plat_priv);
709 int cnss_init_dev_sol_irq(struct cnss_plat_data *plat_priv);
710 int cnss_deinit_dev_sol_irq(struct cnss_plat_data *plat_priv);
711 int cnss_set_host_sol_value(struct cnss_plat_data *plat_priv, int value);
712 int cnss_get_host_sol_value(struct cnss_plat_data *plat_priv);
713 int cnss_register_subsys(struct cnss_plat_data *plat_priv);
714 void cnss_unregister_subsys(struct cnss_plat_data *plat_priv);
715 int cnss_register_ramdump(struct cnss_plat_data *plat_priv);
716 void cnss_unregister_ramdump(struct cnss_plat_data *plat_priv);
717 int cnss_do_ramdump(struct cnss_plat_data *plat_priv);
718 int cnss_do_elf_ramdump(struct cnss_plat_data *plat_priv);
719 int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
720 struct cnss_ssr_driver_dump_entry *ssr_entry,
721 size_t num_entries_loaded);
722 void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv);
723 int cnss_get_cpr_info(struct cnss_plat_data *plat_priv);
724 int cnss_update_cpr_info(struct cnss_plat_data *plat_priv);
725 int cnss_va_to_pa(struct device *dev, size_t size, void *va, dma_addr_t dma,
726 phys_addr_t *pa, unsigned long attrs);
727 int cnss_minidump_add_region(struct cnss_plat_data *plat_priv,
728 enum cnss_fw_dump_type type, int seg_no,
729 void *va, phys_addr_t pa, size_t size);
730 int cnss_minidump_remove_region(struct cnss_plat_data *plat_priv,
731 enum cnss_fw_dump_type type, int seg_no,
732 void *va, phys_addr_t pa, size_t size);
733 int cnss_enable_int_pow_amp_vreg(struct cnss_plat_data *plat_priv);
734 int cnss_get_tcs_info(struct cnss_plat_data *plat_priv);
735 unsigned int cnss_get_timeout(struct cnss_plat_data *plat_priv,
736 enum cnss_timeout_type);
737 int cnss_aop_interface_init(struct cnss_plat_data *plat_priv);
738 void cnss_aop_interface_deinit(struct cnss_plat_data *plat_priv);
739 int cnss_aop_pdc_reconfig(struct cnss_plat_data *plat_priv);
740 int cnss_aop_send_msg(struct cnss_plat_data *plat_priv, char *msg);
741 void cnss_power_misc_params_init(struct cnss_plat_data *plat_priv);
742 int cnss_aop_ol_cpr_cfg_setup(struct cnss_plat_data *plat_priv,
743 struct wlfw_pmu_cfg_v01 *fw_pmu_cfg);
744 int cnss_request_firmware_direct(struct cnss_plat_data *plat_priv,
745 const struct firmware **fw_entry,
746 const char *filename);
747 int cnss_set_feature_list(struct cnss_plat_data *plat_priv,
748 enum cnss_feature_v01 feature);
749 int cnss_clear_feature_list(struct cnss_plat_data *plat_priv,
750 enum cnss_feature_v01 feature);
751 int cnss_get_feature_list(struct cnss_plat_data *plat_priv,
752 u64 *feature_list);
753 int cnss_get_input_gpio_value(struct cnss_plat_data *plat_priv, int gpio_num);
754 bool cnss_check_driver_loading_allowed(void);
755 int cnss_dev_specific_power_on(struct cnss_plat_data *plat_priv);
756 void cnss_recovery_handler(struct cnss_plat_data *plat_priv);
757 size_t cnss_get_platform_name(struct cnss_plat_data *plat_priv,
758 char *buf, const size_t buf_len);
759 int cnss_iommu_map(struct iommu_domain *domain, unsigned long iova,
760 phys_addr_t paddr, size_t size, int prot);
761 #endif /* _CNSS_MAIN_H */
762