1 /* 2 * include/linux/irqchip/arm-gic.h 3 * 4 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef __LINUX_IRQCHIP_ARM_GIC_H 11 #define __LINUX_IRQCHIP_ARM_GIC_H 12 13 #define GIC_CPU_CTRL 0x00 14 #define GIC_CPU_PRIMASK 0x04 15 #define GIC_CPU_BINPOINT 0x08 16 #define GIC_CPU_INTACK 0x0c 17 #define GIC_CPU_EOI 0x10 18 #define GIC_CPU_RUNNINGPRI 0x14 19 #define GIC_CPU_HIGHPRI 0x18 20 #define GIC_CPU_ALIAS_BINPOINT 0x1c 21 #define GIC_CPU_ACTIVEPRIO 0xd0 22 #define GIC_CPU_IDENT 0xfc 23 #define GIC_CPU_DEACTIVATE 0x1000 24 25 #define GICC_ENABLE 0x1 26 #define GICC_INT_PRI_THRESHOLD 0xf0 27 28 #define GIC_CPU_CTRL_EnableGrp0_SHIFT 0 29 #define GIC_CPU_CTRL_EnableGrp0 (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT) 30 #define GIC_CPU_CTRL_EnableGrp1_SHIFT 1 31 #define GIC_CPU_CTRL_EnableGrp1 (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT) 32 #define GIC_CPU_CTRL_AckCtl_SHIFT 2 33 #define GIC_CPU_CTRL_AckCtl (1 << GIC_CPU_CTRL_AckCtl_SHIFT) 34 #define GIC_CPU_CTRL_FIQEn_SHIFT 3 35 #define GIC_CPU_CTRL_FIQEn (1 << GIC_CPU_CTRL_FIQEn_SHIFT) 36 #define GIC_CPU_CTRL_CBPR_SHIFT 4 37 #define GIC_CPU_CTRL_CBPR (1 << GIC_CPU_CTRL_CBPR_SHIFT) 38 #define GIC_CPU_CTRL_EOImodeNS_SHIFT 9 39 #define GIC_CPU_CTRL_EOImodeNS (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT) 40 41 #define GICC_IAR_INT_ID_MASK 0x3ff 42 #define GICC_INT_SPURIOUS 1023 43 #define GICC_DIS_BYPASS_MASK 0x1e0 44 45 #define GIC_DIST_CTRL 0x000 46 #define GIC_DIST_CTR 0x004 47 #define GIC_DIST_IIDR 0x008 48 #define GIC_DIST_IGROUP 0x080 49 #define GIC_DIST_ENABLE_SET 0x100 50 #define GIC_DIST_ENABLE_CLEAR 0x180 51 #define GIC_DIST_PENDING_SET 0x200 52 #define GIC_DIST_PENDING_CLEAR 0x280 53 #define GIC_DIST_ACTIVE_SET 0x300 54 #define GIC_DIST_ACTIVE_CLEAR 0x380 55 #define GIC_DIST_PRI 0x400 56 #define GIC_DIST_TARGET 0x800 57 #define GIC_DIST_CONFIG 0xc00 58 #define GIC_DIST_SOFTINT 0xf00 59 #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 60 #define GIC_DIST_SGI_PENDING_SET 0xf20 61 62 #define GICD_ENABLE 0x1 63 #define GICD_DISABLE 0x0 64 #define GICD_INT_ACTLOW_LVLTRIG 0x0 65 #define GICD_INT_EN_CLR_X32 0xffffffff 66 #define GICD_INT_EN_SET_SGI 0x0000ffff 67 #define GICD_INT_EN_CLR_PPI 0xffff0000 68 #define GICD_INT_DEF_PRI 0xa0 69 #define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\ 70 (GICD_INT_DEF_PRI << 16) |\ 71 (GICD_INT_DEF_PRI << 8) |\ 72 GICD_INT_DEF_PRI) 73 74 #define GICD_IIDR_IMPLEMENTER_SHIFT 0 75 #define GICD_IIDR_IMPLEMENTER_MASK (0xfff << GICD_IIDR_IMPLEMENTER_SHIFT) 76 #define GICD_IIDR_REVISION_SHIFT 12 77 #define GICD_IIDR_REVISION_MASK (0xf << GICD_IIDR_REVISION_SHIFT) 78 #define GICD_IIDR_VARIANT_SHIFT 16 79 #define GICD_IIDR_VARIANT_MASK (0xf << GICD_IIDR_VARIANT_SHIFT) 80 #define GICD_IIDR_PRODUCT_ID_SHIFT 24 81 #define GICD_IIDR_PRODUCT_ID_MASK (0xff << GICD_IIDR_PRODUCT_ID_SHIFT) 82 83 84 #define GICH_HCR 0x0 85 #define GICH_VTR 0x4 86 #define GICH_VMCR 0x8 87 #define GICH_MISR 0x10 88 #define GICH_EISR0 0x20 89 #define GICH_EISR1 0x24 90 #define GICH_ELRSR0 0x30 91 #define GICH_ELRSR1 0x34 92 #define GICH_APR 0xf0 93 #define GICH_LR0 0x100 94 95 #define GICH_HCR_EN (1 << 0) 96 #define GICH_HCR_UIE (1 << 1) 97 #define GICH_HCR_NPIE (1 << 3) 98 99 #define GICH_LR_VIRTUALID (0x3ff << 0) 100 #define GICH_LR_PHYSID_CPUID_SHIFT (10) 101 #define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT) 102 #define GICH_LR_PRIORITY_SHIFT 23 103 #define GICH_LR_STATE (3 << 28) 104 #define GICH_LR_PENDING_BIT (1 << 28) 105 #define GICH_LR_ACTIVE_BIT (1 << 29) 106 #define GICH_LR_EOI (1 << 19) 107 #define GICH_LR_GROUP1 (1 << 30) 108 #define GICH_LR_HW (1 << 31) 109 110 #define GICH_VMCR_ENABLE_GRP0_SHIFT 0 111 #define GICH_VMCR_ENABLE_GRP0_MASK (1 << GICH_VMCR_ENABLE_GRP0_SHIFT) 112 #define GICH_VMCR_ENABLE_GRP1_SHIFT 1 113 #define GICH_VMCR_ENABLE_GRP1_MASK (1 << GICH_VMCR_ENABLE_GRP1_SHIFT) 114 #define GICH_VMCR_ACK_CTL_SHIFT 2 115 #define GICH_VMCR_ACK_CTL_MASK (1 << GICH_VMCR_ACK_CTL_SHIFT) 116 #define GICH_VMCR_FIQ_EN_SHIFT 3 117 #define GICH_VMCR_FIQ_EN_MASK (1 << GICH_VMCR_FIQ_EN_SHIFT) 118 #define GICH_VMCR_CBPR_SHIFT 4 119 #define GICH_VMCR_CBPR_MASK (1 << GICH_VMCR_CBPR_SHIFT) 120 #define GICH_VMCR_EOI_MODE_SHIFT 9 121 #define GICH_VMCR_EOI_MODE_MASK (1 << GICH_VMCR_EOI_MODE_SHIFT) 122 123 #define GICH_VMCR_PRIMASK_SHIFT 27 124 #define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) 125 #define GICH_VMCR_BINPOINT_SHIFT 21 126 #define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) 127 #define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 128 #define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) 129 130 #define GICH_MISR_EOI (1 << 0) 131 #define GICH_MISR_U (1 << 1) 132 133 #define GICV_PMR_PRIORITY_SHIFT 3 134 #define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT) 135 136 #ifndef __ASSEMBLY__ 137 138 #include <linux/irqdomain.h> 139 140 struct device_node; 141 struct gic_chip_data; 142 143 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); 144 int gic_cpu_if_down(unsigned int gic_nr); 145 void gic_cpu_save(struct gic_chip_data *gic); 146 void gic_cpu_restore(struct gic_chip_data *gic); 147 void gic_dist_save(struct gic_chip_data *gic); 148 void gic_dist_restore(struct gic_chip_data *gic); 149 150 /* 151 * Subdrivers that need some preparatory work can initialize their 152 * chips and call this to register their GICs. 153 */ 154 int gic_of_init(struct device_node *node, struct device_node *parent); 155 156 /* 157 * Initialises and registers a non-root or child GIC chip. Memory for 158 * the gic_chip_data structure is dynamically allocated. 159 */ 160 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq); 161 162 /* 163 * Legacy platforms not converted to DT yet must use this to init 164 * their GIC 165 */ 166 void gic_init(unsigned int nr, int start, 167 void __iomem *dist , void __iomem *cpu); 168 169 int gicv2m_init(struct fwnode_handle *parent_handle, 170 struct irq_domain *parent); 171 172 void gic_send_sgi(unsigned int cpu_id, unsigned int irq); 173 int gic_get_cpu_id(unsigned int cpu); 174 void gic_migrate_target(unsigned int new_cpu_id); 175 unsigned long gic_get_sgir_physaddr(void); 176 177 #endif /* __ASSEMBLY */ 178 #endif 179