1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _LINUX_IRQ_H
3 #define _LINUX_IRQ_H
4
5 /*
6 * Please do not include this file in generic code. There is currently
7 * no requirement for any architecture to implement anything held
8 * within this file.
9 *
10 * Thanks. --rmk
11 */
12
13 #include <linux/cache.h>
14 #include <linux/spinlock.h>
15 #include <linux/cpumask.h>
16 #include <linux/irqhandler.h>
17 #include <linux/irqreturn.h>
18 #include <linux/irqnr.h>
19 #include <linux/topology.h>
20 #include <linux/io.h>
21 #include <linux/slab.h>
22
23 #include <asm/irq.h>
24 #include <asm/ptrace.h>
25 #include <asm/irq_regs.h>
26
27 struct seq_file;
28 struct module;
29 struct msi_msg;
30 enum irqchip_irq_state;
31
32 /*
33 * IRQ line status.
34 *
35 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
36 *
37 * IRQ_TYPE_NONE - default, unspecified type
38 * IRQ_TYPE_EDGE_RISING - rising edge triggered
39 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
40 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
41 * IRQ_TYPE_LEVEL_HIGH - high level triggered
42 * IRQ_TYPE_LEVEL_LOW - low level triggered
43 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
44 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
45 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
46 * to setup the HW to a sane default (used
47 * by irqdomain map() callbacks to synchronize
48 * the HW state and SW flags for a newly
49 * allocated descriptor).
50 *
51 * IRQ_TYPE_PROBE - Special flag for probing in progress
52 *
53 * Bits which can be modified via irq_set/clear/modify_status_flags()
54 * IRQ_LEVEL - Interrupt is level type. Will be also
55 * updated in the code when the above trigger
56 * bits are modified via irq_set_irq_type()
57 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
58 * it from affinity setting
59 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
60 * IRQ_NOREQUEST - Interrupt cannot be requested via
61 * request_irq()
62 * IRQ_NOTHREAD - Interrupt cannot be threaded
63 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
64 * request/setup_irq()
65 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
66 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
67 * IRQ_NESTED_THREAD - Interrupt nests into another thread
68 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
69 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
70 * it from the spurious interrupt detection
71 * mechanism and from core side polling.
72 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
73 */
74 enum {
75 IRQ_TYPE_NONE = 0x00000000,
76 IRQ_TYPE_EDGE_RISING = 0x00000001,
77 IRQ_TYPE_EDGE_FALLING = 0x00000002,
78 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
79 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
80 IRQ_TYPE_LEVEL_LOW = 0x00000008,
81 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
82 IRQ_TYPE_SENSE_MASK = 0x0000000f,
83 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
84
85 IRQ_TYPE_PROBE = 0x00000010,
86
87 IRQ_LEVEL = (1 << 8),
88 IRQ_PER_CPU = (1 << 9),
89 IRQ_NOPROBE = (1 << 10),
90 IRQ_NOREQUEST = (1 << 11),
91 IRQ_NOAUTOEN = (1 << 12),
92 IRQ_NO_BALANCING = (1 << 13),
93 IRQ_MOVE_PCNTXT = (1 << 14),
94 IRQ_NESTED_THREAD = (1 << 15),
95 IRQ_NOTHREAD = (1 << 16),
96 IRQ_PER_CPU_DEVID = (1 << 17),
97 IRQ_IS_POLLED = (1 << 18),
98 IRQ_DISABLE_UNLAZY = (1 << 19),
99 };
100
101 #define IRQF_MODIFY_MASK \
102 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
103 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
104 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
105 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
106
107 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
108
109 /*
110 * Return value for chip->irq_set_affinity()
111 *
112 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
113 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
114 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
115 * support stacked irqchips, which indicates skipping
116 * all descendent irqchips.
117 */
118 enum {
119 IRQ_SET_MASK_OK = 0,
120 IRQ_SET_MASK_OK_NOCOPY,
121 IRQ_SET_MASK_OK_DONE,
122 };
123
124 struct msi_desc;
125 struct irq_domain;
126
127 /**
128 * struct irq_common_data - per irq data shared by all irqchips
129 * @state_use_accessors: status information for irq chip functions.
130 * Use accessor functions to deal with it
131 * @node: node index useful for balancing
132 * @handler_data: per-IRQ data for the irq_chip methods
133 * @affinity: IRQ affinity on SMP. If this is an IPI
134 * related irq, then this is the mask of the
135 * CPUs to which an IPI can be sent.
136 * @effective_affinity: The effective IRQ affinity on SMP as some irq
137 * chips do not allow multi CPU destinations.
138 * A subset of @affinity.
139 * @msi_desc: MSI descriptor
140 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
141 */
142 struct irq_common_data {
143 unsigned int __private state_use_accessors;
144 #ifdef CONFIG_NUMA
145 unsigned int node;
146 #endif
147 void *handler_data;
148 struct msi_desc *msi_desc;
149 cpumask_var_t affinity;
150 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
151 cpumask_var_t effective_affinity;
152 #endif
153 #ifdef CONFIG_GENERIC_IRQ_IPI
154 unsigned int ipi_offset;
155 #endif
156 };
157
158 /**
159 * struct irq_data - per irq chip data passed down to chip functions
160 * @mask: precomputed bitmask for accessing the chip registers
161 * @irq: interrupt number
162 * @hwirq: hardware interrupt number, local to the interrupt domain
163 * @common: point to data shared by all irqchips
164 * @chip: low level interrupt hardware access
165 * @domain: Interrupt translation domain; responsible for mapping
166 * between hwirq number and linux irq number.
167 * @parent_data: pointer to parent struct irq_data to support hierarchy
168 * irq_domain
169 * @chip_data: platform-specific per-chip private data for the chip
170 * methods, to allow shared chip implementations
171 */
172 struct irq_data {
173 u32 mask;
174 unsigned int irq;
175 unsigned long hwirq;
176 struct irq_common_data *common;
177 struct irq_chip *chip;
178 struct irq_domain *domain;
179 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
180 struct irq_data *parent_data;
181 #endif
182 void *chip_data;
183 };
184
185 /*
186 * Bit masks for irq_common_data.state_use_accessors
187 *
188 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
189 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
190 * IRQD_ACTIVATED - Interrupt has already been activated
191 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
192 * IRQD_PER_CPU - Interrupt is per cpu
193 * IRQD_AFFINITY_SET - Interrupt affinity was set
194 * IRQD_LEVEL - Interrupt is level triggered
195 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
196 * from suspend
197 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
198 * context
199 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
200 * IRQD_IRQ_MASKED - Masked state of the interrupt
201 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
202 * IRQD_WAKEUP_ARMED - Wakeup mode armed
203 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
204 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
205 * IRQD_IRQ_STARTED - Startup state of the interrupt
206 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity
207 * mask. Applies only to affinity managed irqs.
208 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target
209 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set
210 * IRQD_CAN_RESERVE - Can use reservation mode
211 * IRQD_MSI_NOMASK_QUIRK - Non-maskable MSI quirk for affinity change
212 * required
213 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call
214 * irq_chip::irq_set_affinity() when deactivated.
215 */
216 enum {
217 IRQD_TRIGGER_MASK = 0xf,
218 IRQD_SETAFFINITY_PENDING = (1 << 8),
219 IRQD_ACTIVATED = (1 << 9),
220 IRQD_NO_BALANCING = (1 << 10),
221 IRQD_PER_CPU = (1 << 11),
222 IRQD_AFFINITY_SET = (1 << 12),
223 IRQD_LEVEL = (1 << 13),
224 IRQD_WAKEUP_STATE = (1 << 14),
225 IRQD_MOVE_PCNTXT = (1 << 15),
226 IRQD_IRQ_DISABLED = (1 << 16),
227 IRQD_IRQ_MASKED = (1 << 17),
228 IRQD_IRQ_INPROGRESS = (1 << 18),
229 IRQD_WAKEUP_ARMED = (1 << 19),
230 IRQD_FORWARDED_TO_VCPU = (1 << 20),
231 IRQD_AFFINITY_MANAGED = (1 << 21),
232 IRQD_IRQ_STARTED = (1 << 22),
233 IRQD_MANAGED_SHUTDOWN = (1 << 23),
234 IRQD_SINGLE_TARGET = (1 << 24),
235 IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
236 IRQD_CAN_RESERVE = (1 << 26),
237 IRQD_MSI_NOMASK_QUIRK = (1 << 27),
238 IRQD_AFFINITY_ON_ACTIVATE = (1 << 29),
239 };
240
241 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
242
irqd_is_setaffinity_pending(struct irq_data * d)243 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
244 {
245 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
246 }
247
irqd_is_per_cpu(struct irq_data * d)248 static inline bool irqd_is_per_cpu(struct irq_data *d)
249 {
250 return __irqd_to_state(d) & IRQD_PER_CPU;
251 }
252
irqd_can_balance(struct irq_data * d)253 static inline bool irqd_can_balance(struct irq_data *d)
254 {
255 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
256 }
257
irqd_affinity_was_set(struct irq_data * d)258 static inline bool irqd_affinity_was_set(struct irq_data *d)
259 {
260 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
261 }
262
irqd_mark_affinity_was_set(struct irq_data * d)263 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
264 {
265 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
266 }
267
irqd_trigger_type_was_set(struct irq_data * d)268 static inline bool irqd_trigger_type_was_set(struct irq_data *d)
269 {
270 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET;
271 }
272
irqd_get_trigger_type(struct irq_data * d)273 static inline u32 irqd_get_trigger_type(struct irq_data *d)
274 {
275 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
276 }
277
278 /*
279 * Must only be called inside irq_chip.irq_set_type() functions or
280 * from the DT/ACPI setup code.
281 */
irqd_set_trigger_type(struct irq_data * d,u32 type)282 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
283 {
284 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
285 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
286 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET;
287 }
288
irqd_is_level_type(struct irq_data * d)289 static inline bool irqd_is_level_type(struct irq_data *d)
290 {
291 return __irqd_to_state(d) & IRQD_LEVEL;
292 }
293
294 /*
295 * Must only be called of irqchip.irq_set_affinity() or low level
296 * hieararchy domain allocation functions.
297 */
irqd_set_single_target(struct irq_data * d)298 static inline void irqd_set_single_target(struct irq_data *d)
299 {
300 __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
301 }
302
irqd_is_single_target(struct irq_data * d)303 static inline bool irqd_is_single_target(struct irq_data *d)
304 {
305 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
306 }
307
irqd_is_wakeup_set(struct irq_data * d)308 static inline bool irqd_is_wakeup_set(struct irq_data *d)
309 {
310 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
311 }
312
irqd_can_move_in_process_context(struct irq_data * d)313 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
314 {
315 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
316 }
317
irqd_irq_disabled(struct irq_data * d)318 static inline bool irqd_irq_disabled(struct irq_data *d)
319 {
320 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
321 }
322
irqd_irq_masked(struct irq_data * d)323 static inline bool irqd_irq_masked(struct irq_data *d)
324 {
325 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
326 }
327
irqd_irq_inprogress(struct irq_data * d)328 static inline bool irqd_irq_inprogress(struct irq_data *d)
329 {
330 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
331 }
332
irqd_is_wakeup_armed(struct irq_data * d)333 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
334 {
335 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
336 }
337
irqd_is_forwarded_to_vcpu(struct irq_data * d)338 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
339 {
340 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
341 }
342
irqd_set_forwarded_to_vcpu(struct irq_data * d)343 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
344 {
345 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
346 }
347
irqd_clr_forwarded_to_vcpu(struct irq_data * d)348 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
349 {
350 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
351 }
352
irqd_affinity_is_managed(struct irq_data * d)353 static inline bool irqd_affinity_is_managed(struct irq_data *d)
354 {
355 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
356 }
357
irqd_is_activated(struct irq_data * d)358 static inline bool irqd_is_activated(struct irq_data *d)
359 {
360 return __irqd_to_state(d) & IRQD_ACTIVATED;
361 }
362
irqd_set_activated(struct irq_data * d)363 static inline void irqd_set_activated(struct irq_data *d)
364 {
365 __irqd_to_state(d) |= IRQD_ACTIVATED;
366 }
367
irqd_clr_activated(struct irq_data * d)368 static inline void irqd_clr_activated(struct irq_data *d)
369 {
370 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
371 }
372
irqd_is_started(struct irq_data * d)373 static inline bool irqd_is_started(struct irq_data *d)
374 {
375 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
376 }
377
irqd_is_managed_and_shutdown(struct irq_data * d)378 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
379 {
380 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
381 }
382
irqd_set_can_reserve(struct irq_data * d)383 static inline void irqd_set_can_reserve(struct irq_data *d)
384 {
385 __irqd_to_state(d) |= IRQD_CAN_RESERVE;
386 }
387
irqd_clr_can_reserve(struct irq_data * d)388 static inline void irqd_clr_can_reserve(struct irq_data *d)
389 {
390 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE;
391 }
392
irqd_can_reserve(struct irq_data * d)393 static inline bool irqd_can_reserve(struct irq_data *d)
394 {
395 return __irqd_to_state(d) & IRQD_CAN_RESERVE;
396 }
397
irqd_set_msi_nomask_quirk(struct irq_data * d)398 static inline void irqd_set_msi_nomask_quirk(struct irq_data *d)
399 {
400 __irqd_to_state(d) |= IRQD_MSI_NOMASK_QUIRK;
401 }
402
irqd_clr_msi_nomask_quirk(struct irq_data * d)403 static inline void irqd_clr_msi_nomask_quirk(struct irq_data *d)
404 {
405 __irqd_to_state(d) &= ~IRQD_MSI_NOMASK_QUIRK;
406 }
407
irqd_msi_nomask_quirk(struct irq_data * d)408 static inline bool irqd_msi_nomask_quirk(struct irq_data *d)
409 {
410 return __irqd_to_state(d) & IRQD_MSI_NOMASK_QUIRK;
411 }
412
irqd_set_affinity_on_activate(struct irq_data * d)413 static inline void irqd_set_affinity_on_activate(struct irq_data *d)
414 {
415 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE;
416 }
417
irqd_affinity_on_activate(struct irq_data * d)418 static inline bool irqd_affinity_on_activate(struct irq_data *d)
419 {
420 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE;
421 }
422
423 #undef __irqd_to_state
424
irqd_to_hwirq(struct irq_data * d)425 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
426 {
427 return d->hwirq;
428 }
429
430 /**
431 * struct irq_chip - hardware interrupt chip descriptor
432 *
433 * @parent_device: pointer to parent device for irqchip
434 * @name: name for /proc/interrupts
435 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
436 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
437 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
438 * @irq_disable: disable the interrupt
439 * @irq_ack: start of a new interrupt
440 * @irq_mask: mask an interrupt source
441 * @irq_mask_ack: ack and mask an interrupt source
442 * @irq_unmask: unmask an interrupt source
443 * @irq_eoi: end of interrupt
444 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force
445 * argument is true, it tells the driver to
446 * unconditionally apply the affinity setting. Sanity
447 * checks against the supplied affinity mask are not
448 * required. This is used for CPU hotplug where the
449 * target CPU is not yet set in the cpu_online_mask.
450 * @irq_retrigger: resend an IRQ to the CPU
451 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
452 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
453 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
454 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
455 * @irq_cpu_online: configure an interrupt source for a secondary CPU
456 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
457 * @irq_suspend: function called from core code on suspend once per
458 * chip, when one or more interrupts are installed
459 * @irq_resume: function called from core code on resume once per chip,
460 * when one ore more interrupts are installed
461 * @irq_pm_shutdown: function called from core code on shutdown once per chip
462 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
463 * @irq_print_chip: optional to print special chip info in show_interrupts
464 * @irq_request_resources: optional to request resources before calling
465 * any other callback related to this irq
466 * @irq_release_resources: optional to release resources acquired with
467 * irq_request_resources
468 * @irq_compose_msi_msg: optional to compose message content for MSI
469 * @irq_write_msi_msg: optional to write message content for MSI
470 * @irq_get_irqchip_state: return the internal state of an interrupt
471 * @irq_set_irqchip_state: set the internal state of a interrupt
472 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
473 * @ipi_send_single: send a single IPI to destination cpus
474 * @ipi_send_mask: send an IPI to destination cpus in cpumask
475 * @flags: chip specific flags
476 */
477 struct irq_chip {
478 struct device *parent_device;
479 const char *name;
480 unsigned int (*irq_startup)(struct irq_data *data);
481 void (*irq_shutdown)(struct irq_data *data);
482 void (*irq_enable)(struct irq_data *data);
483 void (*irq_disable)(struct irq_data *data);
484
485 void (*irq_ack)(struct irq_data *data);
486 void (*irq_mask)(struct irq_data *data);
487 void (*irq_mask_ack)(struct irq_data *data);
488 void (*irq_unmask)(struct irq_data *data);
489 void (*irq_eoi)(struct irq_data *data);
490
491 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
492 int (*irq_retrigger)(struct irq_data *data);
493 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
494 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
495
496 void (*irq_bus_lock)(struct irq_data *data);
497 void (*irq_bus_sync_unlock)(struct irq_data *data);
498
499 void (*irq_cpu_online)(struct irq_data *data);
500 void (*irq_cpu_offline)(struct irq_data *data);
501
502 void (*irq_suspend)(struct irq_data *data);
503 void (*irq_resume)(struct irq_data *data);
504 void (*irq_pm_shutdown)(struct irq_data *data);
505
506 void (*irq_calc_mask)(struct irq_data *data);
507
508 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
509 int (*irq_request_resources)(struct irq_data *data);
510 void (*irq_release_resources)(struct irq_data *data);
511
512 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
513 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
514
515 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
516 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
517
518 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
519
520 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
521 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
522
523 unsigned long flags;
524 };
525
526 /*
527 * irq_chip specific flags
528 *
529 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
530 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
531 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
532 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
533 * when irq enabled
534 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
535 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
536 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
537 * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs
538 * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup
539 */
540 enum {
541 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
542 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
543 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
544 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
545 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
546 IRQCHIP_ONESHOT_SAFE = (1 << 5),
547 IRQCHIP_EOI_THREADED = (1 << 6),
548 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
549 IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10),
550 };
551
552 #include <linux/irqdesc.h>
553
554 /*
555 * Pick up the arch-dependent methods:
556 */
557 #include <asm/hw_irq.h>
558
559 #ifndef NR_IRQS_LEGACY
560 # define NR_IRQS_LEGACY 0
561 #endif
562
563 #ifndef ARCH_IRQ_INIT_FLAGS
564 # define ARCH_IRQ_INIT_FLAGS 0
565 #endif
566
567 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
568
569 struct irqaction;
570 extern int setup_irq(unsigned int irq, struct irqaction *new);
571 extern void remove_irq(unsigned int irq, struct irqaction *act);
572 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
573 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
574
575 extern void irq_cpu_online(void);
576 extern void irq_cpu_offline(void);
577 extern int irq_set_affinity_locked(struct irq_data *data,
578 const struct cpumask *cpumask, bool force);
579 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
580
581 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
582 extern void irq_migrate_all_off_this_cpu(void);
583 extern int irq_affinity_online_cpu(unsigned int cpu);
584 #else
585 # define irq_affinity_online_cpu NULL
586 #endif
587
588 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
589 void __irq_move_irq(struct irq_data *data);
irq_move_irq(struct irq_data * data)590 static inline void irq_move_irq(struct irq_data *data)
591 {
592 if (unlikely(irqd_is_setaffinity_pending(data)))
593 __irq_move_irq(data);
594 }
595 void irq_move_masked_irq(struct irq_data *data);
596 void irq_force_complete_move(struct irq_desc *desc);
597 #else
irq_move_irq(struct irq_data * data)598 static inline void irq_move_irq(struct irq_data *data) { }
irq_move_masked_irq(struct irq_data * data)599 static inline void irq_move_masked_irq(struct irq_data *data) { }
irq_force_complete_move(struct irq_desc * desc)600 static inline void irq_force_complete_move(struct irq_desc *desc) { }
601 #endif
602
603 extern int no_irq_affinity;
604
605 #ifdef CONFIG_HARDIRQS_SW_RESEND
606 int irq_set_parent(int irq, int parent_irq);
607 #else
irq_set_parent(int irq,int parent_irq)608 static inline int irq_set_parent(int irq, int parent_irq)
609 {
610 return 0;
611 }
612 #endif
613
614 /*
615 * Built-in IRQ handlers for various IRQ types,
616 * callable via desc->handle_irq()
617 */
618 extern void handle_level_irq(struct irq_desc *desc);
619 extern void handle_fasteoi_irq(struct irq_desc *desc);
620 extern void handle_edge_irq(struct irq_desc *desc);
621 extern void handle_edge_eoi_irq(struct irq_desc *desc);
622 extern void handle_simple_irq(struct irq_desc *desc);
623 extern void handle_untracked_irq(struct irq_desc *desc);
624 extern void handle_percpu_irq(struct irq_desc *desc);
625 extern void handle_percpu_devid_irq(struct irq_desc *desc);
626 extern void handle_bad_irq(struct irq_desc *desc);
627 extern void handle_nested_irq(unsigned int irq);
628
629 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
630 extern int irq_chip_pm_get(struct irq_data *data);
631 extern int irq_chip_pm_put(struct irq_data *data);
632 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
633 extern void handle_fasteoi_ack_irq(struct irq_desc *desc);
634 extern void handle_fasteoi_mask_irq(struct irq_desc *desc);
635 extern void irq_chip_enable_parent(struct irq_data *data);
636 extern void irq_chip_disable_parent(struct irq_data *data);
637 extern void irq_chip_ack_parent(struct irq_data *data);
638 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
639 extern void irq_chip_mask_parent(struct irq_data *data);
640 extern void irq_chip_unmask_parent(struct irq_data *data);
641 extern void irq_chip_eoi_parent(struct irq_data *data);
642 extern int irq_chip_set_affinity_parent(struct irq_data *data,
643 const struct cpumask *dest,
644 bool force);
645 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
646 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
647 void *vcpu_info);
648 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
649 #endif
650
651 /* Handling of unhandled and spurious interrupts: */
652 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
653
654
655 /* Enable/disable irq debugging output: */
656 extern int noirqdebug_setup(char *str);
657
658 /* Checks whether the interrupt can be requested by request_irq(): */
659 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
660
661 /* Dummy irq-chip implementations: */
662 extern struct irq_chip no_irq_chip;
663 extern struct irq_chip dummy_irq_chip;
664
665 extern void
666 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
667 irq_flow_handler_t handle, const char *name);
668
irq_set_chip_and_handler(unsigned int irq,struct irq_chip * chip,irq_flow_handler_t handle)669 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
670 irq_flow_handler_t handle)
671 {
672 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
673 }
674
675 extern int irq_set_percpu_devid(unsigned int irq);
676 extern int irq_set_percpu_devid_partition(unsigned int irq,
677 const struct cpumask *affinity);
678 extern int irq_get_percpu_devid_partition(unsigned int irq,
679 struct cpumask *affinity);
680
681 extern void
682 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
683 const char *name);
684
685 static inline void
irq_set_handler(unsigned int irq,irq_flow_handler_t handle)686 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
687 {
688 __irq_set_handler(irq, handle, 0, NULL);
689 }
690
691 /*
692 * Set a highlevel chained flow handler for a given IRQ.
693 * (a chained handler is automatically enabled and set to
694 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
695 */
696 static inline void
irq_set_chained_handler(unsigned int irq,irq_flow_handler_t handle)697 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
698 {
699 __irq_set_handler(irq, handle, 1, NULL);
700 }
701
702 /*
703 * Set a highlevel chained flow handler and its data for a given IRQ.
704 * (a chained handler is automatically enabled and set to
705 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
706 */
707 void
708 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
709 void *data);
710
711 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
712
irq_set_status_flags(unsigned int irq,unsigned long set)713 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
714 {
715 irq_modify_status(irq, 0, set);
716 }
717
irq_clear_status_flags(unsigned int irq,unsigned long clr)718 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
719 {
720 irq_modify_status(irq, clr, 0);
721 }
722
irq_set_noprobe(unsigned int irq)723 static inline void irq_set_noprobe(unsigned int irq)
724 {
725 irq_modify_status(irq, 0, IRQ_NOPROBE);
726 }
727
irq_set_probe(unsigned int irq)728 static inline void irq_set_probe(unsigned int irq)
729 {
730 irq_modify_status(irq, IRQ_NOPROBE, 0);
731 }
732
irq_set_nothread(unsigned int irq)733 static inline void irq_set_nothread(unsigned int irq)
734 {
735 irq_modify_status(irq, 0, IRQ_NOTHREAD);
736 }
737
irq_set_thread(unsigned int irq)738 static inline void irq_set_thread(unsigned int irq)
739 {
740 irq_modify_status(irq, IRQ_NOTHREAD, 0);
741 }
742
irq_set_nested_thread(unsigned int irq,bool nest)743 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
744 {
745 if (nest)
746 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
747 else
748 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
749 }
750
irq_set_percpu_devid_flags(unsigned int irq)751 static inline void irq_set_percpu_devid_flags(unsigned int irq)
752 {
753 irq_set_status_flags(irq,
754 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
755 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
756 }
757
758 /* Set/get chip/data for an IRQ: */
759 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
760 extern int irq_set_handler_data(unsigned int irq, void *data);
761 extern int irq_set_chip_data(unsigned int irq, void *data);
762 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
763 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
764 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
765 struct msi_desc *entry);
766 extern struct irq_data *irq_get_irq_data(unsigned int irq);
767
irq_get_chip(unsigned int irq)768 static inline struct irq_chip *irq_get_chip(unsigned int irq)
769 {
770 struct irq_data *d = irq_get_irq_data(irq);
771 return d ? d->chip : NULL;
772 }
773
irq_data_get_irq_chip(struct irq_data * d)774 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
775 {
776 return d->chip;
777 }
778
irq_get_chip_data(unsigned int irq)779 static inline void *irq_get_chip_data(unsigned int irq)
780 {
781 struct irq_data *d = irq_get_irq_data(irq);
782 return d ? d->chip_data : NULL;
783 }
784
irq_data_get_irq_chip_data(struct irq_data * d)785 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
786 {
787 return d->chip_data;
788 }
789
irq_get_handler_data(unsigned int irq)790 static inline void *irq_get_handler_data(unsigned int irq)
791 {
792 struct irq_data *d = irq_get_irq_data(irq);
793 return d ? d->common->handler_data : NULL;
794 }
795
irq_data_get_irq_handler_data(struct irq_data * d)796 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
797 {
798 return d->common->handler_data;
799 }
800
irq_get_msi_desc(unsigned int irq)801 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
802 {
803 struct irq_data *d = irq_get_irq_data(irq);
804 return d ? d->common->msi_desc : NULL;
805 }
806
irq_data_get_msi_desc(struct irq_data * d)807 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
808 {
809 return d->common->msi_desc;
810 }
811
irq_get_trigger_type(unsigned int irq)812 static inline u32 irq_get_trigger_type(unsigned int irq)
813 {
814 struct irq_data *d = irq_get_irq_data(irq);
815 return d ? irqd_get_trigger_type(d) : 0;
816 }
817
irq_common_data_get_node(struct irq_common_data * d)818 static inline int irq_common_data_get_node(struct irq_common_data *d)
819 {
820 #ifdef CONFIG_NUMA
821 return d->node;
822 #else
823 return 0;
824 #endif
825 }
826
irq_data_get_node(struct irq_data * d)827 static inline int irq_data_get_node(struct irq_data *d)
828 {
829 return irq_common_data_get_node(d->common);
830 }
831
irq_get_affinity_mask(int irq)832 static inline struct cpumask *irq_get_affinity_mask(int irq)
833 {
834 struct irq_data *d = irq_get_irq_data(irq);
835
836 return d ? d->common->affinity : NULL;
837 }
838
irq_data_get_affinity_mask(struct irq_data * d)839 static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
840 {
841 return d->common->affinity;
842 }
843
844 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
845 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)846 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
847 {
848 return d->common->effective_affinity;
849 }
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)850 static inline void irq_data_update_effective_affinity(struct irq_data *d,
851 const struct cpumask *m)
852 {
853 cpumask_copy(d->common->effective_affinity, m);
854 }
855 #else
irq_data_update_effective_affinity(struct irq_data * d,const struct cpumask * m)856 static inline void irq_data_update_effective_affinity(struct irq_data *d,
857 const struct cpumask *m)
858 {
859 }
860 static inline
irq_data_get_effective_affinity_mask(struct irq_data * d)861 struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
862 {
863 return d->common->affinity;
864 }
865 #endif
866
867 unsigned int arch_dynirq_lower_bound(unsigned int from);
868
869 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
870 struct module *owner, const struct cpumask *affinity);
871
872 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
873 unsigned int cnt, int node, struct module *owner,
874 const struct cpumask *affinity);
875
876 /* use macros to avoid needing export.h for THIS_MODULE */
877 #define irq_alloc_descs(irq, from, cnt, node) \
878 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
879
880 #define irq_alloc_desc(node) \
881 irq_alloc_descs(-1, 0, 1, node)
882
883 #define irq_alloc_desc_at(at, node) \
884 irq_alloc_descs(at, at, 1, node)
885
886 #define irq_alloc_desc_from(from, node) \
887 irq_alloc_descs(-1, from, 1, node)
888
889 #define irq_alloc_descs_from(from, cnt, node) \
890 irq_alloc_descs(-1, from, cnt, node)
891
892 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
893 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
894
895 #define devm_irq_alloc_desc(dev, node) \
896 devm_irq_alloc_descs(dev, -1, 0, 1, node)
897
898 #define devm_irq_alloc_desc_at(dev, at, node) \
899 devm_irq_alloc_descs(dev, at, at, 1, node)
900
901 #define devm_irq_alloc_desc_from(dev, from, node) \
902 devm_irq_alloc_descs(dev, -1, from, 1, node)
903
904 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \
905 devm_irq_alloc_descs(dev, -1, from, cnt, node)
906
907 void irq_free_descs(unsigned int irq, unsigned int cnt);
irq_free_desc(unsigned int irq)908 static inline void irq_free_desc(unsigned int irq)
909 {
910 irq_free_descs(irq, 1);
911 }
912
913 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
914 unsigned int irq_alloc_hwirqs(int cnt, int node);
irq_alloc_hwirq(int node)915 static inline unsigned int irq_alloc_hwirq(int node)
916 {
917 return irq_alloc_hwirqs(1, node);
918 }
919 void irq_free_hwirqs(unsigned int from, int cnt);
irq_free_hwirq(unsigned int irq)920 static inline void irq_free_hwirq(unsigned int irq)
921 {
922 return irq_free_hwirqs(irq, 1);
923 }
924 int arch_setup_hwirq(unsigned int irq, int node);
925 void arch_teardown_hwirq(unsigned int irq);
926 #endif
927
928 #ifdef CONFIG_GENERIC_IRQ_LEGACY
929 void irq_init_desc(unsigned int irq);
930 #endif
931
932 /**
933 * struct irq_chip_regs - register offsets for struct irq_gci
934 * @enable: Enable register offset to reg_base
935 * @disable: Disable register offset to reg_base
936 * @mask: Mask register offset to reg_base
937 * @ack: Ack register offset to reg_base
938 * @eoi: Eoi register offset to reg_base
939 * @type: Type configuration register offset to reg_base
940 * @polarity: Polarity configuration register offset to reg_base
941 */
942 struct irq_chip_regs {
943 unsigned long enable;
944 unsigned long disable;
945 unsigned long mask;
946 unsigned long ack;
947 unsigned long eoi;
948 unsigned long type;
949 unsigned long polarity;
950 };
951
952 /**
953 * struct irq_chip_type - Generic interrupt chip instance for a flow type
954 * @chip: The real interrupt chip which provides the callbacks
955 * @regs: Register offsets for this chip
956 * @handler: Flow handler associated with this chip
957 * @type: Chip can handle these flow types
958 * @mask_cache_priv: Cached mask register private to the chip type
959 * @mask_cache: Pointer to cached mask register
960 *
961 * A irq_generic_chip can have several instances of irq_chip_type when
962 * it requires different functions and register offsets for different
963 * flow types.
964 */
965 struct irq_chip_type {
966 struct irq_chip chip;
967 struct irq_chip_regs regs;
968 irq_flow_handler_t handler;
969 u32 type;
970 u32 mask_cache_priv;
971 u32 *mask_cache;
972 };
973
974 /**
975 * struct irq_chip_generic - Generic irq chip data structure
976 * @lock: Lock to protect register and cache data access
977 * @reg_base: Register base address (virtual)
978 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
979 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
980 * @suspend: Function called from core code on suspend once per
981 * chip; can be useful instead of irq_chip::suspend to
982 * handle chip details even when no interrupts are in use
983 * @resume: Function called from core code on resume once per chip;
984 * can be useful instead of irq_chip::suspend to handle
985 * chip details even when no interrupts are in use
986 * @irq_base: Interrupt base nr for this chip
987 * @irq_cnt: Number of interrupts handled by this chip
988 * @mask_cache: Cached mask register shared between all chip types
989 * @type_cache: Cached type register
990 * @polarity_cache: Cached polarity register
991 * @wake_enabled: Interrupt can wakeup from suspend
992 * @wake_active: Interrupt is marked as an wakeup from suspend source
993 * @num_ct: Number of available irq_chip_type instances (usually 1)
994 * @private: Private data for non generic chip callbacks
995 * @installed: bitfield to denote installed interrupts
996 * @unused: bitfield to denote unused interrupts
997 * @domain: irq domain pointer
998 * @list: List head for keeping track of instances
999 * @chip_types: Array of interrupt irq_chip_types
1000 *
1001 * Note, that irq_chip_generic can have multiple irq_chip_type
1002 * implementations which can be associated to a particular irq line of
1003 * an irq_chip_generic instance. That allows to share and protect
1004 * state in an irq_chip_generic instance when we need to implement
1005 * different flow mechanisms (level/edge) for it.
1006 */
1007 struct irq_chip_generic {
1008 raw_spinlock_t lock;
1009 void __iomem *reg_base;
1010 u32 (*reg_readl)(void __iomem *addr);
1011 void (*reg_writel)(u32 val, void __iomem *addr);
1012 void (*suspend)(struct irq_chip_generic *gc);
1013 void (*resume)(struct irq_chip_generic *gc);
1014 unsigned int irq_base;
1015 unsigned int irq_cnt;
1016 u32 mask_cache;
1017 u32 type_cache;
1018 u32 polarity_cache;
1019 u32 wake_enabled;
1020 u32 wake_active;
1021 unsigned int num_ct;
1022 void *private;
1023 unsigned long installed;
1024 unsigned long unused;
1025 struct irq_domain *domain;
1026 struct list_head list;
1027 struct irq_chip_type chip_types[0];
1028 };
1029
1030 /**
1031 * enum irq_gc_flags - Initialization flags for generic irq chips
1032 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
1033 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
1034 * irq chips which need to call irq_set_wake() on
1035 * the parent irq. Usually GPIO implementations
1036 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
1037 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
1038 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
1039 */
1040 enum irq_gc_flags {
1041 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
1042 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
1043 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
1044 IRQ_GC_NO_MASK = 1 << 3,
1045 IRQ_GC_BE_IO = 1 << 4,
1046 };
1047
1048 /*
1049 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
1050 * @irqs_per_chip: Number of interrupts per chip
1051 * @num_chips: Number of chips
1052 * @irq_flags_to_set: IRQ* flags to set on irq setup
1053 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
1054 * @gc_flags: Generic chip specific setup flags
1055 * @gc: Array of pointers to generic interrupt chips
1056 */
1057 struct irq_domain_chip_generic {
1058 unsigned int irqs_per_chip;
1059 unsigned int num_chips;
1060 unsigned int irq_flags_to_clear;
1061 unsigned int irq_flags_to_set;
1062 enum irq_gc_flags gc_flags;
1063 struct irq_chip_generic *gc[0];
1064 };
1065
1066 /* Generic chip callback functions */
1067 void irq_gc_noop(struct irq_data *d);
1068 void irq_gc_mask_disable_reg(struct irq_data *d);
1069 void irq_gc_mask_set_bit(struct irq_data *d);
1070 void irq_gc_mask_clr_bit(struct irq_data *d);
1071 void irq_gc_unmask_enable_reg(struct irq_data *d);
1072 void irq_gc_ack_set_bit(struct irq_data *d);
1073 void irq_gc_ack_clr_bit(struct irq_data *d);
1074 void irq_gc_mask_disable_and_ack_set(struct irq_data *d);
1075 void irq_gc_eoi(struct irq_data *d);
1076 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1077
1078 /* Setup functions for irq_chip_generic */
1079 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1080 irq_hw_number_t hw_irq);
1081 struct irq_chip_generic *
1082 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1083 void __iomem *reg_base, irq_flow_handler_t handler);
1084 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1085 enum irq_gc_flags flags, unsigned int clr,
1086 unsigned int set);
1087 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1088 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1089 unsigned int clr, unsigned int set);
1090
1091 struct irq_chip_generic *
1092 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1093 unsigned int irq_base, void __iomem *reg_base,
1094 irq_flow_handler_t handler);
1095 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1096 u32 msk, enum irq_gc_flags flags,
1097 unsigned int clr, unsigned int set);
1098
1099 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1100
1101 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1102 int num_ct, const char *name,
1103 irq_flow_handler_t handler,
1104 unsigned int clr, unsigned int set,
1105 enum irq_gc_flags flags);
1106
1107 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1108 handler, clr, set, flags) \
1109 ({ \
1110 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1111 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1112 handler, clr, set, flags); \
1113 })
1114
irq_free_generic_chip(struct irq_chip_generic * gc)1115 static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1116 {
1117 kfree(gc);
1118 }
1119
irq_destroy_generic_chip(struct irq_chip_generic * gc,u32 msk,unsigned int clr,unsigned int set)1120 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1121 u32 msk, unsigned int clr,
1122 unsigned int set)
1123 {
1124 irq_remove_generic_chip(gc, msk, clr, set);
1125 irq_free_generic_chip(gc);
1126 }
1127
irq_data_get_chip_type(struct irq_data * d)1128 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1129 {
1130 return container_of(d->chip, struct irq_chip_type, chip);
1131 }
1132
1133 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1134
1135 #ifdef CONFIG_SMP
irq_gc_lock(struct irq_chip_generic * gc)1136 static inline void irq_gc_lock(struct irq_chip_generic *gc)
1137 {
1138 raw_spin_lock(&gc->lock);
1139 }
1140
irq_gc_unlock(struct irq_chip_generic * gc)1141 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1142 {
1143 raw_spin_unlock(&gc->lock);
1144 }
1145 #else
irq_gc_lock(struct irq_chip_generic * gc)1146 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
irq_gc_unlock(struct irq_chip_generic * gc)1147 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1148 #endif
1149
1150 /*
1151 * The irqsave variants are for usage in non interrupt code. Do not use
1152 * them in irq_chip callbacks. Use irq_gc_lock() instead.
1153 */
1154 #define irq_gc_lock_irqsave(gc, flags) \
1155 raw_spin_lock_irqsave(&(gc)->lock, flags)
1156
1157 #define irq_gc_unlock_irqrestore(gc, flags) \
1158 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1159
irq_reg_writel(struct irq_chip_generic * gc,u32 val,int reg_offset)1160 static inline void irq_reg_writel(struct irq_chip_generic *gc,
1161 u32 val, int reg_offset)
1162 {
1163 if (gc->reg_writel)
1164 gc->reg_writel(val, gc->reg_base + reg_offset);
1165 else
1166 writel(val, gc->reg_base + reg_offset);
1167 }
1168
irq_reg_readl(struct irq_chip_generic * gc,int reg_offset)1169 static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1170 int reg_offset)
1171 {
1172 if (gc->reg_readl)
1173 return gc->reg_readl(gc->reg_base + reg_offset);
1174 else
1175 return readl(gc->reg_base + reg_offset);
1176 }
1177
1178 struct irq_matrix;
1179 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits,
1180 unsigned int alloc_start,
1181 unsigned int alloc_end);
1182 void irq_matrix_online(struct irq_matrix *m);
1183 void irq_matrix_offline(struct irq_matrix *m);
1184 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace);
1185 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk);
1186 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk);
1187 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk,
1188 unsigned int *mapped_cpu);
1189 void irq_matrix_reserve(struct irq_matrix *m);
1190 void irq_matrix_remove_reserved(struct irq_matrix *m);
1191 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk,
1192 bool reserved, unsigned int *mapped_cpu);
1193 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu,
1194 unsigned int bit, bool managed);
1195 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit);
1196 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown);
1197 unsigned int irq_matrix_allocated(struct irq_matrix *m);
1198 unsigned int irq_matrix_reserved(struct irq_matrix *m);
1199 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind);
1200
1201 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
1202 #define INVALID_HWIRQ (~0UL)
1203 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1204 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1205 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1206 int ipi_send_single(unsigned int virq, unsigned int cpu);
1207 int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1208
1209 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1210 /*
1211 * Registers a generic IRQ handling function as the top-level IRQ handler in
1212 * the system, which is generally the first C code called from an assembly
1213 * architecture-specific interrupt handler.
1214 *
1215 * Returns 0 on success, or -EBUSY if an IRQ handler has already been
1216 * registered.
1217 */
1218 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *));
1219
1220 /*
1221 * Allows interrupt handlers to find the irqchip that's been registered as the
1222 * top-level IRQ handler.
1223 */
1224 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init;
1225 #endif
1226
1227 #endif /* _LINUX_IRQ_H */
1228