1 /****************************************************************************** 2 * Intel Management Engine Interface (Intel MEI) Linux driver 3 * Intel MEI Interface Header 4 * 5 * This file is provided under a dual BSD/GPLv2 license. When using or 6 * redistributing this file, you may do so under either license. 7 * 8 * GPL LICENSE SUMMARY 9 * 10 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called LICENSE.GPL. 28 * 29 * Contact Information: 30 * Intel Corporation. 31 * linux-mei@linux.intel.com 32 * http://www.intel.com 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 43 * * Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * * Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in 47 * the documentation and/or other materials provided with the 48 * distribution. 49 * * Neither the name Intel Corporation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 * 65 *****************************************************************************/ 66 #ifndef _MEI_HW_MEI_REGS_H_ 67 #define _MEI_HW_MEI_REGS_H_ 68 69 /* 70 * MEI device IDs 71 */ 72 #define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */ 73 #define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */ 74 #define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */ 75 #define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */ 76 77 #define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */ 78 #define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */ 79 80 #define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */ 81 #define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */ 82 #define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */ 83 #define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */ 84 #define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */ 85 86 #define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */ 87 #define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */ 88 #define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */ 89 #define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */ 90 #define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */ 91 92 #define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */ 93 #define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */ 94 #define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */ 95 #define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */ 96 97 #define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */ 98 #define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */ 99 #define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */ 100 #define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */ 101 102 #define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */ 103 #define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */ 104 105 #define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */ 106 #define MEI_DEV_ID_PBG_1 0x1D3A /* C600/X79 Patsburg */ 107 108 #define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */ 109 #define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */ 110 #define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */ 111 112 #define MEI_DEV_ID_LPT_H 0x8C3A /* Lynx Point H */ 113 #define MEI_DEV_ID_LPT_W 0x8D3A /* Lynx Point - Wellsburg */ 114 #define MEI_DEV_ID_LPT_LP 0x9C3A /* Lynx Point LP */ 115 #define MEI_DEV_ID_LPT_HR 0x8CBA /* Lynx Point H Refresh */ 116 117 #define MEI_DEV_ID_WPT_LP 0x9CBA /* Wildcat Point LP */ 118 #define MEI_DEV_ID_WPT_LP_2 0x9CBB /* Wildcat Point LP 2 */ 119 120 #define MEI_DEV_ID_SPT 0x9D3A /* Sunrise Point */ 121 #define MEI_DEV_ID_SPT_2 0x9D3B /* Sunrise Point 2 */ 122 #define MEI_DEV_ID_SPT_H 0xA13A /* Sunrise Point H */ 123 #define MEI_DEV_ID_SPT_H_2 0xA13B /* Sunrise Point H 2 */ 124 125 #define MEI_DEV_ID_LBG 0xA1BA /* Lewisburg (SPT) */ 126 127 #define MEI_DEV_ID_BXT_M 0x1A9A /* Broxton M */ 128 #define MEI_DEV_ID_APL_I 0x5A9A /* Apollo Lake I */ 129 130 #define MEI_DEV_ID_DNV_IE 0x19E5 /* Denverton IE */ 131 132 #define MEI_DEV_ID_GLK 0x319A /* Gemini Lake */ 133 134 #define MEI_DEV_ID_KBP 0xA2BA /* Kaby Point */ 135 #define MEI_DEV_ID_KBP_2 0xA2BB /* Kaby Point 2 */ 136 137 #define MEI_DEV_ID_CNP_LP 0x9DE0 /* Cannon Point LP */ 138 #define MEI_DEV_ID_CNP_LP_4 0x9DE4 /* Cannon Point LP 4 (iTouch) */ 139 #define MEI_DEV_ID_CNP_H 0xA360 /* Cannon Point H */ 140 #define MEI_DEV_ID_CNP_H_4 0xA364 /* Cannon Point H 4 (iTouch) */ 141 142 #define MEI_DEV_ID_CMP_LP 0x02e0 /* Comet Point LP */ 143 #define MEI_DEV_ID_CMP_LP_3 0x02e4 /* Comet Point LP 3 (iTouch) */ 144 145 #define MEI_DEV_ID_CMP_V 0xA3BA /* Comet Point Lake V */ 146 147 #define MEI_DEV_ID_CMP_H 0x06e0 /* Comet Lake H */ 148 #define MEI_DEV_ID_CMP_H_3 0x06e4 /* Comet Lake H 3 (iTouch) */ 149 150 #define MEI_DEV_ID_CDF 0x18D3 /* Cedar Fork */ 151 152 #define MEI_DEV_ID_ICP_LP 0x34E0 /* Ice Lake Point LP */ 153 #define MEI_DEV_ID_ICP_N 0x38E0 /* Ice Lake Point N */ 154 155 #define MEI_DEV_ID_TGP_LP 0xA0E0 /* Tiger Lake Point LP */ 156 157 #define MEI_DEV_ID_MCC 0x4B70 /* Mule Creek Canyon (EHL) */ 158 #define MEI_DEV_ID_MCC_4 0x4B75 /* Mule Creek Canyon 4 (EHL) */ 159 160 /* 161 * MEI HW Section 162 */ 163 164 /* Host Firmware Status Registers in PCI Config Space */ 165 #define PCI_CFG_HFS_1 0x40 166 # define PCI_CFG_HFS_1_D0I3_MSK 0x80000000 167 #define PCI_CFG_HFS_2 0x48 168 #define PCI_CFG_HFS_3 0x60 169 #define PCI_CFG_HFS_4 0x64 170 #define PCI_CFG_HFS_5 0x68 171 #define PCI_CFG_HFS_6 0x6C 172 173 /* MEI registers */ 174 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */ 175 #define H_CB_WW 0 176 /* H_CSR - Host Control Status register */ 177 #define H_CSR 4 178 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */ 179 #define ME_CB_RW 8 180 /* ME_CSR_HA - ME Control Status Host Access register (read only) */ 181 #define ME_CSR_HA 0xC 182 /* H_HGC_CSR - PGI register */ 183 #define H_HPG_CSR 0x10 184 /* H_D0I3C - D0I3 Control */ 185 #define H_D0I3C 0x800 186 187 /* register bits of H_CSR (Host Control Status register) */ 188 /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */ 189 #define H_CBD 0xFF000000 190 /* Host Circular Buffer Write Pointer */ 191 #define H_CBWP 0x00FF0000 192 /* Host Circular Buffer Read Pointer */ 193 #define H_CBRP 0x0000FF00 194 /* Host Reset */ 195 #define H_RST 0x00000010 196 /* Host Ready */ 197 #define H_RDY 0x00000008 198 /* Host Interrupt Generate */ 199 #define H_IG 0x00000004 200 /* Host Interrupt Status */ 201 #define H_IS 0x00000002 202 /* Host Interrupt Enable */ 203 #define H_IE 0x00000001 204 /* Host D0I3 Interrupt Enable */ 205 #define H_D0I3C_IE 0x00000020 206 /* Host D0I3 Interrupt Status */ 207 #define H_D0I3C_IS 0x00000040 208 209 /* H_CSR masks */ 210 #define H_CSR_IE_MASK (H_IE | H_D0I3C_IE) 211 #define H_CSR_IS_MASK (H_IS | H_D0I3C_IS) 212 213 /* register bits of ME_CSR_HA (ME Control Status Host Access register) */ 214 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only 215 access to ME_CBD */ 216 #define ME_CBD_HRA 0xFF000000 217 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */ 218 #define ME_CBWP_HRA 0x00FF0000 219 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */ 220 #define ME_CBRP_HRA 0x0000FF00 221 /* ME Power Gate Isolation Capability HRA - host ready only access */ 222 #define ME_PGIC_HRA 0x00000040 223 /* ME Reset HRA - host read only access to ME_RST */ 224 #define ME_RST_HRA 0x00000010 225 /* ME Ready HRA - host read only access to ME_RDY */ 226 #define ME_RDY_HRA 0x00000008 227 /* ME Interrupt Generate HRA - host read only access to ME_IG */ 228 #define ME_IG_HRA 0x00000004 229 /* ME Interrupt Status HRA - host read only access to ME_IS */ 230 #define ME_IS_HRA 0x00000002 231 /* ME Interrupt Enable HRA - host read only access to ME_IE */ 232 #define ME_IE_HRA 0x00000001 233 234 235 /* H_HPG_CSR register bits */ 236 #define H_HPG_CSR_PGIHEXR 0x00000001 237 #define H_HPG_CSR_PGI 0x00000002 238 239 /* H_D0I3C register bits */ 240 #define H_D0I3C_CIP 0x00000001 241 #define H_D0I3C_IR 0x00000002 242 #define H_D0I3C_I3 0x00000004 243 #define H_D0I3C_RR 0x00000008 244 245 #endif /* _MEI_HW_MEI_REGS_H_ */ 246