1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Rahul Sharma <rahul.sharma@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Common Clock Framework support for Exynos5260 SoC. 10 */ 11 12 #ifndef __CLK_EXYNOS5260_H 13 #define __CLK_EXYNOS5260_H 14 15 /* 16 *Registers for CMU_AUD 17 */ 18 #define MUX_SEL_AUD 0x0200 19 #define MUX_ENABLE_AUD 0x0300 20 #define MUX_STAT_AUD 0x0400 21 #define MUX_IGNORE_AUD 0x0500 22 #define DIV_AUD0 0x0600 23 #define DIV_AUD1 0x0604 24 #define DIV_STAT_AUD0 0x0700 25 #define DIV_STAT_AUD1 0x0704 26 #define EN_ACLK_AUD 0x0800 27 #define EN_PCLK_AUD 0x0900 28 #define EN_SCLK_AUD 0x0a00 29 #define EN_IP_AUD 0x0b00 30 31 /* 32 *Registers for CMU_DISP 33 */ 34 #define MUX_SEL_DISP0 0x0200 35 #define MUX_SEL_DISP1 0x0204 36 #define MUX_SEL_DISP2 0x0208 37 #define MUX_SEL_DISP3 0x020C 38 #define MUX_SEL_DISP4 0x0210 39 #define MUX_ENABLE_DISP0 0x0300 40 #define MUX_ENABLE_DISP1 0x0304 41 #define MUX_ENABLE_DISP2 0x0308 42 #define MUX_ENABLE_DISP3 0x030c 43 #define MUX_ENABLE_DISP4 0x0310 44 #define MUX_STAT_DISP0 0x0400 45 #define MUX_STAT_DISP1 0x0404 46 #define MUX_STAT_DISP2 0x0408 47 #define MUX_STAT_DISP3 0x040c 48 #define MUX_STAT_DISP4 0x0410 49 #define MUX_IGNORE_DISP0 0x0500 50 #define MUX_IGNORE_DISP1 0x0504 51 #define MUX_IGNORE_DISP2 0x0508 52 #define MUX_IGNORE_DISP3 0x050c 53 #define MUX_IGNORE_DISP4 0x0510 54 #define DIV_DISP 0x0600 55 #define DIV_STAT_DISP 0x0700 56 #define EN_ACLK_DISP 0x0800 57 #define EN_PCLK_DISP 0x0900 58 #define EN_SCLK_DISP0 0x0a00 59 #define EN_SCLK_DISP1 0x0a04 60 #define EN_IP_DISP 0x0b00 61 #define EN_IP_DISP_BUS 0x0b04 62 63 64 /* 65 *Registers for CMU_EGL 66 */ 67 #define EGL_PLL_LOCK 0x0000 68 #define EGL_DPLL_LOCK 0x0004 69 #define EGL_PLL_CON0 0x0100 70 #define EGL_PLL_CON1 0x0104 71 #define EGL_PLL_FREQ_DET 0x010c 72 #define EGL_DPLL_CON0 0x0110 73 #define EGL_DPLL_CON1 0x0114 74 #define EGL_DPLL_FREQ_DET 0x011c 75 #define MUX_SEL_EGL 0x0200 76 #define MUX_ENABLE_EGL 0x0300 77 #define MUX_STAT_EGL 0x0400 78 #define DIV_EGL 0x0600 79 #define DIV_EGL_PLL_FDET 0x0604 80 #define DIV_STAT_EGL 0x0700 81 #define DIV_STAT_EGL_PLL_FDET 0x0704 82 #define EN_ACLK_EGL 0x0800 83 #define EN_PCLK_EGL 0x0900 84 #define EN_SCLK_EGL 0x0a00 85 #define EN_IP_EGL 0x0b00 86 #define CLKOUT_CMU_EGL 0x0c00 87 #define CLKOUT_CMU_EGL_DIV_STAT 0x0c04 88 #define ARMCLK_STOPCTRL 0x1000 89 #define EAGLE_EMA_CTRL 0x1008 90 #define EAGLE_EMA_STATUS 0x100c 91 #define PWR_CTRL 0x1020 92 #define PWR_CTRL2 0x1024 93 #define CLKSTOP_CTRL 0x1028 94 #define INTR_SPREAD_EN 0x1080 95 #define INTR_SPREAD_USE_STANDBYWFI 0x1084 96 #define INTR_SPREAD_BLOCKING_DURATION 0x1088 97 #define CMU_EGL_SPARE0 0x2000 98 #define CMU_EGL_SPARE1 0x2004 99 #define CMU_EGL_SPARE2 0x2008 100 #define CMU_EGL_SPARE3 0x200c 101 #define CMU_EGL_SPARE4 0x2010 102 103 /* 104 *Registers for CMU_FSYS 105 */ 106 107 #define MUX_SEL_FSYS0 0x0200 108 #define MUX_SEL_FSYS1 0x0204 109 #define MUX_ENABLE_FSYS0 0x0300 110 #define MUX_ENABLE_FSYS1 0x0304 111 #define MUX_STAT_FSYS0 0x0400 112 #define MUX_STAT_FSYS1 0x0404 113 #define MUX_IGNORE_FSYS0 0x0500 114 #define MUX_IGNORE_FSYS1 0x0504 115 #define EN_ACLK_FSYS 0x0800 116 #define EN_ACLK_FSYS_SECURE_RTIC 0x0804 117 #define EN_ACLK_FSYS_SECURE_SMMU_RTIC 0x0808 118 #define EN_PCLK_FSYS 0x0900 119 #define EN_SCLK_FSYS 0x0a00 120 #define EN_IP_FSYS 0x0b00 121 #define EN_IP_FSYS_SECURE_RTIC 0x0b04 122 #define EN_IP_FSYS_SECURE_SMMU_RTIC 0x0b08 123 124 /* 125 *Registers for CMU_G2D 126 */ 127 128 #define MUX_SEL_G2D 0x0200 129 #define MUX_ENABLE_G2D 0x0300 130 #define MUX_STAT_G2D 0x0400 131 #define DIV_G2D 0x0600 132 #define DIV_STAT_G2D 0x0700 133 #define EN_ACLK_G2D 0x0800 134 #define EN_ACLK_G2D_SECURE_SSS 0x0804 135 #define EN_ACLK_G2D_SECURE_SLIM_SSS 0x0808 136 #define EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS 0x080c 137 #define EN_ACLK_G2D_SECURE_SMMU_SSS 0x0810 138 #define EN_ACLK_G2D_SECURE_SMMU_MDMA 0x0814 139 #define EN_ACLK_G2D_SECURE_SMMU_G2D 0x0818 140 #define EN_PCLK_G2D 0x0900 141 #define EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS 0x0904 142 #define EN_PCLK_G2D_SECURE_SMMU_SSS 0x0908 143 #define EN_PCLK_G2D_SECURE_SMMU_MDMA 0x090c 144 #define EN_PCLK_G2D_SECURE_SMMU_G2D 0x0910 145 #define EN_IP_G2D 0x0b00 146 #define EN_IP_G2D_SECURE_SSS 0x0b04 147 #define EN_IP_G2D_SECURE_SLIM_SSS 0x0b08 148 #define EN_IP_G2D_SECURE_SMMU_SLIM_SSS 0x0b0c 149 #define EN_IP_G2D_SECURE_SMMU_SSS 0x0b10 150 #define EN_IP_G2D_SECURE_SMMU_MDMA 0x0b14 151 #define EN_IP_G2D_SECURE_SMMU_G2D 0x0b18 152 153 /* 154 *Registers for CMU_G3D 155 */ 156 157 #define G3D_PLL_LOCK 0x0000 158 #define G3D_PLL_CON0 0x0100 159 #define G3D_PLL_CON1 0x0104 160 #define G3D_PLL_FDET 0x010c 161 #define MUX_SEL_G3D 0x0200 162 #define MUX_EN_G3D 0x0300 163 #define MUX_STAT_G3D 0x0400 164 #define MUX_IGNORE_G3D 0x0500 165 #define DIV_G3D 0x0600 166 #define DIV_G3D_PLL_FDET 0x0604 167 #define DIV_STAT_G3D 0x0700 168 #define DIV_STAT_G3D_PLL_FDET 0x0704 169 #define EN_ACLK_G3D 0x0800 170 #define EN_PCLK_G3D 0x0900 171 #define EN_SCLK_G3D 0x0a00 172 #define EN_IP_G3D 0x0b00 173 #define CLKOUT_CMU_G3D 0x0c00 174 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 175 #define G3DCLK_STOPCTRL 0x1000 176 #define G3D_EMA_CTRL 0x1008 177 #define G3D_EMA_STATUS 0x100c 178 179 /* 180 *Registers for CMU_GSCL 181 */ 182 183 #define MUX_SEL_GSCL 0x0200 184 #define MUX_EN_GSCL 0x0300 185 #define MUX_STAT_GSCL 0x0400 186 #define MUX_IGNORE_GSCL 0x0500 187 #define DIV_GSCL 0x0600 188 #define DIV_STAT_GSCL 0x0700 189 #define EN_ACLK_GSCL 0x0800 190 #define EN_ACLK_GSCL_FIMC 0x0804 191 #define EN_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0808 192 #define EN_ACLK_GSCL_SECURE_SMMU_GSCL1 0x080c 193 #define EN_ACLK_GSCL_SECURE_SMMU_MSCL0 0x0810 194 #define EN_ACLK_GSCL_SECURE_SMMU_MSCL1 0x0814 195 #define EN_PCLK_GSCL 0x0900 196 #define EN_PCLK_GSCL_FIMC 0x0904 197 #define EN_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0908 198 #define EN_PCLK_GSCL_SECURE_SMMU_GSCL1 0x090c 199 #define EN_PCLK_GSCL_SECURE_SMMU_MSCL0 0x0910 200 #define EN_PCLK_GSCL_SECURE_SMMU_MSCL1 0x0914 201 #define EN_SCLK_GSCL 0x0a00 202 #define EN_SCLK_GSCL_FIMC 0x0a04 203 #define EN_IP_GSCL 0x0b00 204 #define EN_IP_GSCL_FIMC 0x0b04 205 #define EN_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 206 #define EN_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 207 #define EN_IP_GSCL_SECURE_SMMU_MSCL0 0x0b10 208 #define EN_IP_GSCL_SECURE_SMMU_MSCL1 0x0b14 209 210 /* 211 *Registers for CMU_ISP 212 */ 213 #define MUX_SEL_ISP0 0x0200 214 #define MUX_SEL_ISP1 0x0204 215 #define MUX_ENABLE_ISP0 0x0300 216 #define MUX_ENABLE_ISP1 0x0304 217 #define MUX_STAT_ISP0 0x0400 218 #define MUX_STAT_ISP1 0x0404 219 #define MUX_IGNORE_ISP0 0x0500 220 #define MUX_IGNORE_ISP1 0x0504 221 #define DIV_ISP 0x0600 222 #define DIV_STAT_ISP 0x0700 223 #define EN_ACLK_ISP0 0x0800 224 #define EN_ACLK_ISP1 0x0804 225 #define EN_PCLK_ISP0 0x0900 226 #define EN_PCLK_ISP1 0x0904 227 #define EN_SCLK_ISP 0x0a00 228 #define EN_IP_ISP0 0x0b00 229 #define EN_IP_ISP1 0x0b04 230 231 /* 232 *Registers for CMU_KFC 233 */ 234 #define KFC_PLL_LOCK 0x0000 235 #define KFC_PLL_CON0 0x0100 236 #define KFC_PLL_CON1 0x0104 237 #define KFC_PLL_FDET 0x010c 238 #define MUX_SEL_KFC0 0x0200 239 #define MUX_SEL_KFC2 0x0208 240 #define MUX_ENABLE_KFC0 0x0300 241 #define MUX_ENABLE_KFC2 0x0308 242 #define MUX_STAT_KFC0 0x0400 243 #define MUX_STAT_KFC2 0x0408 244 #define DIV_KFC 0x0600 245 #define DIV_KFC_PLL_FDET 0x0604 246 #define DIV_STAT_KFC 0x0700 247 #define DIV_STAT_KFC_PLL_FDET 0x0704 248 #define EN_ACLK_KFC 0x0800 249 #define EN_PCLK_KFC 0x0900 250 #define EN_SCLK_KFC 0x0a00 251 #define EN_IP_KFC 0x0b00 252 #define CLKOUT_CMU_KFC 0x0c00 253 #define CLKOUT_CMU_KFC_DIV_STAT 0x0c04 254 #define ARMCLK_STOPCTRL_KFC 0x1000 255 #define ARM_EMA_CTRL 0x1008 256 #define ARM_EMA_STATUS 0x100c 257 #define PWR_CTRL_KFC 0x1020 258 #define PWR_CTRL2_KFC 0x1024 259 #define CLKSTOP_CTRL_KFC 0x1028 260 #define INTR_SPREAD_ENABLE_KFC 0x1080 261 #define INTR_SPREAD_USE_STANDBYWFI_KFC 0x1084 262 #define INTR_SPREAD_BLOCKING_DURATION_KFC 0x1088 263 #define CMU_KFC_SPARE0 0x2000 264 #define CMU_KFC_SPARE1 0x2004 265 #define CMU_KFC_SPARE2 0x2008 266 #define CMU_KFC_SPARE3 0x200c 267 #define CMU_KFC_SPARE4 0x2010 268 269 /* 270 *Registers for CMU_MFC 271 */ 272 #define MUX_SEL_MFC 0x0200 273 #define MUX_ENABLE_MFC 0x0300 274 #define MUX_STAT_MFC 0x0400 275 #define DIV_MFC 0x0600 276 #define DIV_STAT_MFC 0x0700 277 #define EN_ACLK_MFC 0x0800 278 #define EN_ACLK_SECURE_SMMU2_MFC 0x0804 279 #define EN_PCLK_MFC 0x0900 280 #define EN_PCLK_SECURE_SMMU2_MFC 0x0904 281 #define EN_IP_MFC 0x0b00 282 #define EN_IP_MFC_SECURE_SMMU2_MFC 0x0b04 283 284 /* 285 *Registers for CMU_MIF 286 */ 287 #define MEM_PLL_LOCK 0x0000 288 #define BUS_PLL_LOCK 0x0004 289 #define MEDIA_PLL_LOCK 0x0008 290 #define MEM_PLL_CON0 0x0100 291 #define MEM_PLL_CON1 0x0104 292 #define MEM_PLL_FDET 0x010c 293 #define BUS_PLL_CON0 0x0110 294 #define BUS_PLL_CON1 0x0114 295 #define BUS_PLL_FDET 0x011c 296 #define MEDIA_PLL_CON0 0x0120 297 #define MEDIA_PLL_CON1 0x0124 298 #define MEDIA_PLL_FDET 0x012c 299 #define MUX_SEL_MIF 0x0200 300 #define MUX_ENABLE_MIF 0x0300 301 #define MUX_STAT_MIF 0x0400 302 #define MUX_IGNORE_MIF 0x0500 303 #define DIV_MIF 0x0600 304 #define DIV_MIF_PLL_FDET 0x0604 305 #define DIV_STAT_MIF 0x0700 306 #define DIV_STAT_MIF_PLL_FDET 0x0704 307 #define EN_ACLK_MIF 0x0800 308 #define EN_ACLK_MIF_SECURE_DREX1_TZ 0x0804 309 #define EN_ACLK_MIF_SECURE_DREX0_TZ 0x0808 310 #define EN_ACLK_MIF_SECURE_INTMEM 0x080c 311 #define EN_PCLK_MIF 0x0900 312 #define EN_PCLK_MIF_SECURE_MONOCNT 0x0904 313 #define EN_PCLK_MIF_SECURE_RTC_APBIF 0x0908 314 #define EN_PCLK_MIF_SECURE_DREX1_TZ 0x090c 315 #define EN_PCLK_MIF_SECURE_DREX0_TZ 0x0910 316 #define EN_SCLK_MIF 0x0a00 317 #define EN_IP_MIF 0x0b00 318 #define EN_IP_MIF_SECURE_MONOCNT 0x0b04 319 #define EN_IP_MIF_SECURE_RTC_APBIF 0x0b08 320 #define EN_IP_MIF_SECURE_DREX1_TZ 0x0b0c 321 #define EN_IP_MIF_SECURE_DREX0_TZ 0x0b10 322 #define EN_IP_MIF_SECURE_INTEMEM 0x0b14 323 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 324 #define DREX_FREQ_CTRL 0x1000 325 #define PAUSE 0x1004 326 #define DDRPHY_LOCK_CTRL 0x1008 327 #define CLKOUT_CMU_MIF 0xcb00 328 329 /* 330 *Registers for CMU_PERI 331 */ 332 #define MUX_SEL_PERI 0x0200 333 #define MUX_SEL_PERI1 0x0204 334 #define MUX_ENABLE_PERI 0x0300 335 #define MUX_ENABLE_PERI1 0x0304 336 #define MUX_STAT_PERI 0x0400 337 #define MUX_STAT_PERI1 0x0404 338 #define MUX_IGNORE_PERI 0x0500 339 #define MUX_IGNORE_PERI1 0x0504 340 #define DIV_PERI 0x0600 341 #define DIV_STAT_PERI 0x0700 342 #define EN_PCLK_PERI0 0x0800 343 #define EN_PCLK_PERI1 0x0804 344 #define EN_PCLK_PERI2 0x0808 345 #define EN_PCLK_PERI3 0x080c 346 #define EN_PCLK_PERI_SECURE_CHIPID 0x0810 347 #define EN_PCLK_PERI_SECURE_PROVKEY0 0x0814 348 #define EN_PCLK_PERI_SECURE_PROVKEY1 0x0818 349 #define EN_PCLK_PERI_SECURE_SECKEY 0x081c 350 #define EN_PCLK_PERI_SECURE_ANTIRBKCNT 0x0820 351 #define EN_PCLK_PERI_SECURE_TOP_RTC 0x0824 352 #define EN_PCLK_PERI_SECURE_TZPC 0x0828 353 #define EN_SCLK_PERI 0x0a00 354 #define EN_SCLK_PERI_SECURE_TOP_RTC 0x0a04 355 #define EN_IP_PERI0 0x0b00 356 #define EN_IP_PERI1 0x0b04 357 #define EN_IP_PERI2 0x0b08 358 #define EN_IP_PERI_SECURE_CHIPID 0x0b0c 359 #define EN_IP_PERI_SECURE_PROVKEY0 0x0b10 360 #define EN_IP_PERI_SECURE_PROVKEY1 0x0b14 361 #define EN_IP_PERI_SECURE_SECKEY 0x0b18 362 #define EN_IP_PERI_SECURE_ANTIRBKCNT 0x0b1c 363 #define EN_IP_PERI_SECURE_TOP_RTC 0x0b20 364 #define EN_IP_PERI_SECURE_TZPC 0x0b24 365 366 /* 367 *Registers for CMU_TOP 368 */ 369 #define DISP_PLL_LOCK 0x0000 370 #define AUD_PLL_LOCK 0x0004 371 #define DISP_PLL_CON0 0x0100 372 #define DISP_PLL_CON1 0x0104 373 #define DISP_PLL_FDET 0x0108 374 #define AUD_PLL_CON0 0x0110 375 #define AUD_PLL_CON1 0x0114 376 #define AUD_PLL_CON2 0x0118 377 #define AUD_PLL_FDET 0x011c 378 #define MUX_SEL_TOP_PLL0 0x0200 379 #define MUX_SEL_TOP_MFC 0x0204 380 #define MUX_SEL_TOP_G2D 0x0208 381 #define MUX_SEL_TOP_GSCL 0x020c 382 #define MUX_SEL_TOP_ISP10 0x0214 383 #define MUX_SEL_TOP_ISP11 0x0218 384 #define MUX_SEL_TOP_DISP0 0x021c 385 #define MUX_SEL_TOP_DISP1 0x0220 386 #define MUX_SEL_TOP_BUS 0x0224 387 #define MUX_SEL_TOP_PERI0 0x0228 388 #define MUX_SEL_TOP_PERI1 0x022c 389 #define MUX_SEL_TOP_FSYS 0x0230 390 #define MUX_ENABLE_TOP_PLL0 0x0300 391 #define MUX_ENABLE_TOP_MFC 0x0304 392 #define MUX_ENABLE_TOP_G2D 0x0308 393 #define MUX_ENABLE_TOP_GSCL 0x030c 394 #define MUX_ENABLE_TOP_ISP10 0x0314 395 #define MUX_ENABLE_TOP_ISP11 0x0318 396 #define MUX_ENABLE_TOP_DISP0 0x031c 397 #define MUX_ENABLE_TOP_DISP1 0x0320 398 #define MUX_ENABLE_TOP_BUS 0x0324 399 #define MUX_ENABLE_TOP_PERI0 0x0328 400 #define MUX_ENABLE_TOP_PERI1 0x032c 401 #define MUX_ENABLE_TOP_FSYS 0x0330 402 #define MUX_STAT_TOP_PLL0 0x0400 403 #define MUX_STAT_TOP_MFC 0x0404 404 #define MUX_STAT_TOP_G2D 0x0408 405 #define MUX_STAT_TOP_GSCL 0x040c 406 #define MUX_STAT_TOP_ISP10 0x0414 407 #define MUX_STAT_TOP_ISP11 0x0418 408 #define MUX_STAT_TOP_DISP0 0x041c 409 #define MUX_STAT_TOP_DISP1 0x0420 410 #define MUX_STAT_TOP_BUS 0x0424 411 #define MUX_STAT_TOP_PERI0 0x0428 412 #define MUX_STAT_TOP_PERI1 0x042c 413 #define MUX_STAT_TOP_FSYS 0x0430 414 #define MUX_IGNORE_TOP_PLL0 0x0500 415 #define MUX_IGNORE_TOP_MFC 0x0504 416 #define MUX_IGNORE_TOP_G2D 0x0508 417 #define MUX_IGNORE_TOP_GSCL 0x050c 418 #define MUX_IGNORE_TOP_ISP10 0x0514 419 #define MUX_IGNORE_TOP_ISP11 0x0518 420 #define MUX_IGNORE_TOP_DISP0 0x051c 421 #define MUX_IGNORE_TOP_DISP1 0x0520 422 #define MUX_IGNORE_TOP_BUS 0x0524 423 #define MUX_IGNORE_TOP_PERI0 0x0528 424 #define MUX_IGNORE_TOP_PERI1 0x052c 425 #define MUX_IGNORE_TOP_FSYS 0x0530 426 #define DIV_TOP_G2D_MFC 0x0600 427 #define DIV_TOP_GSCL_ISP0 0x0604 428 #define DIV_TOP_ISP10 0x0608 429 #define DIV_TOP_ISP11 0x060c 430 #define DIV_TOP_DISP 0x0610 431 #define DIV_TOP_BUS 0x0614 432 #define DIV_TOP_PERI0 0x0618 433 #define DIV_TOP_PERI1 0x061c 434 #define DIV_TOP_PERI2 0x0620 435 #define DIV_TOP_FSYS0 0x0624 436 #define DIV_TOP_FSYS1 0x0628 437 #define DIV_TOP_HPM 0x062c 438 #define DIV_TOP_PLL_FDET 0x0630 439 #define DIV_STAT_TOP_G2D_MFC 0x0700 440 #define DIV_STAT_TOP_GSCL_ISP0 0x0704 441 #define DIV_STAT_TOP_ISP10 0x0708 442 #define DIV_STAT_TOP_ISP11 0x070c 443 #define DIV_STAT_TOP_DISP 0x0710 444 #define DIV_STAT_TOP_BUS 0x0714 445 #define DIV_STAT_TOP_PERI0 0x0718 446 #define DIV_STAT_TOP_PERI1 0x071c 447 #define DIV_STAT_TOP_PERI2 0x0720 448 #define DIV_STAT_TOP_FSYS0 0x0724 449 #define DIV_STAT_TOP_FSYS1 0x0728 450 #define DIV_STAT_TOP_HPM 0x072c 451 #define DIV_STAT_TOP_PLL_FDET 0x0730 452 #define EN_ACLK_TOP 0x0800 453 #define EN_SCLK_TOP 0x0a00 454 #define EN_IP_TOP 0x0b00 455 #define CLKOUT_CMU_TOP 0x0c00 456 #define CLKOUT_CMU_TOP_DIV_STAT 0x0c04 457 458 #endif /*__CLK_EXYNOS5260_H */ 459 460