1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #if defined(QCA6750_HEADERS_DEF) 18 19 #undef UMAC 20 #define WLAN_HEADERS 1 21 #include "lithium_top_reg.h" 22 #include "wfss_ce_reg_seq_hwioreg.h" 23 #include "wcss_version.h" 24 25 #define MISSING 0 26 27 #define SOC_RESET_CONTROL_OFFSET MISSING 28 #define GPIO_PIN0_OFFSET MISSING 29 #define GPIO_PIN1_OFFSET MISSING 30 #define GPIO_PIN0_CONFIG_MASK MISSING 31 #define GPIO_PIN1_CONFIG_MASK MISSING 32 #define LOCAL_SCRATCH_OFFSET 0x18 33 #define GPIO_PIN10_OFFSET MISSING 34 #define GPIO_PIN11_OFFSET MISSING 35 #define GPIO_PIN12_OFFSET MISSING 36 #define GPIO_PIN13_OFFSET MISSING 37 #define MBOX_BASE_ADDRESS MISSING 38 #define INT_STATUS_ENABLE_ERROR_LSB MISSING 39 #define INT_STATUS_ENABLE_ERROR_MASK MISSING 40 #define INT_STATUS_ENABLE_CPU_LSB MISSING 41 #define INT_STATUS_ENABLE_CPU_MASK MISSING 42 #define INT_STATUS_ENABLE_COUNTER_LSB MISSING 43 #define INT_STATUS_ENABLE_COUNTER_MASK MISSING 44 #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING 45 #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING 46 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING 47 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING 48 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING 49 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING 50 #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING 51 #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING 52 #define INT_STATUS_ENABLE_ADDRESS MISSING 53 #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING 54 #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING 55 #define HOST_INT_STATUS_ADDRESS MISSING 56 #define CPU_INT_STATUS_ADDRESS MISSING 57 #define ERROR_INT_STATUS_ADDRESS MISSING 58 #define ERROR_INT_STATUS_WAKEUP_MASK MISSING 59 #define ERROR_INT_STATUS_WAKEUP_LSB MISSING 60 #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING 61 #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING 62 #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING 63 #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING 64 #define COUNT_DEC_ADDRESS MISSING 65 #define HOST_INT_STATUS_CPU_MASK MISSING 66 #define HOST_INT_STATUS_CPU_LSB MISSING 67 #define HOST_INT_STATUS_ERROR_MASK MISSING 68 #define HOST_INT_STATUS_ERROR_LSB MISSING 69 #define HOST_INT_STATUS_COUNTER_MASK MISSING 70 #define HOST_INT_STATUS_COUNTER_LSB MISSING 71 #define RX_LOOKAHEAD_VALID_ADDRESS MISSING 72 #define WINDOW_DATA_ADDRESS MISSING 73 #define WINDOW_READ_ADDR_ADDRESS MISSING 74 #define WINDOW_WRITE_ADDR_ADDRESS MISSING 75 /* GPIO Register */ 76 #define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING 77 #define GPIO_PIN0_CONFIG_LSB MISSING 78 #define GPIO_PIN0_PAD_PULL_LSB MISSING 79 #define GPIO_PIN0_PAD_PULL_MASK MISSING 80 /* SI reg */ 81 #define SI_CONFIG_ERR_INT_MASK MISSING 82 #define SI_CONFIG_ERR_INT_LSB MISSING 83 84 #define RTC_SOC_BASE_ADDRESS MISSING 85 #define RTC_WMAC_BASE_ADDRESS MISSING 86 #define SOC_CORE_BASE_ADDRESS MISSING 87 #define WLAN_MAC_BASE_ADDRESS MISSING 88 #define GPIO_BASE_ADDRESS MISSING 89 #define ANALOG_INTF_BASE_ADDRESS MISSING 90 #define CE0_BASE_ADDRESS MISSING 91 #define CE1_BASE_ADDRESS MISSING 92 #define CE_COUNT 12 93 #define CE_WRAPPER_BASE_ADDRESS MISSING 94 #define SI_BASE_ADDRESS MISSING 95 #define DRAM_BASE_ADDRESS MISSING 96 97 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING 98 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING 99 #define CLOCK_CONTROL_OFFSET MISSING 100 #define CLOCK_CONTROL_SI0_CLK_MASK MISSING 101 #define RESET_CONTROL_SI0_RST_MASK MISSING 102 #define WLAN_RESET_CONTROL_OFFSET MISSING 103 #define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING 104 #define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING 105 #define CPU_CLOCK_OFFSET MISSING 106 107 #define CPU_CLOCK_STANDARD_LSB MISSING 108 #define CPU_CLOCK_STANDARD_MASK MISSING 109 #define LPO_CAL_ENABLE_LSB MISSING 110 #define LPO_CAL_ENABLE_MASK MISSING 111 #define WLAN_SYSTEM_SLEEP_OFFSET MISSING 112 113 #define SOC_CHIP_ID_ADDRESS MISSING 114 #define SOC_CHIP_ID_REVISION_MASK MISSING 115 #define SOC_CHIP_ID_REVISION_LSB MISSING 116 #define SOC_CHIP_ID_REVISION_MSB MISSING 117 118 #define FW_IND_EVENT_PENDING MISSING 119 #define FW_IND_INITIALIZED MISSING 120 121 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING 122 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING 123 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING 124 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING 125 #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING 126 #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING 127 #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING 128 #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING 129 130 #define SR_WR_INDEX_ADDRESS MISSING 131 #define DST_WATERMARK_ADDRESS MISSING 132 133 #define DST_WR_INDEX_ADDRESS MISSING 134 #define SRC_WATERMARK_ADDRESS MISSING 135 #define SRC_WATERMARK_LOW_MASK MISSING 136 #define SRC_WATERMARK_HIGH_MASK MISSING 137 #define DST_WATERMARK_LOW_MASK MISSING 138 #define DST_WATERMARK_HIGH_MASK MISSING 139 #define CURRENT_SRRI_ADDRESS MISSING 140 #define CURRENT_DRRI_ADDRESS MISSING 141 #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING 142 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING 143 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING 144 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING 145 #define HOST_IS_ADDRESS MISSING 146 #define MISC_IS_ADDRESS MISSING 147 #define HOST_IS_COPY_COMPLETE_MASK MISSING 148 #define CE_WRAPPER_BASE_ADDRESS MISSING 149 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING 150 #define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING 151 #define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING 152 153 #define HOST_IE_ADDRESS HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR 154 #define HOST_IE_ADDRESS_2 HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR 155 156 #define HOST_IE_COPY_COMPLETE_MASK MISSING 157 #define SR_BA_ADDRESS MISSING 158 #define SR_BA_ADDRESS_HIGH MISSING 159 #define SR_SIZE_ADDRESS MISSING 160 #define CE_CTRL1_ADDRESS MISSING 161 #define CE_CTRL1_DMAX_LENGTH_MASK MISSING 162 #define DR_BA_ADDRESS MISSING 163 #define DR_BA_ADDRESS_HIGH MISSING 164 #define DR_SIZE_ADDRESS MISSING 165 #define CE_CMD_REGISTER MISSING 166 #define CE_MSI_ADDRESS MISSING 167 #define CE_MSI_ADDRESS_HIGH MISSING 168 #define CE_MSI_DATA MISSING 169 #define CE_MSI_ENABLE_BIT MISSING 170 #define MISC_IE_ADDRESS MISSING 171 #define MISC_IS_AXI_ERR_MASK MISSING 172 #define MISC_IS_DST_ADDR_ERR_MASK MISSING 173 #define MISC_IS_SRC_LEN_ERR_MASK MISSING 174 #define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING 175 #define MISC_IS_DST_RING_OVERFLOW_MASK MISSING 176 #define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING 177 #define SRC_WATERMARK_LOW_LSB MISSING 178 #define SRC_WATERMARK_HIGH_LSB MISSING 179 #define DST_WATERMARK_LOW_LSB MISSING 180 #define DST_WATERMARK_HIGH_LSB MISSING 181 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING 182 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING 183 #define CE_CTRL1_DMAX_LENGTH_LSB MISSING 184 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING 185 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING 186 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING 187 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING 188 #define CE_CTRL1_IDX_UPD_EN_MASK MISSING 189 #define CE_WRAPPER_DEBUG_OFFSET MISSING 190 #define CE_WRAPPER_DEBUG_SEL_MSB MISSING 191 #define CE_WRAPPER_DEBUG_SEL_LSB MISSING 192 #define CE_WRAPPER_DEBUG_SEL_MASK MISSING 193 #define CE_DEBUG_OFFSET MISSING 194 #define CE_DEBUG_SEL_MSB MISSING 195 #define CE_DEBUG_SEL_LSB MISSING 196 #define CE_DEBUG_SEL_MASK MISSING 197 #define CE0_BASE_ADDRESS MISSING 198 #define CE1_BASE_ADDRESS MISSING 199 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING 200 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING 201 202 #define QCA6750_BOARD_DATA_SZ MISSING 203 #define QCA6750_BOARD_EXT_DATA_SZ MISSING 204 205 #define MY_TARGET_DEF QCA6750_TARGETdef 206 #define MY_HOST_DEF QCA6750_HOSTdef 207 #define MY_CEREG_DEF QCA6750_CE_TARGETdef 208 #define MY_TARGET_BOARD_DATA_SZ QCA6750_BOARD_DATA_SZ 209 #define MY_TARGET_BOARD_EXT_DATA_SZ QCA6750_BOARD_EXT_DATA_SZ 210 #include "targetdef.h" 211 #include "hostdef.h" 212 #else 213 #include "common_drv.h" 214 #include "targetdef.h" 215 #include "hostdef.h" 216 struct targetdef_s *QCA6750_TARGETdef; 217 struct hostdef_s *QCA6750_HOSTdef; 218 #endif /*QCA6750_HEADERS_DEF */ 219