1 /*
2  * Copyright (C) 2014 Google, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  */
8 
9 #ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H
10 #define _DT_BINDINGS_CLOCK_PISTACHIO_H
11 
12 /* PLLs */
13 #define CLK_MIPS_PLL			0
14 #define CLK_AUDIO_PLL			1
15 #define CLK_RPU_V_PLL			2
16 #define CLK_RPU_L_PLL			3
17 #define CLK_SYS_PLL			4
18 #define CLK_WIFI_PLL			5
19 #define CLK_BT_PLL			6
20 
21 /* Fixed-factor clocks */
22 #define CLK_WIFI_DIV4			16
23 #define CLK_WIFI_DIV8			17
24 
25 /* Gate clocks */
26 #define CLK_MIPS			32
27 #define CLK_AUDIO_IN			33
28 #define CLK_AUDIO			34
29 #define CLK_I2S				35
30 #define CLK_SPDIF			36
31 #define CLK_AUDIO_DAC			37
32 #define CLK_RPU_V			38
33 #define CLK_RPU_L			39
34 #define CLK_RPU_SLEEP			40
35 #define CLK_WIFI_PLL_GATE		41
36 #define CLK_RPU_CORE			42
37 #define CLK_WIFI_ADC			43
38 #define CLK_WIFI_DAC			44
39 #define CLK_USB_PHY			45
40 #define CLK_ENET_IN			46
41 #define CLK_ENET			47
42 #define CLK_UART0			48
43 #define CLK_UART1			49
44 #define CLK_PERIPH_SYS			50
45 #define CLK_SPI0			51
46 #define CLK_SPI1			52
47 #define CLK_EVENT_TIMER			53
48 #define CLK_AUX_ADC_INTERNAL		54
49 #define CLK_AUX_ADC			55
50 #define CLK_SD_HOST			56
51 #define CLK_BT				57
52 #define CLK_BT_DIV4			58
53 #define CLK_BT_DIV8			59
54 #define CLK_BT_1MHZ			60
55 
56 /* Divider clocks */
57 #define CLK_MIPS_INTERNAL_DIV		64
58 #define CLK_MIPS_DIV			65
59 #define CLK_AUDIO_DIV			66
60 #define CLK_I2S_DIV			67
61 #define CLK_SPDIF_DIV			68
62 #define CLK_AUDIO_DAC_DIV		69
63 #define CLK_RPU_V_DIV			70
64 #define CLK_RPU_L_DIV			71
65 #define CLK_RPU_SLEEP_DIV		72
66 #define CLK_RPU_CORE_DIV		73
67 #define CLK_USB_PHY_DIV			74
68 #define CLK_ENET_DIV			75
69 #define CLK_UART0_INTERNAL_DIV		76
70 #define CLK_UART0_DIV			77
71 #define CLK_UART1_INTERNAL_DIV		78
72 #define CLK_UART1_DIV			79
73 #define CLK_SYS_INTERNAL_DIV		80
74 #define CLK_SPI0_INTERNAL_DIV		81
75 #define CLK_SPI0_DIV			82
76 #define CLK_SPI1_INTERNAL_DIV		83
77 #define CLK_SPI1_DIV			84
78 #define CLK_EVENT_TIMER_INTERNAL_DIV	85
79 #define CLK_EVENT_TIMER_DIV		86
80 #define CLK_AUX_ADC_INTERNAL_DIV	87
81 #define CLK_AUX_ADC_DIV			88
82 #define CLK_SD_HOST_DIV			89
83 #define CLK_BT_DIV			90
84 #define CLK_BT_DIV4_DIV			91
85 #define CLK_BT_DIV8_DIV			92
86 #define CLK_BT_1MHZ_INTERNAL_DIV	93
87 #define CLK_BT_1MHZ_DIV			94
88 
89 /* Mux clocks */
90 #define CLK_AUDIO_REF_MUX		96
91 #define CLK_MIPS_PLL_MUX		97
92 #define CLK_AUDIO_PLL_MUX		98
93 #define CLK_AUDIO_MUX			99
94 #define CLK_RPU_V_PLL_MUX		100
95 #define CLK_RPU_L_PLL_MUX		101
96 #define CLK_RPU_L_MUX			102
97 #define CLK_WIFI_PLL_MUX		103
98 #define CLK_WIFI_DIV4_MUX		104
99 #define CLK_WIFI_DIV8_MUX		105
100 #define CLK_RPU_CORE_MUX		106
101 #define CLK_SYS_PLL_MUX			107
102 #define CLK_ENET_MUX			108
103 #define CLK_EVENT_TIMER_MUX		109
104 #define CLK_SD_HOST_MUX			110
105 #define CLK_BT_PLL_MUX			111
106 #define CLK_DEBUG_MUX			112
107 
108 #define CLK_NR_CLKS			113
109 
110 /* Peripheral gate clocks */
111 #define PERIPH_CLK_SYS			0
112 #define PERIPH_CLK_SYS_BUS		1
113 #define PERIPH_CLK_DDR			2
114 #define PERIPH_CLK_ROM			3
115 #define PERIPH_CLK_COUNTER_FAST		4
116 #define PERIPH_CLK_COUNTER_SLOW		5
117 #define PERIPH_CLK_IR			6
118 #define PERIPH_CLK_WD			7
119 #define PERIPH_CLK_PDM			8
120 #define PERIPH_CLK_PWM			9
121 #define PERIPH_CLK_I2C0			10
122 #define PERIPH_CLK_I2C1			11
123 #define PERIPH_CLK_I2C2			12
124 #define PERIPH_CLK_I2C3			13
125 
126 /* Peripheral divider clocks */
127 #define PERIPH_CLK_ROM_DIV		32
128 #define PERIPH_CLK_COUNTER_FAST_DIV	33
129 #define PERIPH_CLK_COUNTER_SLOW_PRE_DIV	34
130 #define PERIPH_CLK_COUNTER_SLOW_DIV	35
131 #define PERIPH_CLK_IR_PRE_DIV		36
132 #define PERIPH_CLK_IR_DIV		37
133 #define PERIPH_CLK_WD_PRE_DIV		38
134 #define PERIPH_CLK_WD_DIV		39
135 #define PERIPH_CLK_PDM_PRE_DIV		40
136 #define PERIPH_CLK_PDM_DIV		41
137 #define PERIPH_CLK_PWM_PRE_DIV		42
138 #define PERIPH_CLK_PWM_DIV		43
139 #define PERIPH_CLK_I2C0_PRE_DIV		44
140 #define PERIPH_CLK_I2C0_DIV		45
141 #define PERIPH_CLK_I2C1_PRE_DIV		46
142 #define PERIPH_CLK_I2C1_DIV		47
143 #define PERIPH_CLK_I2C2_PRE_DIV		48
144 #define PERIPH_CLK_I2C2_DIV		49
145 #define PERIPH_CLK_I2C3_PRE_DIV		50
146 #define PERIPH_CLK_I2C3_DIV		51
147 
148 #define PERIPH_CLK_NR_CLKS		52
149 
150 /* System gate clocks */
151 #define SYS_CLK_I2C0			0
152 #define SYS_CLK_I2C1			1
153 #define SYS_CLK_I2C2			2
154 #define SYS_CLK_I2C3			3
155 #define SYS_CLK_I2S_IN			4
156 #define SYS_CLK_PAUD_OUT		5
157 #define SYS_CLK_SPDIF_OUT		6
158 #define SYS_CLK_SPI0_MASTER		7
159 #define SYS_CLK_SPI0_SLAVE		8
160 #define SYS_CLK_PWM			9
161 #define SYS_CLK_UART0			10
162 #define SYS_CLK_UART1			11
163 #define SYS_CLK_SPI1			12
164 #define SYS_CLK_MDC			13
165 #define SYS_CLK_SD_HOST			14
166 #define SYS_CLK_ENET			15
167 #define SYS_CLK_IR			16
168 #define SYS_CLK_WD			17
169 #define SYS_CLK_TIMER			18
170 #define SYS_CLK_I2S_OUT			24
171 #define SYS_CLK_SPDIF_IN		25
172 #define SYS_CLK_EVENT_TIMER		26
173 #define SYS_CLK_HASH			27
174 
175 #define SYS_CLK_NR_CLKS			28
176 
177 /* Gates for external input clocks */
178 #define EXT_CLK_AUDIO_IN		0
179 #define EXT_CLK_ENET_IN			1
180 
181 #define EXT_CLK_NR_CLKS			2
182 
183 #endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */
184