1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3  * V4L2 DV timings header.
4  *
5  * Copyright (C) 2012-2016  Hans Verkuil <hans.verkuil@cisco.com>
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * version 2 as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but
12  * WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * General Public License for more details.
15  */
16 
17 #ifndef _V4L2_DV_TIMINGS_H
18 #define _V4L2_DV_TIMINGS_H
19 
20 #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
21 /* Sadly gcc versions older than 4.6 have a bug in how they initialize
22    anonymous unions where they require additional curly brackets.
23    This violates the C1x standard. This workaround adds the curly brackets
24    if needed. */
25 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
26 	{ .bt = { _width , ## args } }
27 #else
28 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
29 	.bt = { _width , ## args }
30 #endif
31 
32 /* CEA-861-F timings (i.e. standard HDTV timings) */
33 
34 #define V4L2_DV_BT_CEA_640X480P59_94 { \
35 	.type = V4L2_DV_BT_656_1120, \
36 	V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
37 		25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
38 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
39 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \
40 }
41 
42 /* Note: these are the nominal timings, for HDMI links this format is typically
43  * double-clocked to meet the minimum pixelclock requirements.  */
44 #define V4L2_DV_BT_CEA_720X480I59_94 { \
45 	.type = V4L2_DV_BT_656_1120, \
46 	V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
47 		13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
48 		V4L2_DV_BT_STD_CEA861, \
49 		V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
50 		V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
51 		{ 4, 3 }, 6) \
52 }
53 
54 #define V4L2_DV_BT_CEA_720X480P59_94 { \
55 	.type = V4L2_DV_BT_656_1120, \
56 	V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
57 		27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
58 		V4L2_DV_BT_STD_CEA861, \
59 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
60 		V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \
61 }
62 
63 /* Note: these are the nominal timings, for HDMI links this format is typically
64  * double-clocked to meet the minimum pixelclock requirements.  */
65 #define V4L2_DV_BT_CEA_720X576I50 { \
66 	.type = V4L2_DV_BT_656_1120, \
67 	V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
68 		13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
69 		V4L2_DV_BT_STD_CEA861, \
70 		V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
71 		V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
72 		{ 4, 3 }, 21) \
73 }
74 
75 #define V4L2_DV_BT_CEA_720X576P50 { \
76 	.type = V4L2_DV_BT_656_1120, \
77 	V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
78 		27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
79 		V4L2_DV_BT_STD_CEA861, \
80 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
81 		V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \
82 }
83 
84 #define V4L2_DV_BT_CEA_1280X720P24 { \
85 	.type = V4L2_DV_BT_656_1120, \
86 	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
87 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
88 		59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
89 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
90 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
91 }
92 
93 #define V4L2_DV_BT_CEA_1280X720P25 { \
94 	.type = V4L2_DV_BT_656_1120, \
95 	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
96 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
97 		74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
98 		V4L2_DV_BT_STD_CEA861, \
99 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
100 }
101 
102 #define V4L2_DV_BT_CEA_1280X720P30 { \
103 	.type = V4L2_DV_BT_656_1120, \
104 	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
105 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
106 		74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
107 		V4L2_DV_BT_STD_CEA861, \
108 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
109 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
110 }
111 
112 #define V4L2_DV_BT_CEA_1280X720P50 { \
113 	.type = V4L2_DV_BT_656_1120, \
114 	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
115 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
116 		74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
117 		V4L2_DV_BT_STD_CEA861, \
118 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
119 }
120 
121 #define V4L2_DV_BT_CEA_1280X720P60 { \
122 	.type = V4L2_DV_BT_656_1120, \
123 	V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
124 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
125 		74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
126 		V4L2_DV_BT_STD_CEA861, \
127 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
128 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \
129 }
130 
131 #define V4L2_DV_BT_CEA_1920X1080P24 { \
132 	.type = V4L2_DV_BT_656_1120, \
133 	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
134 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
135 		74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
136 		V4L2_DV_BT_STD_CEA861, \
137 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
138 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \
139 }
140 
141 #define V4L2_DV_BT_CEA_1920X1080P25 { \
142 	.type = V4L2_DV_BT_656_1120, \
143 	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
144 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
145 		74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
146 		V4L2_DV_BT_STD_CEA861, \
147 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \
148 }
149 
150 #define V4L2_DV_BT_CEA_1920X1080P30 { \
151 	.type = V4L2_DV_BT_656_1120, \
152 	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
153 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
154 		74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
155 		V4L2_DV_BT_STD_CEA861, \
156 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
157 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \
158 }
159 
160 #define V4L2_DV_BT_CEA_1920X1080I50 { \
161 	.type = V4L2_DV_BT_656_1120, \
162 	V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
163 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
164 		74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
165 		V4L2_DV_BT_STD_CEA861, \
166 		V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
167 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
168 }
169 
170 #define V4L2_DV_BT_CEA_1920X1080P50 { \
171 	.type = V4L2_DV_BT_656_1120, \
172 	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
173 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
174 		148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
175 		V4L2_DV_BT_STD_CEA861, \
176 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 31) \
177 }
178 
179 #define V4L2_DV_BT_CEA_1920X1080I60 { \
180 	.type = V4L2_DV_BT_656_1120, \
181 	V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
182 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
183 		74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
184 		V4L2_DV_BT_STD_CEA861, \
185 		V4L2_DV_FL_CAN_REDUCE_FPS | \
186 		V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
187 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 5) \
188 }
189 
190 #define V4L2_DV_BT_CEA_1920X1080P60 { \
191 	.type = V4L2_DV_BT_656_1120, \
192 	V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
193 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
194 		148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
195 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
196 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
197 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 16) \
198 }
199 
200 #define V4L2_DV_BT_CEA_3840X2160P24 { \
201 	.type = V4L2_DV_BT_656_1120, \
202 	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
203 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
204 		297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
205 		V4L2_DV_BT_STD_CEA861, \
206 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
207 		V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
208 		{ 0, 0 }, 93, 3) \
209 }
210 
211 #define V4L2_DV_BT_CEA_3840X2160P25 { \
212 	.type = V4L2_DV_BT_656_1120, \
213 	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
214 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
215 		297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
216 		V4L2_DV_BT_STD_CEA861, \
217 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC | \
218 		V4L2_DV_FL_HAS_HDMI_VIC, { 0, 0 }, 94, 2) \
219 }
220 
221 #define V4L2_DV_BT_CEA_3840X2160P30 { \
222 	.type = V4L2_DV_BT_656_1120, \
223 	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
224 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
225 		297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
226 		V4L2_DV_BT_STD_CEA861, \
227 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
228 		V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
229 		{ 0, 0 }, 95, 1) \
230 }
231 
232 #define V4L2_DV_BT_CEA_3840X2160P50 { \
233 	.type = V4L2_DV_BT_656_1120, \
234 	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
235 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
236 		594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
237 		V4L2_DV_BT_STD_CEA861, \
238 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 96) \
239 }
240 
241 #define V4L2_DV_BT_CEA_3840X2160P60 { \
242 	.type = V4L2_DV_BT_656_1120, \
243 	V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
244 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
245 		594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
246 		V4L2_DV_BT_STD_CEA861, \
247 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
248 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 97) \
249 }
250 
251 #define V4L2_DV_BT_CEA_4096X2160P24 { \
252 	.type = V4L2_DV_BT_656_1120, \
253 	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
254 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
255 		297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
256 		V4L2_DV_BT_STD_CEA861, \
257 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
258 		V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
259 		{ 0, 0 }, 98, 4) \
260 }
261 
262 #define V4L2_DV_BT_CEA_4096X2160P25 { \
263 	.type = V4L2_DV_BT_656_1120, \
264 	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
265 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
266 		297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
267 		V4L2_DV_BT_STD_CEA861, \
268 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 99) \
269 }
270 
271 #define V4L2_DV_BT_CEA_4096X2160P30 { \
272 	.type = V4L2_DV_BT_656_1120, \
273 	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
274 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
275 		297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
276 		V4L2_DV_BT_STD_CEA861, \
277 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
278 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \
279 }
280 
281 #define V4L2_DV_BT_CEA_4096X2160P50 { \
282 	.type = V4L2_DV_BT_656_1120, \
283 	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
284 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
285 		594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
286 		V4L2_DV_BT_STD_CEA861, \
287 		V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 101) \
288 }
289 
290 #define V4L2_DV_BT_CEA_4096X2160P60 { \
291 	.type = V4L2_DV_BT_656_1120, \
292 	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
293 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
294 		594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
295 		V4L2_DV_BT_STD_CEA861, \
296 		V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
297 		V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
298 }
299 
300 
301 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
302 
303 #define V4L2_DV_BT_DMT_640X350P85 { \
304 	.type = V4L2_DV_BT_656_1120, \
305 	V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
306 		31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
307 		V4L2_DV_BT_STD_DMT, 0) \
308 }
309 
310 #define V4L2_DV_BT_DMT_640X400P85 { \
311 	.type = V4L2_DV_BT_656_1120, \
312 	V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
313 		31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
314 		V4L2_DV_BT_STD_DMT, 0) \
315 }
316 
317 #define V4L2_DV_BT_DMT_720X400P85 { \
318 	.type = V4L2_DV_BT_656_1120, \
319 	V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
320 		35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
321 		V4L2_DV_BT_STD_DMT, 0) \
322 }
323 
324 /* VGA resolutions */
325 #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
326 
327 #define V4L2_DV_BT_DMT_640X480P72 { \
328 	.type = V4L2_DV_BT_656_1120, \
329 	V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
330 		31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
331 		V4L2_DV_BT_STD_DMT, 0) \
332 }
333 
334 #define V4L2_DV_BT_DMT_640X480P75 { \
335 	.type = V4L2_DV_BT_656_1120, \
336 	V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
337 		31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
338 		V4L2_DV_BT_STD_DMT, 0) \
339 }
340 
341 #define V4L2_DV_BT_DMT_640X480P85 { \
342 	.type = V4L2_DV_BT_656_1120, \
343 	V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
344 		36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
345 		V4L2_DV_BT_STD_DMT, 0) \
346 }
347 
348 /* SVGA resolutions */
349 #define V4L2_DV_BT_DMT_800X600P56 { \
350 	.type = V4L2_DV_BT_656_1120, \
351 	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
352 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
353 		36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
354 		V4L2_DV_BT_STD_DMT, 0) \
355 }
356 
357 #define V4L2_DV_BT_DMT_800X600P60 { \
358 	.type = V4L2_DV_BT_656_1120, \
359 	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
360 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
361 		40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
362 		V4L2_DV_BT_STD_DMT, 0) \
363 }
364 
365 #define V4L2_DV_BT_DMT_800X600P72 { \
366 	.type = V4L2_DV_BT_656_1120, \
367 	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
368 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
369 		50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
370 		V4L2_DV_BT_STD_DMT, 0) \
371 }
372 
373 #define V4L2_DV_BT_DMT_800X600P75 { \
374 	.type = V4L2_DV_BT_656_1120, \
375 	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
376 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
377 		49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
378 		V4L2_DV_BT_STD_DMT, 0) \
379 }
380 
381 #define V4L2_DV_BT_DMT_800X600P85 { \
382 	.type = V4L2_DV_BT_656_1120, \
383 	V4L2_INIT_BT_TIMINGS(800, 600, 0, \
384 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
385 		56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
386 		V4L2_DV_BT_STD_DMT, 0) \
387 }
388 
389 #define V4L2_DV_BT_DMT_800X600P120_RB { \
390 	.type = V4L2_DV_BT_656_1120, \
391 	V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
392 		73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
393 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
394 		V4L2_DV_FL_REDUCED_BLANKING) \
395 }
396 
397 #define V4L2_DV_BT_DMT_848X480P60 { \
398 	.type = V4L2_DV_BT_656_1120, \
399 	V4L2_INIT_BT_TIMINGS(848, 480, 0, \
400 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
401 		33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
402 		V4L2_DV_BT_STD_DMT, 0) \
403 }
404 
405 #define V4L2_DV_BT_DMT_1024X768I43 { \
406 	.type = V4L2_DV_BT_656_1120, \
407 	V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
408 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
409 		44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
410 		V4L2_DV_BT_STD_DMT, 0) \
411 }
412 
413 /* XGA resolutions */
414 #define V4L2_DV_BT_DMT_1024X768P60 { \
415 	.type = V4L2_DV_BT_656_1120, \
416 	V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
417 		65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
418 		V4L2_DV_BT_STD_DMT, 0) \
419 }
420 
421 #define V4L2_DV_BT_DMT_1024X768P70 { \
422 	.type = V4L2_DV_BT_656_1120, \
423 	V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
424 		75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
425 		V4L2_DV_BT_STD_DMT, 0) \
426 }
427 
428 #define V4L2_DV_BT_DMT_1024X768P75 { \
429 	.type = V4L2_DV_BT_656_1120, \
430 	V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
431 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
432 		78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
433 		V4L2_DV_BT_STD_DMT, 0) \
434 }
435 
436 #define V4L2_DV_BT_DMT_1024X768P85 { \
437 	.type = V4L2_DV_BT_656_1120, \
438 	V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
439 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
440 		94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
441 		V4L2_DV_BT_STD_DMT, 0) \
442 }
443 
444 #define V4L2_DV_BT_DMT_1024X768P120_RB { \
445 	.type = V4L2_DV_BT_656_1120, \
446 	V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
447 		115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
448 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
449 		V4L2_DV_FL_REDUCED_BLANKING) \
450 }
451 
452 /* XGA+ resolution */
453 #define V4L2_DV_BT_DMT_1152X864P75 { \
454 	.type = V4L2_DV_BT_656_1120, \
455 	V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
456 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
457 		108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
458 		V4L2_DV_BT_STD_DMT, 0) \
459 }
460 
461 #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
462 
463 /* WXGA resolutions */
464 #define V4L2_DV_BT_DMT_1280X768P60_RB { \
465 	.type = V4L2_DV_BT_656_1120, \
466 	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
467 		68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
468 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
469 		V4L2_DV_FL_REDUCED_BLANKING) \
470 }
471 
472 #define V4L2_DV_BT_DMT_1280X768P60 { \
473 	.type = V4L2_DV_BT_656_1120, \
474 	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
475 		79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
476 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
477 }
478 
479 #define V4L2_DV_BT_DMT_1280X768P75 { \
480 	.type = V4L2_DV_BT_656_1120, \
481 	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
482 		102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
483 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
484 }
485 
486 #define V4L2_DV_BT_DMT_1280X768P85 { \
487 	.type = V4L2_DV_BT_656_1120, \
488 	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
489 		117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
490 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
491 }
492 
493 #define V4L2_DV_BT_DMT_1280X768P120_RB { \
494 	.type = V4L2_DV_BT_656_1120, \
495 	V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
496 		140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
497 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
498 		V4L2_DV_FL_REDUCED_BLANKING) \
499 }
500 
501 #define V4L2_DV_BT_DMT_1280X800P60_RB { \
502 	.type = V4L2_DV_BT_656_1120, \
503 	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
504 		71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
505 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
506 		V4L2_DV_FL_REDUCED_BLANKING) \
507 }
508 
509 #define V4L2_DV_BT_DMT_1280X800P60 { \
510 	.type = V4L2_DV_BT_656_1120, \
511 	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
512 		83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
513 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
514 }
515 
516 #define V4L2_DV_BT_DMT_1280X800P75 { \
517 	.type = V4L2_DV_BT_656_1120, \
518 	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
519 		106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
520 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
521 }
522 
523 #define V4L2_DV_BT_DMT_1280X800P85 { \
524 	.type = V4L2_DV_BT_656_1120, \
525 	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
526 		122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
527 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
528 }
529 
530 #define V4L2_DV_BT_DMT_1280X800P120_RB { \
531 	.type = V4L2_DV_BT_656_1120, \
532 	V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
533 		146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
534 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
535 		V4L2_DV_FL_REDUCED_BLANKING) \
536 }
537 
538 #define V4L2_DV_BT_DMT_1280X960P60 { \
539 	.type = V4L2_DV_BT_656_1120, \
540 	V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
541 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
542 		108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
543 		V4L2_DV_BT_STD_DMT, 0) \
544 }
545 
546 #define V4L2_DV_BT_DMT_1280X960P85 { \
547 	.type = V4L2_DV_BT_656_1120, \
548 	V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
549 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
550 		148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
551 		V4L2_DV_BT_STD_DMT, 0) \
552 }
553 
554 #define V4L2_DV_BT_DMT_1280X960P120_RB { \
555 	.type = V4L2_DV_BT_656_1120, \
556 	V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
557 		175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
558 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
559 		V4L2_DV_FL_REDUCED_BLANKING) \
560 }
561 
562 /* SXGA resolutions */
563 #define V4L2_DV_BT_DMT_1280X1024P60 { \
564 	.type = V4L2_DV_BT_656_1120, \
565 	V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
566 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
567 		108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
568 		V4L2_DV_BT_STD_DMT, 0) \
569 }
570 
571 #define V4L2_DV_BT_DMT_1280X1024P75 { \
572 	.type = V4L2_DV_BT_656_1120, \
573 	V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
574 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
575 		135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
576 		V4L2_DV_BT_STD_DMT, 0) \
577 }
578 
579 #define V4L2_DV_BT_DMT_1280X1024P85 { \
580 	.type = V4L2_DV_BT_656_1120, \
581 	V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
582 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
583 		157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
584 		V4L2_DV_BT_STD_DMT, 0) \
585 }
586 
587 #define V4L2_DV_BT_DMT_1280X1024P120_RB { \
588 	.type = V4L2_DV_BT_656_1120, \
589 	V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
590 		187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
591 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
592 		V4L2_DV_FL_REDUCED_BLANKING) \
593 }
594 
595 #define V4L2_DV_BT_DMT_1360X768P60 { \
596 	.type = V4L2_DV_BT_656_1120, \
597 	V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
598 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
599 		85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
600 		V4L2_DV_BT_STD_DMT, 0) \
601 }
602 
603 #define V4L2_DV_BT_DMT_1360X768P120_RB { \
604 	.type = V4L2_DV_BT_656_1120, \
605 	V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
606 		148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
607 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
608 		V4L2_DV_FL_REDUCED_BLANKING) \
609 }
610 
611 #define V4L2_DV_BT_DMT_1366X768P60 { \
612 	.type = V4L2_DV_BT_656_1120, \
613 	V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
614 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
615 		85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
616 		V4L2_DV_BT_STD_DMT, 0) \
617 }
618 
619 #define V4L2_DV_BT_DMT_1366X768P60_RB { \
620 	.type = V4L2_DV_BT_656_1120, \
621 	V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
622 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
623 		72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
624 		V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
625 }
626 
627 /* SXGA+ resolutions */
628 #define V4L2_DV_BT_DMT_1400X1050P60_RB { \
629 	.type = V4L2_DV_BT_656_1120, \
630 	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
631 		101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
632 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
633 		V4L2_DV_FL_REDUCED_BLANKING) \
634 }
635 
636 #define V4L2_DV_BT_DMT_1400X1050P60 { \
637 	.type = V4L2_DV_BT_656_1120, \
638 	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
639 		121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
640 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
641 }
642 
643 #define V4L2_DV_BT_DMT_1400X1050P75 { \
644 	.type = V4L2_DV_BT_656_1120, \
645 	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
646 		156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
647 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
648 }
649 
650 #define V4L2_DV_BT_DMT_1400X1050P85 { \
651 	.type = V4L2_DV_BT_656_1120, \
652 	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
653 		179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
654 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
655 }
656 
657 #define V4L2_DV_BT_DMT_1400X1050P120_RB { \
658 	.type = V4L2_DV_BT_656_1120, \
659 	V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
660 		208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
661 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
662 		V4L2_DV_FL_REDUCED_BLANKING) \
663 }
664 
665 /* WXGA+ resolutions */
666 #define V4L2_DV_BT_DMT_1440X900P60_RB { \
667 	.type = V4L2_DV_BT_656_1120, \
668 	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
669 		88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
670 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
671 		V4L2_DV_FL_REDUCED_BLANKING) \
672 }
673 
674 #define V4L2_DV_BT_DMT_1440X900P60 { \
675 	.type = V4L2_DV_BT_656_1120, \
676 	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
677 		106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
678 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
679 }
680 
681 #define V4L2_DV_BT_DMT_1440X900P75 { \
682 	.type = V4L2_DV_BT_656_1120, \
683 	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
684 		136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
685 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
686 }
687 
688 #define V4L2_DV_BT_DMT_1440X900P85 { \
689 	.type = V4L2_DV_BT_656_1120, \
690 	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
691 		157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
692 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
693 }
694 
695 #define V4L2_DV_BT_DMT_1440X900P120_RB { \
696 	.type = V4L2_DV_BT_656_1120, \
697 	V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
698 		182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
699 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
700 		V4L2_DV_FL_REDUCED_BLANKING) \
701 }
702 
703 #define V4L2_DV_BT_DMT_1600X900P60_RB { \
704 	.type = V4L2_DV_BT_656_1120, \
705 	V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
706 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
707 		108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
708 		V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
709 }
710 
711 /* UXGA resolutions */
712 #define V4L2_DV_BT_DMT_1600X1200P60 { \
713 	.type = V4L2_DV_BT_656_1120, \
714 	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
715 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
716 		162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
717 		V4L2_DV_BT_STD_DMT, 0) \
718 }
719 
720 #define V4L2_DV_BT_DMT_1600X1200P65 { \
721 	.type = V4L2_DV_BT_656_1120, \
722 	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
723 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
724 		175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
725 		V4L2_DV_BT_STD_DMT, 0) \
726 }
727 
728 #define V4L2_DV_BT_DMT_1600X1200P70 { \
729 	.type = V4L2_DV_BT_656_1120, \
730 	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
731 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
732 		189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
733 		V4L2_DV_BT_STD_DMT, 0) \
734 }
735 
736 #define V4L2_DV_BT_DMT_1600X1200P75 { \
737 	.type = V4L2_DV_BT_656_1120, \
738 	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
739 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
740 		202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
741 		V4L2_DV_BT_STD_DMT, 0) \
742 }
743 
744 #define V4L2_DV_BT_DMT_1600X1200P85 { \
745 	.type = V4L2_DV_BT_656_1120, \
746 	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
747 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
748 		229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
749 		V4L2_DV_BT_STD_DMT, 0) \
750 }
751 
752 #define V4L2_DV_BT_DMT_1600X1200P120_RB { \
753 	.type = V4L2_DV_BT_656_1120, \
754 	V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
755 		268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
756 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
757 		V4L2_DV_FL_REDUCED_BLANKING) \
758 }
759 
760 /* WSXGA+ resolutions */
761 #define V4L2_DV_BT_DMT_1680X1050P60_RB { \
762 	.type = V4L2_DV_BT_656_1120, \
763 	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
764 		119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
765 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
766 		V4L2_DV_FL_REDUCED_BLANKING) \
767 }
768 
769 #define V4L2_DV_BT_DMT_1680X1050P60 { \
770 	.type = V4L2_DV_BT_656_1120, \
771 	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
772 		146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
773 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
774 }
775 
776 #define V4L2_DV_BT_DMT_1680X1050P75 { \
777 	.type = V4L2_DV_BT_656_1120, \
778 	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
779 		187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
780 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
781 }
782 
783 #define V4L2_DV_BT_DMT_1680X1050P85 { \
784 	.type = V4L2_DV_BT_656_1120, \
785 	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
786 		214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
787 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
788 }
789 
790 #define V4L2_DV_BT_DMT_1680X1050P120_RB { \
791 	.type = V4L2_DV_BT_656_1120, \
792 	V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
793 		245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
794 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
795 		V4L2_DV_FL_REDUCED_BLANKING) \
796 }
797 
798 #define V4L2_DV_BT_DMT_1792X1344P60 { \
799 	.type = V4L2_DV_BT_656_1120, \
800 	V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
801 		204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
802 		V4L2_DV_BT_STD_DMT, 0) \
803 }
804 
805 #define V4L2_DV_BT_DMT_1792X1344P75 { \
806 	.type = V4L2_DV_BT_656_1120, \
807 	V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
808 		261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
809 		V4L2_DV_BT_STD_DMT, 0) \
810 }
811 
812 #define V4L2_DV_BT_DMT_1792X1344P120_RB { \
813 	.type = V4L2_DV_BT_656_1120, \
814 	V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
815 		333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
816 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
817 		V4L2_DV_FL_REDUCED_BLANKING) \
818 }
819 
820 #define V4L2_DV_BT_DMT_1856X1392P60 { \
821 	.type = V4L2_DV_BT_656_1120, \
822 	V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
823 		218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
824 		V4L2_DV_BT_STD_DMT, 0) \
825 }
826 
827 #define V4L2_DV_BT_DMT_1856X1392P75 { \
828 	.type = V4L2_DV_BT_656_1120, \
829 	V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
830 		288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
831 		V4L2_DV_BT_STD_DMT, 0) \
832 }
833 
834 #define V4L2_DV_BT_DMT_1856X1392P120_RB { \
835 	.type = V4L2_DV_BT_656_1120, \
836 	V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
837 		356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
838 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
839 		V4L2_DV_FL_REDUCED_BLANKING) \
840 }
841 
842 #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
843 
844 /* WUXGA resolutions */
845 #define V4L2_DV_BT_DMT_1920X1200P60_RB { \
846 	.type = V4L2_DV_BT_656_1120, \
847 	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
848 		154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
849 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
850 		V4L2_DV_FL_REDUCED_BLANKING) \
851 }
852 
853 #define V4L2_DV_BT_DMT_1920X1200P60 { \
854 	.type = V4L2_DV_BT_656_1120, \
855 	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
856 		193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
857 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
858 }
859 
860 #define V4L2_DV_BT_DMT_1920X1200P75 { \
861 	.type = V4L2_DV_BT_656_1120, \
862 	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
863 		245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
864 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
865 }
866 
867 #define V4L2_DV_BT_DMT_1920X1200P85 { \
868 	.type = V4L2_DV_BT_656_1120, \
869 	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
870 		281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
871 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
872 }
873 
874 #define V4L2_DV_BT_DMT_1920X1200P120_RB { \
875 	.type = V4L2_DV_BT_656_1120, \
876 	V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
877 		317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
878 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
879 		V4L2_DV_FL_REDUCED_BLANKING) \
880 }
881 
882 #define V4L2_DV_BT_DMT_1920X1440P60 { \
883 	.type = V4L2_DV_BT_656_1120, \
884 	V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
885 		234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
886 		V4L2_DV_BT_STD_DMT, 0) \
887 }
888 
889 #define V4L2_DV_BT_DMT_1920X1440P75 { \
890 	.type = V4L2_DV_BT_656_1120, \
891 	V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
892 		297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
893 		V4L2_DV_BT_STD_DMT, 0) \
894 }
895 
896 #define V4L2_DV_BT_DMT_1920X1440P120_RB { \
897 	.type = V4L2_DV_BT_656_1120, \
898 	V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
899 		380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
900 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
901 		V4L2_DV_FL_REDUCED_BLANKING) \
902 }
903 
904 #define V4L2_DV_BT_DMT_2048X1152P60_RB { \
905 	.type = V4L2_DV_BT_656_1120, \
906 	V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
907 		V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
908 		162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
909 		V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
910 }
911 
912 /* WQXGA resolutions */
913 #define V4L2_DV_BT_DMT_2560X1600P60_RB { \
914 	.type = V4L2_DV_BT_656_1120, \
915 	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
916 		268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
917 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
918 		V4L2_DV_FL_REDUCED_BLANKING) \
919 }
920 
921 #define V4L2_DV_BT_DMT_2560X1600P60 { \
922 	.type = V4L2_DV_BT_656_1120, \
923 	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
924 		348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
925 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
926 }
927 
928 #define V4L2_DV_BT_DMT_2560X1600P75 { \
929 	.type = V4L2_DV_BT_656_1120, \
930 	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
931 		443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
932 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
933 }
934 
935 #define V4L2_DV_BT_DMT_2560X1600P85 { \
936 	.type = V4L2_DV_BT_656_1120, \
937 	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
938 		505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
939 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
940 }
941 
942 #define V4L2_DV_BT_DMT_2560X1600P120_RB { \
943 	.type = V4L2_DV_BT_656_1120, \
944 	V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
945 		552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
946 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
947 		V4L2_DV_FL_REDUCED_BLANKING) \
948 }
949 
950 /* 4K resolutions */
951 #define V4L2_DV_BT_DMT_4096X2160P60_RB { \
952 	.type = V4L2_DV_BT_656_1120, \
953 	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
954 		556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
955 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
956 		V4L2_DV_FL_REDUCED_BLANKING) \
957 }
958 
959 #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \
960 	.type = V4L2_DV_BT_656_1120, \
961 	V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
962 		556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
963 		V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
964 		V4L2_DV_FL_REDUCED_BLANKING) \
965 }
966 
967 /* SDI timings definitions */
968 
969 /* SMPTE-125M */
970 #define V4L2_DV_BT_SDI_720X487I60 { \
971 	.type = V4L2_DV_BT_656_1120, \
972 	V4L2_INIT_BT_TIMINGS(720, 487, 1, \
973 		V4L2_DV_HSYNC_POS_POL, \
974 		13500000, 16, 121, 0, 0, 19, 0, 0, 19, 0, \
975 		V4L2_DV_BT_STD_SDI, \
976 		V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) \
977 }
978 
979 #endif
980