1 /* 2 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: This file contains definitions of Data Path configuration. 22 */ 23 24 #ifndef _CFG_DP_H_ 25 #define _CFG_DP_H_ 26 27 #include "cfg_define.h" 28 #include "wlan_init_cfg.h" 29 30 #define WLAN_CFG_MAX_CLIENTS 64 31 #define WLAN_CFG_MAX_CLIENTS_MIN 8 32 #define WLAN_CFG_MAX_CLIENTS_MAX 64 33 34 /* Change this to a lower value to enforce scattered idle list mode */ 35 #define WLAN_CFG_MAX_ALLOC_SIZE 0x200000 36 #define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000 37 #define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000 38 39 #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \ 40 defined(QCA_LL_PDEV_TX_FLOW_CONTROL) 41 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10 42 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15 43 #else 44 #define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0 45 #define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0 46 #endif 47 48 #define WLAN_CFG_PER_PDEV_TX_RING_MIN 0 49 #define WLAN_CFG_PER_PDEV_TX_RING_MAX 1 50 51 #ifdef IPA_OFFLOAD 52 /* Size of TCL TX Ring */ 53 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 54 #define WLAN_CFG_TX_RING_SIZE 2048 55 #else 56 #define WLAN_CFG_TX_RING_SIZE 1024 57 #endif 58 59 #define WLAN_CFG_IPA_TX_RING_SIZE_MIN 512 60 #define WLAN_CFG_IPA_TX_RING_SIZE 1024 61 #define WLAN_CFG_IPA_TX_RING_SIZE_MAX 0x80000 62 63 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN 512 64 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE 1024 65 #define WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX 0x80000 66 67 #ifdef IPA_WDI3_TX_TWO_PIPES 68 #ifdef WLAN_MEMORY_OPT 69 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 128 70 #else 71 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN 512 72 #endif 73 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE 1024 74 #define WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX 0x80000 75 76 #ifdef WLAN_MEMORY_OPT 77 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 128 78 #else 79 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN 512 80 #endif 81 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE 1024 82 #define WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX 0x80000 83 #endif 84 85 #define WLAN_CFG_PER_PDEV_TX_RING 0 86 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048 87 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000 88 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024 89 #else 90 #define WLAN_CFG_TX_RING_SIZE 512 91 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 92 #define WLAN_CFG_PER_PDEV_TX_RING 1 93 #else 94 #define WLAN_CFG_PER_PDEV_TX_RING 0 95 #endif 96 #define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0 97 #define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0 98 #define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0 99 #endif /* IPA_OFFLOAD */ 100 101 #define WLAN_CFG_TIME_CONTROL_BP 3000 102 103 #if defined(RX_DATA_BUFFER_SIZE) 104 #define WLAN_CFG_RX_BUFFER_SIZE RX_DATA_BUFFER_SIZE 105 #else 106 #define WLAN_CFG_RX_BUFFER_SIZE 2048 107 #endif 108 109 #define WLAN_CFG_QREF_CONTROL_SIZE 0 110 111 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 112 #define WLAN_CFG_PER_PDEV_RX_RING 0 113 #define WLAN_CFG_PER_PDEV_LMAC_RING 0 114 #define WLAN_LRO_ENABLE 0 115 #if defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_WCN6450) 116 #define WLAN_CFG_MAC_PER_TARGET 1 117 #else 118 #define WLAN_CFG_MAC_PER_TARGET 2 119 #endif 120 121 #if defined(TX_TO_NPEERS_INC_TX_DESCS) 122 #define WLAN_CFG_TX_COMP_RING_SIZE 4096 123 124 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 125 #define WLAN_CFG_NUM_TX_DESC 4096 126 #define WLAN_CFG_NUM_TX_EXT_DESC 4096 127 #else 128 #define WLAN_CFG_TX_COMP_RING_SIZE 1024 129 130 /* Tx Descriptor and Tx Extension Descriptor pool sizes */ 131 #define WLAN_CFG_NUM_TX_DESC 1024 132 #define WLAN_CFG_NUM_TX_EXT_DESC 1024 133 #endif 134 135 /* Interrupt Mitigation - Batch threshold in terms of number of frames */ 136 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1 137 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1 138 139 /* Interrupt Mitigation - Timer threshold in us */ 140 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8 141 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8 142 143 #ifdef WLAN_DP_PER_RING_TYPE_CONFIG 144 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX \ 145 WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 146 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX \ 147 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 148 #else 149 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1 150 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8 151 #endif 152 #endif /* WLAN_MAX_PDEVS */ 153 154 #define WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST 1 155 #define WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST 256 156 157 #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL 0 158 #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL 30 159 160 #ifdef NBUF_MEMORY_DEBUG 161 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0xFFFF 162 #else 163 #define WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 0x1FFFF 164 #endif 165 166 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD \ 167 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 168 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN 0 169 #define WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX 0x200000 170 171 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD \ 172 WLAN_CFG_RX_PENDING_THRESHOLD_DEFAULT 173 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN 100 174 #define WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX 0x200000 175 176 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256 177 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512 178 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING 0 179 180 #define WLAN_CFG_PER_PDEV_RX_RING_MIN 0 181 #define WLAN_CFG_PER_PDEV_RX_RING_MAX 0 182 183 #define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0 184 #define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1 185 186 #define WLAN_CFG_TX_RING_SIZE_MIN 512 187 #define WLAN_CFG_TX_RING_SIZE_MAX 0x80000 188 189 #define WLAN_CFG_TIME_CONTROL_BP_MIN 3000 190 #define WLAN_CFG_TIME_CONTROL_BP_MAX 1800000 191 /*MTU size of ethernet is 1500*/ 192 #define WLAN_CFG_RX_BUFFER_SIZE_MIN 1536 193 #define WLAN_CFG_RX_BUFFER_SIZE_MAX 4096 194 195 #define WLAN_CFG_QREF_CONTROL_SIZE_MIN 0 196 #define WLAN_CFG_QREF_CONTROL_SIZE_MAX 4000 197 198 #define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512 199 #define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000 200 201 #define WLAN_CFG_NUM_TX_DESC_MIN 16 202 #define WLAN_CFG_NUM_TX_DESC_MAX 0x10000 203 204 #define WLAN_CFG_NUM_TX_SPL_DESC 1024 205 #define WLAN_CFG_NUM_TX_SPL_DESC_MIN 0 206 #define WLAN_CFG_NUM_TX_SPL_DESC_MAX 0x1000 207 208 #define WLAN_CFG_NUM_TX_EXT_DESC_MIN 16 209 #define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000 210 211 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1 212 #define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256 213 214 #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MIN 0 215 #define WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MAX 1024 216 217 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 0 218 #define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128 219 220 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1 221 #define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128 222 223 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1 224 #define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128 225 226 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1 227 #define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1 228 229 #define WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST_MIN 1 230 #define WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST_MAX 64 231 232 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8 233 #define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 1000 234 235 #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MIN 8 236 #define WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MAX 1000 237 238 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8 239 #define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500 240 241 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8 242 #define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000 243 244 #define WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST_MIN 256 245 #define WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST_MAX 1000 246 247 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8 248 #define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 512 249 250 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8 251 #define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500 252 253 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000 254 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000 255 #define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000 256 257 #ifdef QCA_LL_TX_FLOW_CONTROL_V2 258 259 /* Per vdev pools */ 260 #define WLAN_CFG_NUM_TX_DESC_POOL 3 261 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 262 263 #else /* QCA_LL_TX_FLOW_CONTROL_V2 */ 264 265 #ifdef TX_PER_PDEV_DESC_POOL 266 #define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT 267 #define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT 268 269 #else /* TX_PER_PDEV_DESC_POOL */ 270 271 #define WLAN_CFG_NUM_TX_DESC_POOL 3 272 #define WLAN_CFG_NUM_TXEXT_DESC_POOL 3 273 274 #endif /* TX_PER_PDEV_DESC_POOL */ 275 #endif /* QCA_LL_TX_FLOW_CONTROL_V2 */ 276 277 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1 278 #define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4 279 280 #define WLAN_CFG_HTT_PKT_TYPE 2 281 #define WLAN_CFG_HTT_PKT_TYPE_MIN 2 282 #define WLAN_CFG_HTT_PKT_TYPE_MAX 2 283 284 #define WLAN_CFG_MAX_PEER_ID 64 285 #define WLAN_CFG_MAX_PEER_ID_MIN 64 286 #define WLAN_CFG_MAX_PEER_ID_MAX 64 287 288 #define WLAN_CFG_RX_DEFRAG_TIMEOUT 100 289 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100 290 #define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100 291 292 #define WLAN_CFG_NUM_TCL_DATA_RINGS 3 293 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 1 294 #define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX MAX_TCL_DATA_RINGS 295 296 #define WLAN_CFG_NUM_TX_COMP_RINGS WLAN_CFG_NUM_TCL_DATA_RINGS 297 #define WLAN_CFG_NUM_TX_COMP_RINGS_MIN WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 298 #define WLAN_CFG_NUM_TX_COMP_RINGS_MAX WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 299 300 #if defined(CONFIG_BERYLLIUM) 301 #define WLAN_CFG_NUM_REO_DEST_RING 8 302 #else 303 #define WLAN_CFG_NUM_REO_DEST_RING 4 304 #endif 305 #define WLAN_CFG_NUM_REO_DEST_RING_MIN 4 306 #define WLAN_CFG_NUM_REO_DEST_RING_MAX MAX_REO_DEST_RINGS 307 308 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS 2 309 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN 1 310 #define WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX 3 311 312 #define WLAN_CFG_NSS_NUM_REO_DEST_RING 2 313 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN 1 314 #define WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX 3 315 316 #define WLAN_CFG_WBM_RELEASE_RING_SIZE 1024 317 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64 318 #define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 1024 319 320 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE 512 321 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN 32 322 #define WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX 512 323 324 #define WLAN_CFG_TCL_STATUS_RING_SIZE 32 325 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32 326 #define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32 327 328 #if defined(QCA_WIFI_QCA6290) 329 #define WLAN_CFG_REO_DST_RING_SIZE 1024 330 #else 331 #define WLAN_CFG_REO_DST_RING_SIZE 2048 332 #endif 333 334 #define WLAN_CFG_REO_DST_RING_SIZE_MIN 8 335 #define WLAN_CFG_REO_DST_RING_SIZE_MAX 8192 336 337 #define WLAN_CFG_REO_REINJECT_RING_SIZE 128 338 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32 339 #define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 128 340 341 #define WLAN_CFG_RX_RELEASE_RING_SIZE 1024 342 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8 343 #if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \ 344 defined(QCA_WIFI_QCA6750) || defined(QCA_WIFI_KIWI) 345 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024 346 #else 347 #define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 32768 348 #endif 349 350 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE 256 351 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128 352 #define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 512 353 354 #define WLAN_CFG_REO_CMD_RING_SIZE 128 355 #define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64 356 #define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128 357 358 #define WLAN_CFG_REO_STATUS_RING_SIZE 256 359 #define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128 360 #define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048 361 362 #define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024 363 #ifdef WLAN_MEMORY_OPT 364 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 128 365 #else 366 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024 367 #endif 368 #define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 8192 369 370 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096 371 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16 372 #define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 16384 373 374 #define WLAN_CFG_TX_DESC_LIMIT_0 0 375 #define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096 376 #define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768 377 378 #define WLAN_CFG_TX_DESC_LIMIT_1 0 379 #define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096 380 #define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768 381 382 #define WLAN_CFG_TX_DESC_LIMIT_2 0 383 #define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096 384 #define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768 385 386 #define WLAN_CFG_TX_DEVICE_LIMIT 65536 387 #define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384 388 #define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536 389 390 #define WLAN_CFG_TX_SPL_DEVICE_LIMIT 1024 391 #define WLAN_CFG_TX_SPL_DEVICE_LIMIT_MIN 0 392 #define WLAN_CFG_TX_SPL_DEVICE_LIMIT_MAX 4096 393 394 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024 395 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128 396 #define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024 397 398 #define WLAN_CFG_TX_DESC_GLOBAL_COUNT 0xC000 399 #define WLAN_CFG_TX_DESC_GLOBAL_COUNT_MIN 0x8000 400 #define WLAN_CFG_TX_DESC_GLOBAL_COUNT_MAX 0x60000 401 402 #define WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT 0x400 403 #define WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MIN 0x400 404 #define WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MAX 0x1000 405 406 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096 407 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16 408 #define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192 409 410 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE 4096 411 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN 16 412 #define WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX 8192 413 414 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048 415 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48 416 #define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192 417 418 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE 2048 419 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN 48 420 #define WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX 8192 421 422 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024 423 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16 424 #define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192 425 426 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096 427 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096 428 #define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384 429 430 #define WLAN_CFG_SW2RXDMA_LINK_RING_SIZE 1024 431 #define WLAN_CFG_SW2RXDMA_LINK_RING_SIZE_MIN 256 432 #define WLAN_CFG_SW2RXDMA_LINK_RING_SIZE_MAX 4096 433 434 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024 435 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024 436 #define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192 437 438 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32 439 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0 440 #define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256 441 442 /* 443 * Allocate as many RX descriptors as buffers in the SW2RXDMA 444 * ring. This value may need to be tuned later. 445 */ 446 #if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1) 447 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 448 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 449 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1 450 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 451 #ifdef WLAN_MEMORY_OPT 452 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 128 453 #else 454 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 455 #endif 456 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 457 458 /* 459 * For low memory AP cases using 1 will reduce the rx descriptors memory req 460 */ 461 #elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG) 462 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1 463 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 464 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 465 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 4096 466 #ifdef WLAN_MEMORY_OPT 467 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 128 468 #else 469 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 1024 470 #endif 471 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 472 473 /* 474 * AP use cases need to allocate more RX Descriptors than the number of 475 * entries available in the SW2RXDMA buffer replenish ring. This is to account 476 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a 477 * multiplication factor of 3, to allocate three times as many RX descriptors 478 * as RX buffers. 479 */ 480 #else 481 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3 482 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1 483 #define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3 484 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE 12288 485 #ifdef WLAN_MEMORY_OPT 486 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 128 487 #else 488 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN 4096 489 #endif 490 #define WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX 16384 491 #endif 492 493 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384 494 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1 495 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384 496 #define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT 128 497 498 #define WLAN_CFG_PKTLOG_BUFFER_SIZE 10 499 #define WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE 1 500 #define WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE 10 501 502 #ifdef IPA_OFFLOAD 503 #define WLAN_CFG_NUM_REO_RINGS_MAP 0x7 504 #else 505 #define WLAN_CFG_NUM_REO_RINGS_MAP 0xF 506 #endif 507 #define WLAN_CFG_NUM_REO_RINGS_MAP_MIN 0x1 508 #if defined(CONFIG_BERYLLIUM) 509 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xFF 510 #else 511 #define WLAN_CFG_NUM_REO_RINGS_MAP_MAX 0xF 512 #endif 513 514 #define WLAN_CFG_RADIO_0_DEFAULT_REO 0x1 515 #define WLAN_CFG_RADIO_1_DEFAULT_REO 0x2 516 #define WLAN_CFG_RADIO_2_DEFAULT_REO 0x3 517 518 #define WLAN_CFG_RADIO_DEFAULT_REO_MIN 0x1 519 #define WLAN_CFG_RADIO_DEFAULT_REO_MAX 0x4 520 521 #define WLAN_CFG_REO2PPE_RING_SIZE 16384 522 #define WLAN_CFG_REO2PPE_RING_SIZE_MIN 64 523 #define WLAN_CFG_REO2PPE_RING_SIZE_MAX 16384 524 525 #define WLAN_CFG_PPE2TCL_RING_SIZE 8192 526 #define WLAN_CFG_PPE2TCL_RING_SIZE_MIN 64 527 #define WLAN_CFG_PPE2TCL_RING_SIZE_MAX 32768 528 529 #define WLAN_CFG_PPE_RELEASE_RING_SIZE 1024 530 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MIN 64 531 #define WLAN_CFG_PPE_RELEASE_RING_SIZE_MAX 1024 532 533 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 534 #define WLAN_CFG_MLO_RX_RING_MAP 0x7 535 #define WLAN_CFG_MLO_RX_RING_MAP_MIN 0x0 536 #define WLAN_CFG_MLO_RX_RING_MAP_MAX 0xFF 537 #endif 538 539 #define WLAN_CFG_TX_CAPT_MAX_MEM_MIN 0 540 #define WLAN_CFG_TX_CAPT_MAX_MEM_MAX 512 541 #define WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT 0 542 543 #define CFG_DP_MPDU_RETRY_THRESHOLD_MIN 0 544 #define CFG_DP_MPDU_RETRY_THRESHOLD_MAX 255 545 #define CFG_DP_MPDU_RETRY_THRESHOLD 0 546 547 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR 0 548 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN 0 549 #define WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX 4 550 551 #define CFG_DP_PPEDS_WIFI_SOC_CFG_NONE 0 552 #define CFG_DP_PPEDS_WIFI_SOC_CFG_ALL 0xFF 553 #define CFG_DP_PPEDS_WIFI_SOC_CFG_DEFAULT 0xFF 554 555 #ifdef CONFIG_SAWF_STATS 556 #define WLAN_CFG_SAWF_STATS 0x0 557 #define WLAN_CFG_SAWF_STATS_MIN 0x0 558 #define WLAN_CFG_SAWF_STATS_MAX 0x7 559 #endif 560 561 #define WLAN_CFG_TX_CAPT_RBM_ID_MIN 0 562 #define WLAN_CFG_TX_CAPT_RBM_ID_MAX 3 563 #define WLAN_CFG_TX_CAPT_0_RBM_DEFAULT 0 564 #define WLAN_CFG_TX_CAPT_1_RBM_DEFAULT 1 565 #define WLAN_CFG_TX_CAPT_2_RBM_DEFAULT 2 566 #define WLAN_CFG_TX_CAPT_3_RBM_DEFAULT 3 567 568 #define WLAN_CFG_DP_AVG_RATE_FILTER_MIN 0 569 #define WLAN_CFG_DP_AVG_RATE_FILTER_MAX 11000 570 #define WLAN_CFG_DP_AVG_RATE_FILTER_DEFAULT 0 571 572 /* 573 * <ini> 574 * "dp_tx_capt_max_mem_mb"- maximum memory used by Tx capture 575 * @Min: 0 576 * @Max: 512 MB 577 * @Default: 0 (disabled) 578 * 579 * This ini entry is used to set a max limit beyond which frames 580 * are dropped by Tx capture. User needs to set a non-zero value 581 * to enable it. 582 * 583 * Usage: External 584 * 585 * </ini> 586 */ 587 #define CFG_DP_TX_CAPT_MAX_MEM_MB \ 588 CFG_INI_UINT("dp_tx_capt_max_mem_mb", \ 589 WLAN_CFG_TX_CAPT_MAX_MEM_MIN, \ 590 WLAN_CFG_TX_CAPT_MAX_MEM_MAX, \ 591 WLAN_CFG_TX_CAPT_MAX_MEM_DEFAULT, \ 592 CFG_VALUE_OR_DEFAULT, "Max Memory (in MB) used by Tx Capture") 593 594 #define CFG_DP_TX_CAPT_RADIO_0_RBM_ID \ 595 CFG_INI_UINT("dp_tx_capt_pdev_0_rbm_id", \ 596 WLAN_CFG_TX_CAPT_RBM_ID_MIN, \ 597 WLAN_CFG_TX_CAPT_RBM_ID_MAX, \ 598 WLAN_CFG_TX_CAPT_0_RBM_DEFAULT, \ 599 CFG_VALUE_OR_DEFAULT, "RBM_ID used by pdev 0 Tx capture") 600 601 #define CFG_DP_TX_CAPT_RADIO_1_RBM_ID \ 602 CFG_INI_UINT("dp_tx_capt_pdev_1_rbm_id", \ 603 WLAN_CFG_TX_CAPT_RBM_ID_MIN, \ 604 WLAN_CFG_TX_CAPT_RBM_ID_MAX, \ 605 WLAN_CFG_TX_CAPT_1_RBM_DEFAULT, \ 606 CFG_VALUE_OR_DEFAULT, "RBM_ID used by pdev 1 Tx capture") 607 608 #define CFG_DP_TX_CAPT_RADIO_2_RBM_ID \ 609 CFG_INI_UINT("dp_tx_capt_pdev_2_rbm_id", \ 610 WLAN_CFG_TX_CAPT_RBM_ID_MIN, \ 611 WLAN_CFG_TX_CAPT_RBM_ID_MAX, \ 612 WLAN_CFG_TX_CAPT_2_RBM_DEFAULT, \ 613 CFG_VALUE_OR_DEFAULT, "RBM_ID used by pdev 2 Tx capture") 614 615 #define CFG_DP_TX_CAPT_RADIO_3_RBM_ID \ 616 CFG_INI_UINT("dp_tx_capt_pdev_3_rbm_id", \ 617 WLAN_CFG_TX_CAPT_RBM_ID_MIN, \ 618 WLAN_CFG_TX_CAPT_RBM_ID_MAX, \ 619 WLAN_CFG_TX_CAPT_3_RBM_DEFAULT, \ 620 CFG_VALUE_OR_DEFAULT, "RBM_ID used by pdev 3 Tx capture") 621 622 /* DP INI Declarations */ 623 #define CFG_DP_HTT_PACKET_TYPE \ 624 CFG_INI_UINT("dp_htt_packet_type", \ 625 WLAN_CFG_HTT_PKT_TYPE_MIN, \ 626 WLAN_CFG_HTT_PKT_TYPE_MAX, \ 627 WLAN_CFG_HTT_PKT_TYPE, \ 628 CFG_VALUE_OR_DEFAULT, "DP HTT packet type") 629 630 #define CFG_DP_INT_BATCH_THRESHOLD_OTHER \ 631 CFG_INI_UINT("dp_int_batch_threshold_other", \ 632 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \ 633 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \ 634 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \ 635 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other") 636 637 #define CFG_DP_INT_BATCH_THRESHOLD_MON_DEST \ 638 CFG_INI_UINT("dp_int_batch_threshold_mon_dest", \ 639 WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST_MIN, \ 640 WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST_MAX, \ 641 WLAN_CFG_INT_BATCH_THRESHOLD_MON_DEST, \ 642 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold mon_dest") 643 644 #define CFG_DP_INT_BATCH_THRESHOLD_RX \ 645 CFG_INI_UINT("dp_int_batch_threshold_rx", \ 646 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \ 647 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \ 648 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \ 649 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx") 650 651 #define CFG_DP_INT_BATCH_THRESHOLD_TX \ 652 CFG_INI_UINT("dp_int_batch_threshold_tx", \ 653 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \ 654 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \ 655 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \ 656 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx") 657 658 #define CFG_DP_INT_BATCH_THRESHOLD_PPE2TCL \ 659 CFG_INI_UINT("dp_int_batch_threshold_ppe2tcl", \ 660 WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MIN, \ 661 WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL_MAX, \ 662 WLAN_CFG_INT_BATCH_THRESHOLD_PPE2TCL, \ 663 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold ppe2tcl") 664 665 #define CFG_DP_INT_TIMER_THRESHOLD_PPE2TCL \ 666 CFG_INI_UINT("dp_int_timer_threshold_ppe2tcl", \ 667 WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MIN, \ 668 WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL_MAX, \ 669 WLAN_CFG_INT_TIMER_THRESHOLD_PPE2TCL, \ 670 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold ppe2tcl") 671 672 #define CFG_DP_INT_TIMER_THRESHOLD_OTHER \ 673 CFG_INI_UINT("dp_int_timer_threshold_other", \ 674 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \ 675 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \ 676 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \ 677 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other") 678 679 #define CFG_DP_INT_TIMER_THRESHOLD_MON_DEST \ 680 CFG_INI_UINT("dp_int_timer_threshold_mon_dest", \ 681 WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST_MIN, \ 682 WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST_MAX, \ 683 WLAN_CFG_INT_TIMER_THRESHOLD_MON_DEST, \ 684 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold mon dest") 685 686 #define CFG_DP_INT_TIMER_THRESHOLD_RX \ 687 CFG_INI_UINT("dp_int_timer_threshold_rx", \ 688 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \ 689 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \ 690 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \ 691 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx") 692 693 #define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \ 694 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \ 695 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \ 696 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \ 697 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \ 698 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring") 699 700 #define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \ 701 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \ 702 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \ 703 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \ 704 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \ 705 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring") 706 707 #define CFG_DP_INT_TIMER_THRESHOLD_TX \ 708 CFG_INI_UINT("dp_int_timer_threshold_tx", \ 709 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \ 710 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \ 711 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \ 712 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx") 713 714 #define CFG_DP_MAX_ALLOC_SIZE \ 715 CFG_INI_UINT("dp_max_alloc_size", \ 716 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \ 717 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \ 718 WLAN_CFG_MAX_ALLOC_SIZE, \ 719 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size") 720 721 #define CFG_DP_MAX_CLIENTS \ 722 CFG_INI_UINT("dp_max_clients", \ 723 WLAN_CFG_MAX_CLIENTS_MIN, \ 724 WLAN_CFG_MAX_CLIENTS_MAX, \ 725 WLAN_CFG_MAX_CLIENTS, \ 726 CFG_VALUE_OR_DEFAULT, "DP Max Clients") 727 728 #define CFG_DP_MAX_PEER_ID \ 729 CFG_INI_UINT("dp_max_peer_id", \ 730 WLAN_CFG_MAX_PEER_ID_MIN, \ 731 WLAN_CFG_MAX_PEER_ID_MAX, \ 732 WLAN_CFG_MAX_PEER_ID, \ 733 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID") 734 735 #define CFG_DP_REO_DEST_RINGS \ 736 CFG_INI_UINT("dp_reo_dest_rings", \ 737 WLAN_CFG_NUM_REO_DEST_RING_MIN, \ 738 WLAN_CFG_NUM_REO_DEST_RING_MAX, \ 739 WLAN_CFG_NUM_REO_DEST_RING, \ 740 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings") 741 742 #define CFG_DP_TX_COMP_RINGS \ 743 CFG_INI_UINT("dp_tx_comp_rings", \ 744 WLAN_CFG_NUM_TX_COMP_RINGS_MIN, \ 745 WLAN_CFG_NUM_TX_COMP_RINGS_MAX, \ 746 WLAN_CFG_NUM_TX_COMP_RINGS, \ 747 CFG_VALUE_OR_DEFAULT, "DP Tx Comp Rings") 748 749 #define CFG_DP_TCL_DATA_RINGS \ 750 CFG_INI_UINT("dp_tcl_data_rings", \ 751 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \ 752 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \ 753 WLAN_CFG_NUM_TCL_DATA_RINGS, \ 754 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings") 755 756 #define CFG_DP_NSS_REO_DEST_RINGS \ 757 CFG_INI_UINT("dp_nss_reo_dest_rings", \ 758 WLAN_CFG_NSS_NUM_REO_DEST_RING_MIN, \ 759 WLAN_CFG_NSS_NUM_REO_DEST_RING_MAX, \ 760 WLAN_CFG_NSS_NUM_REO_DEST_RING, \ 761 CFG_VALUE_OR_DEFAULT, "DP NSS REO Destination Rings") 762 763 #define CFG_DP_NSS_TCL_DATA_RINGS \ 764 CFG_INI_UINT("dp_nss_tcl_data_rings", \ 765 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MIN, \ 766 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS_MAX, \ 767 WLAN_CFG_NSS_NUM_TCL_DATA_RINGS, \ 768 CFG_VALUE_OR_DEFAULT, "DP NSS TCL Data Rings") 769 770 #define CFG_DP_TX_DESC \ 771 CFG_INI_UINT("dp_tx_desc", \ 772 WLAN_CFG_NUM_TX_DESC_MIN, \ 773 WLAN_CFG_NUM_TX_DESC_MAX, \ 774 WLAN_CFG_NUM_TX_DESC, \ 775 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors") 776 777 #define CFG_DP_TX_DESC_POOL_3 \ 778 CFG_INI_UINT("dp_tx_desc_pool_3", \ 779 WLAN_CFG_NUM_TX_DESC_MIN, \ 780 WLAN_CFG_NUM_TX_DESC_MAX, \ 781 WLAN_CFG_NUM_TX_DESC, \ 782 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptor of 3rd pool") 783 784 #define CFG_DP_TX_SPL_DESC \ 785 CFG_INI_UINT("dp_tx_spl_desc", \ 786 WLAN_CFG_NUM_TX_SPL_DESC_MIN, \ 787 WLAN_CFG_NUM_TX_SPL_DESC_MAX, \ 788 WLAN_CFG_NUM_TX_SPL_DESC, \ 789 CFG_VALUE_OR_DEFAULT, "DP Tx Special Descriptors") 790 791 #define CFG_DP_TX_EXT_DESC \ 792 CFG_INI_UINT("dp_tx_ext_desc", \ 793 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \ 794 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \ 795 WLAN_CFG_NUM_TX_EXT_DESC, \ 796 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors") 797 798 #define CFG_DP_TX_EXT_DESC_POOLS \ 799 CFG_INI_UINT("dp_tx_ext_desc_pool", \ 800 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \ 801 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \ 802 WLAN_CFG_NUM_TXEXT_DESC_POOL, \ 803 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool") 804 805 #define CFG_DP_PDEV_RX_RING \ 806 CFG_INI_UINT("dp_pdev_rx_ring", \ 807 WLAN_CFG_PER_PDEV_RX_RING_MIN, \ 808 WLAN_CFG_PER_PDEV_RX_RING_MAX, \ 809 WLAN_CFG_PER_PDEV_RX_RING, \ 810 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring") 811 812 #define CFG_DP_PDEV_TX_RING \ 813 CFG_INI_UINT("dp_pdev_tx_ring", \ 814 WLAN_CFG_PER_PDEV_TX_RING_MIN, \ 815 WLAN_CFG_PER_PDEV_TX_RING_MAX, \ 816 WLAN_CFG_PER_PDEV_TX_RING, \ 817 CFG_VALUE_OR_DEFAULT, \ 818 "DP PDEV Tx Ring") 819 820 #define CFG_DP_RX_DEFRAG_TIMEOUT \ 821 CFG_INI_UINT("dp_rx_defrag_timeout", \ 822 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \ 823 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \ 824 WLAN_CFG_RX_DEFRAG_TIMEOUT, \ 825 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout") 826 827 #define CFG_DP_TX_COMPL_RING_SIZE \ 828 CFG_INI_UINT("dp_tx_compl_ring_size", \ 829 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \ 830 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \ 831 WLAN_CFG_TX_COMP_RING_SIZE, \ 832 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size") 833 834 #define CFG_DP_TX_RING_SIZE \ 835 CFG_INI_UINT("dp_tx_ring_size", \ 836 WLAN_CFG_TX_RING_SIZE_MIN,\ 837 WLAN_CFG_TX_RING_SIZE_MAX,\ 838 WLAN_CFG_TX_RING_SIZE,\ 839 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size") 840 841 #define CFG_DP_NSS_COMP_RING_SIZE \ 842 CFG_INI_UINT("dp_nss_comp_ring_size", \ 843 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \ 844 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \ 845 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \ 846 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size") 847 848 #define CFG_DP_PDEV_LMAC_RING \ 849 CFG_INI_UINT("dp_pdev_lmac_ring", \ 850 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \ 851 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \ 852 WLAN_CFG_PER_PDEV_LMAC_RING, \ 853 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring") 854 855 #define CFG_DP_TIME_CONTROL_BP \ 856 CFG_INI_UINT("dp_time_control_bp", \ 857 WLAN_CFG_TIME_CONTROL_BP_MIN,\ 858 WLAN_CFG_TIME_CONTROL_BP_MAX,\ 859 WLAN_CFG_TIME_CONTROL_BP,\ 860 CFG_VALUE_OR_DEFAULT, "DP time control back pressure") 861 862 #define CFG_DP_RX_BUFFER_SIZE \ 863 CFG_INI_UINT("dp_rx_buffer_size", \ 864 WLAN_CFG_RX_BUFFER_SIZE_MIN,\ 865 WLAN_CFG_RX_BUFFER_SIZE_MAX,\ 866 WLAN_CFG_RX_BUFFER_SIZE,\ 867 CFG_VALUE_OR_DEFAULT, "DP rx buffer size") 868 869 #define CFG_DP_QREF_CONTROL_SIZE \ 870 CFG_INI_UINT("dp_qref_control_size", \ 871 WLAN_CFG_QREF_CONTROL_SIZE_MIN,\ 872 WLAN_CFG_QREF_CONTROL_SIZE_MAX,\ 873 WLAN_CFG_QREF_CONTROL_SIZE,\ 874 CFG_VALUE_OR_DEFAULT, "DP array size for qref debug") 875 876 #ifdef CONFIG_SAWF_STATS 877 #define CFG_DP_SAWF_STATS \ 878 CFG_INI_UINT("dp_sawf_stats", \ 879 WLAN_CFG_SAWF_STATS_MIN,\ 880 WLAN_CFG_SAWF_STATS_MAX,\ 881 WLAN_CFG_SAWF_STATS,\ 882 CFG_VALUE_OR_DEFAULT, "DP sawf stats config") 883 #define CFG_DP_SAWF_STATS_CONFIG CFG(CFG_DP_SAWF_STATS) 884 #else 885 #define CFG_DP_SAWF_STATS_CONFIG 886 #endif 887 888 #ifdef WLAN_FEATURE_LOCAL_PKT_CAPTURE 889 /* 890 * <ini> 891 * local_pkt_capture - Enable/Disable Local packet capture 892 * @Default: false 893 * 894 * This ini is used to enable/disable local packet capture. 895 * 896 * Related: None 897 * 898 * Usage: External 899 * 900 * </ini> 901 */ 902 #define CFG_DP_LOCAL_PKT_CAPTURE \ 903 CFG_INI_BOOL( \ 904 "local_packet_capture", \ 905 true, \ 906 "Local packet capture") 907 908 #define CFG_DP_LOCAL_PKT_CAPTURE_CONFIG CFG(CFG_DP_LOCAL_PKT_CAPTURE) 909 #else 910 #define CFG_DP_LOCAL_PKT_CAPTURE_CONFIG 911 #endif 912 913 /* 914 * <ini> 915 * dp_rx_pending_hl_threshold - High threshold of frame number to start 916 * frame dropping scheme 917 * @Min: 0 918 * @Max: 524288 919 * @Default: 393216 920 * 921 * This ini entry is used to set a high limit threshold to start frame 922 * dropping scheme 923 * 924 * Usage: External 925 * 926 * </ini> 927 */ 928 #define CFG_DP_RX_PENDING_HL_THRESHOLD \ 929 CFG_INI_UINT("dp_rx_pending_hl_threshold", \ 930 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MIN, \ 931 WLAN_CFG_RX_PENDING_HL_THRESHOLD_MAX, \ 932 WLAN_CFG_RX_PENDING_HL_THRESHOLD, \ 933 CFG_VALUE_OR_DEFAULT, "DP rx pending hl threshold") 934 935 /* 936 * <ini> 937 * dp_rx_pending_lo_threshold - Low threshold of frame number to stop 938 * frame dropping scheme 939 * @Min: 100 940 * @Max: 524288 941 * @Default: 393216 942 * 943 * This ini entry is used to set a low limit threshold to stop frame 944 * dropping scheme 945 * 946 * Usage: External 947 * 948 * </ini> 949 */ 950 #define CFG_DP_RX_PENDING_LO_THRESHOLD \ 951 CFG_INI_UINT("dp_rx_pending_lo_threshold", \ 952 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MIN, \ 953 WLAN_CFG_RX_PENDING_LO_THRESHOLD_MAX, \ 954 WLAN_CFG_RX_PENDING_LO_THRESHOLD, \ 955 CFG_VALUE_OR_DEFAULT, "DP rx pending lo threshold") 956 957 #define CFG_DP_BASE_HW_MAC_ID \ 958 CFG_INI_UINT("dp_base_hw_macid", \ 959 0, 1, 1, \ 960 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID") 961 962 #define CFG_DP_RX_HASH \ 963 CFG_INI_BOOL("dp_rx_hash", true, \ 964 "DP Rx Hash") 965 966 #define CFG_DP_RX_RR \ 967 CFG_INI_BOOL("dp_rx_rr", true, \ 968 "DP Rx Round Robin") 969 970 #define CFG_DP_TSO \ 971 CFG_INI_BOOL("TSOEnable", false, \ 972 "DP TSO Enabled") 973 974 #define CFG_DP_LRO \ 975 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \ 976 "DP LRO Enable") 977 978 #ifdef WLAN_USE_CONFIG_PARAMS 979 /* 980 * <ini> 981 * dp_tx_desc_use_512p - Use 512M tx descriptor size 982 * @Min: 0 983 * @Max: 1 984 * @Default: 0 985 * 986 * This ini entry is used as flag to use 512M tx descriptor size or not 987 * 988 * Usage: Internal 989 * 990 * </ini> 991 */ 992 #define CFG_DP_TX_DESC_512P \ 993 CFG_INI_BOOL("dp_tx_desc_use_512p", false, \ 994 "DP TX DESC PINE SPECIFIC") 995 996 /* 997 * <ini> 998 * dp_nss_3radio_ring - Use 3 Radio NSS comp ring size 999 * @Min: 0 1000 * @Max: 1 1001 * @Default: 0 1002 * 1003 * This ini entry is used as flag to use 3 Radio NSS com ring size or not 1004 * 1005 * Usage: Internal 1006 * 1007 * </ini> 1008 */ 1009 #define CFG_DP_NSS_3RADIO_RING \ 1010 CFG_INI_BOOL("dp_nss_3radio_ring", false, \ 1011 "DP NSS 3 RADIO RING SIZE") 1012 1013 /* 1014 * <ini> 1015 * dp_mon_ring_per_512M - Update monitor status ring as 512M profile 1016 * @Min: 0 1017 * @Max: 1 1018 * @Default: 0 1019 * 1020 * This ini entry is used as flag to update monitor status ring as 512M profile 1021 * 1022 * Usage: Internal 1023 * 1024 * </ini> 1025 */ 1026 #define CFG_DP_MON_STATUS_512M \ 1027 CFG_INI_BOOL("dp_mon_ring_per_512M", false, \ 1028 "DP MON STATUS RING SIZE PER 512M PROFILE") 1029 1030 /* 1031 * <ini> 1032 * dp_mon_2chain_ring - Reduce monitor rings size as for 2 Chains case 1033 * @Min: 0 1034 * @Max: 1 1035 * @Default: 0 1036 * 1037 * This ini entry is used as flag to reduce monitor rings size as those used 1038 * in case of 2 Tx/RxChains 1039 * 1040 * Usage: Internal 1041 * 1042 * </ini> 1043 */ 1044 #define CFG_DP_MON_2CHAIN_RING \ 1045 CFG_INI_BOOL("dp_mon_2chain_ring", false, \ 1046 "DP MON UPDATE RINGS FOR 2CHAIN") 1047 1048 /* 1049 * <ini> 1050 * dp_mon_4chain_ring - Update monitor rings size for 4 Chains case 1051 * @Min: 0 1052 * @Max: 1 1053 * @Default: 0 1054 * 1055 * This ini entry is used as flag to reduce monitor rings size as those used 1056 * in case of 4 Tx/RxChains 1057 * 1058 * Usage: Internal 1059 * 1060 * </ini> 1061 */ 1062 #define CFG_DP_MON_4CHAIN_RING \ 1063 CFG_INI_BOOL("dp_mon_4chain_ring", false, \ 1064 "DP MON UPDATE RINGS FOR 4CHAIN") 1065 1066 /* 1067 * <ini> 1068 * dp_4radip_rdp_reo - Update RDP REO map based on 4 radio config 1069 * @Min: 0 1070 * @Max: 1 1071 * @Default: 0 1072 * 1073 * This ini entry is used as flag to update RDP reo map based on 4 Radio config 1074 * 1075 * Usage: Internal 1076 * 1077 * </ini> 1078 */ 1079 #define CFG_DP_4RADIO_RDP_REO \ 1080 CFG_INI_BOOL("dp_nss_4radio_rdp_reo", \ 1081 false, "Update REO destination mapping for 4radio") 1082 1083 #define CFG_DP_INI_SECTION_PARAMS \ 1084 CFG(CFG_DP_NSS_3RADIO_RING) \ 1085 CFG(CFG_DP_TX_DESC_512P) \ 1086 CFG(CFG_DP_MON_STATUS_512M) \ 1087 CFG(CFG_DP_MON_2CHAIN_RING) \ 1088 CFG(CFG_DP_MON_4CHAIN_RING) \ 1089 CFG(CFG_DP_4RADIO_RDP_REO) 1090 #else 1091 #define CFG_DP_INI_SECTION_PARAMS 1092 #endif 1093 1094 /* 1095 * <ini> 1096 * CFG_DP_SG - Enable the SG feature standalonely 1097 * @Min: 0 1098 * @Max: 1 1099 * @Default: 1 1100 * 1101 * This ini entry is used to enable/disable SG feature standalonely. 1102 * Also does Rome support SG on TX, lithium does not. 1103 * For example the lithium does not support SG on UDP frames. 1104 * Which is able to handle SG only for TSO frames(in case TSO is enabled). 1105 * 1106 * Usage: External 1107 * 1108 * </ini> 1109 */ 1110 #define CFG_DP_SG \ 1111 CFG_INI_BOOL("dp_sg_support", false, \ 1112 "DP SG Enable") 1113 1114 #define WLAN_CFG_GRO_ENABLE_MIN 0 1115 #define WLAN_CFG_GRO_ENABLE_MAX 3 1116 #define WLAN_CFG_GRO_ENABLE_DEFAULT 0 1117 #define DP_GRO_ENABLE_BIT_SET BIT(0) 1118 #define DP_TC_BASED_DYNAMIC_GRO BIT(1) 1119 1120 /* 1121 * <ini> 1122 * CFG_DP_GRO - Enable the GRO feature standalonely 1123 * @Min: 0 1124 * @Max: 3 1125 * @Default: 0 1126 * 1127 * This ini entry is used to enable/disable GRO feature standalonely. 1128 * Value 0: Disable GRO feature 1129 * Value 1: Enable GRO feature always 1130 * Value 3: Enable GRO dynamic feature where TC rule can control GRO 1131 * behavior 1132 * 1133 * Usage: External 1134 * 1135 * </ini> 1136 */ 1137 #define CFG_DP_GRO \ 1138 CFG_INI_UINT("GROEnable", \ 1139 WLAN_CFG_GRO_ENABLE_MIN, \ 1140 WLAN_CFG_GRO_ENABLE_MAX, \ 1141 WLAN_CFG_GRO_ENABLE_DEFAULT, \ 1142 CFG_VALUE_OR_DEFAULT, "DP GRO Enable") 1143 1144 #define WLAN_CFG_TC_INGRESS_PRIO_MIN 0 1145 #define WLAN_CFG_TC_INGRESS_PRIO_MAX 0xFFFF 1146 #define WLAN_CFG_TC_INGRESS_PRIO_DEFAULT 0 1147 1148 #define CFG_DP_TC_INGRESS_PRIO \ 1149 CFG_INI_UINT("tc_ingress_prio", \ 1150 WLAN_CFG_TC_INGRESS_PRIO_MIN, \ 1151 WLAN_CFG_TC_INGRESS_PRIO_MAX, \ 1152 WLAN_CFG_TC_INGRESS_PRIO_DEFAULT, \ 1153 CFG_VALUE_OR_DEFAULT, "DP tc ingress prio") 1154 1155 #define CFG_DP_OL_TX_CSUM \ 1156 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \ 1157 "DP tx csum Enable") 1158 1159 #define CFG_DP_OL_RX_CSUM \ 1160 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \ 1161 "DP rx csum Enable") 1162 1163 #define CFG_DP_RAWMODE \ 1164 CFG_INI_BOOL("dp_rawmode_support", false, \ 1165 "DP rawmode Enable") 1166 1167 #define CFG_DP_PEER_FLOW_CTRL \ 1168 CFG_INI_BOOL("dp_peer_flow_control_support", false, \ 1169 "DP peer flow ctrl Enable") 1170 1171 #define CFG_DP_NAPI \ 1172 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \ 1173 "DP Napi Enabled") 1174 /* 1175 * <ini> 1176 * gEnableP2pIpTcpUdpChecksumOffload - Enable checksum offload for P2P mode 1177 * @Min: 0 1178 * @Max: 1 1179 * @Default: 1 1180 * 1181 * This ini entry is used to enable/disable TX checksum(UDP/TCP) for P2P modes. 1182 * This includes P2P device mode, P2P client mode and P2P GO mode. 1183 * The feature is enabled by default. To disable TX checksum for P2P, add the 1184 * following entry in ini file: 1185 * gEnableP2pIpTcpUdpChecksumOffload=0 1186 * 1187 * Usage: External 1188 * 1189 * </ini> 1190 */ 1191 #define CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD \ 1192 CFG_INI_BOOL("gEnableP2pIpTcpUdpChecksumOffload", true, \ 1193 "DP TCP UDP Checksum Offload for P2P mode (device/cli/go)") 1194 1195 /* 1196 * <ini> 1197 * gEnableNanIpTcpUdpChecksumOffload - Enable checksum offload for NAN mode 1198 * @Min: 0 1199 * @Max: 1 1200 * @Default: 1 1201 * 1202 * Usage: External 1203 * 1204 * </ini> 1205 */ 1206 #define CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD \ 1207 CFG_INI_BOOL("gEnableNanIpTcpUdpChecksumOffload", true, \ 1208 "DP TCP UDP Checksum Offload for NAN mode") 1209 1210 /* 1211 * <ini> 1212 * gEnableIpTcpUdpChecksumOffload - Enable checksum offload 1213 * @Min: 0 1214 * @Max: 1 1215 * @Default: 1 1216 * 1217 * Usage: External 1218 * 1219 * </ini> 1220 */ 1221 #define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \ 1222 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \ 1223 "DP TCP UDP Checksum Offload") 1224 1225 #define CFG_DP_DEFRAG_TIMEOUT_CHECK \ 1226 CFG_INI_BOOL("dp_defrag_timeout_check", true, \ 1227 "DP Defrag Timeout Check") 1228 1229 #define CFG_DP_WBM_RELEASE_RING \ 1230 CFG_INI_UINT("dp_wbm_release_ring", \ 1231 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \ 1232 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \ 1233 WLAN_CFG_WBM_RELEASE_RING_SIZE, \ 1234 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring") 1235 1236 #define CFG_DP_TCL_CMD_CREDIT_RING \ 1237 CFG_INI_UINT("dp_tcl_cmd_credit_ring", \ 1238 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MIN, \ 1239 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE_MAX, \ 1240 WLAN_CFG_TCL_CMD_CREDIT_RING_SIZE, \ 1241 CFG_VALUE_OR_DEFAULT, "DP TCL Cmd_Credit ring") 1242 1243 #define CFG_DP_TCL_STATUS_RING \ 1244 CFG_INI_UINT("dp_tcl_status_ring",\ 1245 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \ 1246 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \ 1247 WLAN_CFG_TCL_STATUS_RING_SIZE, \ 1248 CFG_VALUE_OR_DEFAULT, "DP TCL status ring") 1249 1250 #define CFG_DP_REO_REINJECT_RING \ 1251 CFG_INI_UINT("dp_reo_reinject_ring", \ 1252 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \ 1253 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \ 1254 WLAN_CFG_REO_REINJECT_RING_SIZE, \ 1255 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring") 1256 1257 #define CFG_DP_RX_RELEASE_RING \ 1258 CFG_INI_UINT("dp_rx_release_ring", \ 1259 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \ 1260 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \ 1261 WLAN_CFG_RX_RELEASE_RING_SIZE, \ 1262 CFG_VALUE_OR_DEFAULT, "DP Rx release ring") 1263 1264 #define CFG_DP_RX_DESTINATION_RING \ 1265 CFG_INI_UINT("dp_reo_dst_ring", \ 1266 WLAN_CFG_REO_DST_RING_SIZE_MIN, \ 1267 WLAN_CFG_REO_DST_RING_SIZE_MAX, \ 1268 WLAN_CFG_REO_DST_RING_SIZE, \ 1269 CFG_VALUE_OR_DEFAULT, "DP REO destination ring") 1270 1271 #define CFG_DP_REO_EXCEPTION_RING \ 1272 CFG_INI_UINT("dp_reo_exception_ring", \ 1273 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \ 1274 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \ 1275 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \ 1276 CFG_VALUE_OR_DEFAULT, "DP REO exception ring") 1277 1278 #define CFG_DP_REO_CMD_RING \ 1279 CFG_INI_UINT("dp_reo_cmd_ring", \ 1280 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \ 1281 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \ 1282 WLAN_CFG_REO_CMD_RING_SIZE, \ 1283 CFG_VALUE_OR_DEFAULT, "DP REO command ring") 1284 1285 #define CFG_DP_REO_STATUS_RING \ 1286 CFG_INI_UINT("dp_reo_status_ring", \ 1287 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \ 1288 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \ 1289 WLAN_CFG_REO_STATUS_RING_SIZE, \ 1290 CFG_VALUE_OR_DEFAULT, "DP REO status ring") 1291 1292 #define CFG_DP_RXDMA_BUF_RING \ 1293 CFG_INI_UINT("dp_rxdma_buf_ring", \ 1294 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \ 1295 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \ 1296 WLAN_CFG_RXDMA_BUF_RING_SIZE, \ 1297 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring") 1298 1299 #define CFG_DP_RXDMA_REFILL_RING \ 1300 CFG_INI_UINT("dp_rxdma_refill_ring", \ 1301 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \ 1302 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \ 1303 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \ 1304 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring") 1305 1306 #define CFG_DP_RXDMA_REFILL_LT_DISABLE \ 1307 CFG_INI_BOOL("dp_disable_rx_buf_low_threshold", false, \ 1308 "Disable Low threshold interrupts for Rx Refill ring") 1309 1310 #define CFG_DP_TX_DESC_LIMIT_0 \ 1311 CFG_INI_UINT("dp_tx_desc_limit_0", \ 1312 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \ 1313 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \ 1314 WLAN_CFG_TX_DESC_LIMIT_0, \ 1315 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0") 1316 1317 #define CFG_DP_TX_DESC_LIMIT_1 \ 1318 CFG_INI_UINT("dp_tx_desc_limit_1", \ 1319 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \ 1320 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \ 1321 WLAN_CFG_TX_DESC_LIMIT_1, \ 1322 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1") 1323 1324 #define CFG_DP_TX_DESC_LIMIT_2 \ 1325 CFG_INI_UINT("dp_tx_desc_limit_2", \ 1326 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \ 1327 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \ 1328 WLAN_CFG_TX_DESC_LIMIT_2, \ 1329 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2") 1330 1331 #define CFG_DP_TX_DEVICE_LIMIT \ 1332 CFG_INI_UINT("dp_tx_device_limit", \ 1333 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \ 1334 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \ 1335 WLAN_CFG_TX_DEVICE_LIMIT, \ 1336 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit") 1337 1338 #define CFG_DP_TX_SPL_DEVICE_LIMIT \ 1339 CFG_INI_UINT("dp_tx_spl_device_limit", \ 1340 WLAN_CFG_TX_SPL_DEVICE_LIMIT_MIN, \ 1341 WLAN_CFG_TX_SPL_DEVICE_LIMIT_MAX, \ 1342 WLAN_CFG_TX_SPL_DEVICE_LIMIT, \ 1343 CFG_VALUE_OR_DEFAULT, "DP TX Special DEVICE limit") 1344 1345 #define CFG_DP_TX_SW_INTERNODE_QUEUE \ 1346 CFG_INI_UINT("dp_tx_sw_internode_queue", \ 1347 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \ 1348 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \ 1349 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \ 1350 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue") 1351 1352 #define CFG_DP_TX_DESC_GLOBAL_COUNT \ 1353 CFG_INI_UINT("dp_tx_desc_global", \ 1354 WLAN_CFG_TX_DESC_GLOBAL_COUNT_MIN, \ 1355 WLAN_CFG_TX_DESC_GLOBAL_COUNT_MAX, \ 1356 WLAN_CFG_TX_DESC_GLOBAL_COUNT, \ 1357 CFG_VALUE_OR_DEFAULT, "DP Global TX descriptor count") 1358 1359 #define CFG_DP_SPCL_TX_DESC_GLOBAL_COUNT \ 1360 CFG_INI_UINT("dp_spcl_tx_desc_global", \ 1361 WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MIN, \ 1362 WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT_MAX, \ 1363 WLAN_CFG_SPCL_TX_DESC_GLOBAL_COUNT, \ 1364 CFG_VALUE_OR_DEFAULT, "DP Global special TX descriptor count") 1365 1366 #define CFG_DP_RXDMA_MONITOR_BUF_RING \ 1367 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \ 1368 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \ 1369 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \ 1370 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \ 1371 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring") 1372 1373 #define CFG_DP_TX_MONITOR_BUF_RING \ 1374 CFG_INI_UINT("dp_tx_monitor_buf_ring", \ 1375 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MIN, \ 1376 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE_MAX, \ 1377 WLAN_CFG_TX_MONITOR_BUF_RING_SIZE, \ 1378 CFG_VALUE_OR_DEFAULT, "DP TX monitor buffer ring") 1379 1380 #define CFG_DP_RXDMA_MONITOR_DST_RING \ 1381 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \ 1382 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \ 1383 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \ 1384 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \ 1385 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1386 1387 #define CFG_DP_TX_MONITOR_DST_RING \ 1388 CFG_INI_UINT("dp_tx_monitor_dst_ring", \ 1389 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MIN, \ 1390 WLAN_CFG_TX_MONITOR_DST_RING_SIZE_MAX, \ 1391 WLAN_CFG_TX_MONITOR_DST_RING_SIZE, \ 1392 CFG_VALUE_OR_DEFAULT, "DP TX monitor destination ring") 1393 1394 #define CFG_DP_RXDMA_MONITOR_STATUS_RING \ 1395 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \ 1396 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \ 1397 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \ 1398 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \ 1399 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring") 1400 1401 #define CFG_DP_RXDMA_MONITOR_DESC_RING \ 1402 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \ 1403 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \ 1404 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \ 1405 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \ 1406 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring") 1407 1408 #define CFG_DP_SW2RXDMA_LINK_RING \ 1409 CFG_INI_UINT("dp_sw2rxdma_link_ring", \ 1410 WLAN_CFG_SW2RXDMA_LINK_RING_SIZE_MIN, \ 1411 WLAN_CFG_SW2RXDMA_LINK_RING_SIZE_MAX, \ 1412 WLAN_CFG_SW2RXDMA_LINK_RING_SIZE, \ 1413 CFG_VALUE_OR_DEFAULT, "DP SW2RXDMA link ring") 1414 1415 #define CFG_DP_RXDMA_ERR_DST_RING \ 1416 CFG_INI_UINT("dp_rxdma_err_dst_ring", \ 1417 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \ 1418 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \ 1419 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \ 1420 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring") 1421 1422 #define CFG_DP_PER_PKT_LOGGING \ 1423 CFG_INI_UINT("enable_verbose_debug", \ 1424 0, 0xffff, 0, \ 1425 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging") 1426 1427 #define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \ 1428 CFG_INI_UINT("TxFlowStartQueueOffset", \ 1429 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \ 1430 CFG_VALUE_OR_DEFAULT, "Start queue offset") 1431 1432 #define CFG_DP_TX_FLOW_STOP_QUEUE_TH \ 1433 CFG_INI_UINT("TxFlowStopQueueThreshold", \ 1434 0, 50, 15, \ 1435 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold") 1436 1437 #define CFG_DP_IPA_UC_TX_BUF_SIZE \ 1438 CFG_INI_UINT("IpaUcTxBufSize", \ 1439 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \ 1440 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size") 1441 1442 #define CFG_DP_IPA_UC_TX_PARTITION_BASE \ 1443 CFG_INI_UINT("IpaUcTxPartitionBase", \ 1444 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \ 1445 CFG_VALUE_OR_DEFAULT, "IPA tx partition base") 1446 1447 #define CFG_DP_IPA_UC_RX_IND_RING_COUNT \ 1448 CFG_INI_UINT("IpaUcRxIndRingCount", \ 1449 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \ 1450 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count") 1451 1452 #define CFG_DP_AP_STA_SECURITY_SEPERATION \ 1453 CFG_INI_BOOL("gDisableIntraBssFwd", \ 1454 false, "Disable intrs BSS Rx packets") 1455 1456 #define CFG_DP_ENABLE_DATA_STALL_DETECTION \ 1457 CFG_INI_UINT("gEnableDataStallDetection", \ 1458 0, 0xFFFFFFFF, 0x1, \ 1459 CFG_VALUE_OR_DEFAULT, "Enable/Disable Data stall detection") 1460 1461 #define CFG_DP_RX_SW_DESC_WEIGHT \ 1462 CFG_INI_UINT("dp_rx_sw_desc_weight", \ 1463 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \ 1464 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \ 1465 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \ 1466 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight") 1467 1468 #define CFG_DP_RX_SW_DESC_NUM \ 1469 CFG_INI_UINT("dp_rx_sw_desc_num", \ 1470 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MIN, \ 1471 WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX, \ 1472 WLAN_CFG_RX_SW_DESC_NUM_SIZE, \ 1473 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC num") 1474 1475 #define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \ 1476 CFG_INI_UINT("dp_rx_flow_search_table_size", \ 1477 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \ 1478 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \ 1479 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_DEFAULT, \ 1480 CFG_VALUE_OR_DEFAULT, \ 1481 "DP Rx Flow Search Table Size in number of entries") 1482 1483 #define CFG_DP_RX_FLOW_TAG_ENABLE \ 1484 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \ 1485 "Enable/Disable DP Rx Flow Tag") 1486 1487 #define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \ 1488 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \ 1489 "DP Rx Flow Search Table Is Per PDev") 1490 1491 #define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \ 1492 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \ 1493 "Enable/Disable Rx Protocol & Flow tags in Monitor mode") 1494 1495 #define CFG_DP_TX_PER_PKT_VDEV_ID_CHECK \ 1496 CFG_INI_BOOL("dp_tx_allow_per_pkt_vdev_id_check", false, \ 1497 "Enable/Disable tx Per Pkt vdev id check") 1498 1499 #define CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE \ 1500 CFG_INI_BOOL("dp_handle_invalid_decap_type_disable", false, \ 1501 "Enable/Disable DP TLV out of order WAR") 1502 1503 #define CFG_DP_TXMON_SW_PEER_FILTERING \ 1504 CFG_INI_BOOL("tx_litemon_sw_peer_filtering", false, \ 1505 "Enable SW based tx monitor peer fitlering") 1506 1507 #define CFG_DP_POINTER_TIMER_THRESHOLD_RX \ 1508 CFG_INI_UINT("dp_rx_ptr_timer_threshold", \ 1509 0, 0xFFFF, 0, \ 1510 CFG_VALUE_OR_DEFAULT, "RX pointer update timer threshold") 1511 1512 #define CFG_DP_POINTER_NUM_THRESHOLD_RX \ 1513 CFG_INI_UINT("dp_rx_ptr_num_threshold", \ 1514 0, 63, 0, \ 1515 CFG_VALUE_OR_DEFAULT, "RX pointer update entries number threshold") 1516 1517 #define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \ 1518 CFG_INI_UINT("mon_drop_thresh", \ 1519 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \ 1520 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \ 1521 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \ 1522 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop threshold") 1523 1524 #define CFG_DP_PKTLOG_BUFFER_SIZE \ 1525 CFG_INI_UINT("PktlogBufSize", \ 1526 WLAN_CFG_PKTLOG_MIN_BUFFER_SIZE, \ 1527 WLAN_CFG_PKTLOG_MAX_BUFFER_SIZE, \ 1528 WLAN_CFG_PKTLOG_BUFFER_SIZE, \ 1529 CFG_VALUE_OR_DEFAULT, "Packet Log buffer size") 1530 1531 #define CFG_DP_FULL_MON_MODE \ 1532 CFG_INI_BOOL("full_mon_mode", \ 1533 false, "Full Monitor mode support") 1534 1535 #define CFG_DP_REO_RINGS_MAP \ 1536 CFG_INI_UINT("dp_reo_rings_map", \ 1537 WLAN_CFG_NUM_REO_RINGS_MAP_MIN, \ 1538 WLAN_CFG_NUM_REO_RINGS_MAP_MAX, \ 1539 WLAN_CFG_NUM_REO_RINGS_MAP, \ 1540 CFG_VALUE_OR_DEFAULT, "REO Destination Rings Mapping") 1541 1542 #define CFG_DP_RX_RADIO_0_DEFAULT_REO \ 1543 CFG_INI_UINT("dp_rx_radio0_default_reo", \ 1544 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1545 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1546 WLAN_CFG_RADIO_0_DEFAULT_REO, \ 1547 CFG_VALUE_OR_DEFAULT, "Radio0 to REO destination default mapping") 1548 1549 #define CFG_DP_RX_RADIO_1_DEFAULT_REO \ 1550 CFG_INI_UINT("dp_rx_radio1_default_reo", \ 1551 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1552 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1553 WLAN_CFG_RADIO_1_DEFAULT_REO, \ 1554 CFG_VALUE_OR_DEFAULT, "Radio1 to REO destination default mapping") 1555 1556 #define CFG_DP_RX_RADIO_2_DEFAULT_REO \ 1557 CFG_INI_UINT("dp_rx_radio2_default_reo", \ 1558 WLAN_CFG_RADIO_DEFAULT_REO_MIN, \ 1559 WLAN_CFG_RADIO_DEFAULT_REO_MAX, \ 1560 WLAN_CFG_RADIO_2_DEFAULT_REO, \ 1561 CFG_VALUE_OR_DEFAULT, "Radio2 to REO destination default mapping") 1562 1563 #define CFG_DP_PEER_EXT_STATS \ 1564 CFG_INI_BOOL("peer_ext_stats", \ 1565 false, "Peer extended stats") 1566 1567 #if defined QCA_ENHANCED_STATS_SUPPORT || defined DP_MLO_LINK_STATS_SUPPORT 1568 #define DEFAULT_PEER_LINK_STATS_VALUE true 1569 #else 1570 #define DEFAULT_PEER_LINK_STATS_VALUE false 1571 #endif /* QCA_ENHANCED_STATS_SUPPORT */ 1572 1573 #define CFG_DP_PEER_LINK_STATS \ 1574 CFG_INI_BOOL("peer_link_stats", \ 1575 DEFAULT_PEER_LINK_STATS_VALUE, "Peer Link stats") 1576 1577 #define CFG_DP_PEER_JITTER_STATS \ 1578 CFG_INI_BOOL("peer_jitter_stats", \ 1579 false, "Peer Jitter stats") 1580 1581 #define CFG_DP_NAPI_SCALE_FACTOR \ 1582 CFG_INI_UINT("dp_napi_scale_factor", \ 1583 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MIN, \ 1584 WLAN_CFG_DP_NAPI_SCALE_FACTOR_MAX, \ 1585 WLAN_CFG_DP_NAPI_SCALE_FACTOR, \ 1586 CFG_VALUE_OR_DEFAULT, "NAPI scale factor for DP") 1587 1588 #define CFG_DP_STATS_AVG_RATE_FILTER \ 1589 CFG_INI_UINT("dp_stats_avg_rate_filter_val", \ 1590 WLAN_CFG_DP_AVG_RATE_FILTER_MIN,\ 1591 WLAN_CFG_DP_AVG_RATE_FILTER_MAX, \ 1592 WLAN_CFG_DP_AVG_RATE_FILTER_DEFAULT, \ 1593 CFG_VALUE_OR_DEFAULT, \ 1594 "Average Rate filter for stats") 1595 1596 /* 1597 * <ini> 1598 * legacy_mode_csum_disable - Disable csum offload for legacy 802.11abg modes 1599 * @Min: 0 1600 * @Max: 1 1601 * @Default: Default value indicating if checksum should be disabled for 1602 * legacy WLAN modes 1603 * 1604 * This ini is used to disable HW checksum offload capability for legacy 1605 * connections 1606 * 1607 * Related: gEnableIpTcpUdpChecksumOffload should be enabled 1608 * 1609 * Usage: Internal 1610 * 1611 * </ini> 1612 */ 1613 #ifndef DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1614 #define DP_LEGACY_MODE_CSM_DEFAULT_DISABLE 1 1615 #endif 1616 1617 #define CFG_DP_LEGACY_MODE_CSUM_DISABLE \ 1618 CFG_INI_BOOL("legacy_mode_csum_disable", \ 1619 DP_LEGACY_MODE_CSM_DEFAULT_DISABLE, \ 1620 "Enable/Disable legacy mode checksum") 1621 1622 #define CFG_DP_RX_BUFF_POOL_ENABLE \ 1623 CFG_INI_BOOL("dp_rx_buff_prealloc_pool", false, \ 1624 "Enable/Disable DP RX emergency buffer pool support") 1625 1626 #define CFG_DP_RX_REFILL_BUFF_POOL_ENABLE \ 1627 CFG_INI_BOOL("dp_rx_refill_buff_pool", false, \ 1628 "Enable/Disable DP RX refill buffer pool support") 1629 1630 #define CFG_DP_BUFS_PAGE_FRAG_ALLOCS \ 1631 CFG_INI_BOOL("dp_bufs_page_frag_allocs", true, \ 1632 "Enable/Disable forced DP page frage buffer allocations") 1633 1634 #define CFG_DP_POLL_MODE_ENABLE \ 1635 CFG_INI_BOOL("dp_poll_mode_enable", false, \ 1636 "Enable/Disable Polling mode for data path") 1637 1638 #define CFG_DP_RX_FST_IN_CMEM \ 1639 CFG_INI_BOOL("dp_rx_fst_in_cmem", false, \ 1640 "Enable/Disable flow search table in CMEM") 1641 /* 1642 * <ini> 1643 * gEnableSWLM - Control DP Software latency manager 1644 * @Min: 0 1645 * @Max: 1 1646 * @Default: 0 1647 * 1648 * This ini is used to enable DP Software latency Manager 1649 * 1650 * Supported Feature: STA,P2P and SAP IPA disabled terminating 1651 * 1652 * Usage: Internal 1653 * 1654 * </ini> 1655 */ 1656 #define CFG_DP_SWLM_ENABLE \ 1657 CFG_INI_BOOL("gEnableSWLM", false, \ 1658 "Enable/Disable DP SWLM") 1659 /* 1660 * <ini> 1661 * wow_check_rx_pending_enable - control to check RX frames pending in Wow 1662 * @Min: 0 1663 * @Max: 1 1664 * @Default: 0 1665 * 1666 * This ini is used to control DP Software to perform RX pending check 1667 * before entering WoW mode 1668 * 1669 * Usage: Internal 1670 * 1671 * </ini> 1672 */ 1673 #define CFG_DP_WOW_CHECK_RX_PENDING \ 1674 CFG_INI_BOOL("wow_check_rx_pending_enable", \ 1675 false, \ 1676 "enable rx frame pending check in WoW mode") 1677 #define CFG_DP_DELAY_MON_REPLENISH \ 1678 CFG_INI_BOOL("delay_mon_replenish", \ 1679 true, "Delay Monitor Replenish") 1680 1681 #ifdef QCA_VDEV_STATS_HW_OFFLOAD_SUPPORT 1682 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN 500 1683 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX 2000 1684 #define WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER 500 1685 1686 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG \ 1687 CFG_INI_BOOL("vdev_stats_hw_offload_config", \ 1688 false, "Offload vdev stats to HW") 1689 #define CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER \ 1690 CFG_INI_UINT("vdev_stats_hw_offload_timer", \ 1691 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MIN, \ 1692 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER_MAX, \ 1693 WLAN_CFG_INT_VDEV_STATS_HW_OFFLOAD_TIMER, \ 1694 CFG_VALUE_OR_DEFAULT, \ 1695 "vdev stats hw offload timer duration") 1696 #define CFG_DP_VDEV_STATS_HW_OFFLOAD \ 1697 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_CONFIG) \ 1698 CFG(CFG_DP_VDEV_STATS_HW_OFFLOAD_TIMER) 1699 #else 1700 #define CFG_DP_VDEV_STATS_HW_OFFLOAD 1701 #endif 1702 1703 /* 1704 * <ini> 1705 * ghw_cc_enable - enable HW cookie conversion by register 1706 * @Min: 0 1707 * @Max: 1 1708 * @Default: 1 1709 * 1710 * This ini is used to control HW based 20 bits cookie to 64 bits 1711 * Desc virtual address conversion 1712 * 1713 * Usage: Internal 1714 * 1715 * </ini> 1716 */ 1717 #define CFG_DP_HW_CC_ENABLE \ 1718 CFG_INI_BOOL("ghw_cc_enable", \ 1719 true, "Enable/Disable HW cookie conversion") 1720 1721 #ifdef IPA_OFFLOAD 1722 /* 1723 * <ini> 1724 * dp_ipa_tx_ring_size - Set tcl ring size for IPA 1725 * @Min: 1024 1726 * @Max: 8096 1727 * @Default: 1024 1728 * 1729 * This ini sets the tcl ring size for IPA 1730 * 1731 * Related: N/A 1732 * 1733 * Supported Feature: IPA 1734 * 1735 * Usage: Internal 1736 * 1737 * </ini> 1738 */ 1739 #define CFG_DP_IPA_TX_RING_SIZE \ 1740 CFG_INI_UINT("dp_ipa_tx_ring_size", \ 1741 WLAN_CFG_IPA_TX_RING_SIZE_MIN, \ 1742 WLAN_CFG_IPA_TX_RING_SIZE_MAX, \ 1743 WLAN_CFG_IPA_TX_RING_SIZE, \ 1744 CFG_VALUE_OR_DEFAULT, "IPA TCL ring size") 1745 1746 /* 1747 * <ini> 1748 * dp_ipa_tx_comp_ring_size - Set tx comp ring size for IPA 1749 * @Min: 1024 1750 * @Max: 8096 1751 * @Default: 1024 1752 * 1753 * This ini sets the tx comp ring size for IPA 1754 * 1755 * Related: N/A 1756 * 1757 * Supported Feature: IPA 1758 * 1759 * Usage: Internal 1760 * 1761 * </ini> 1762 */ 1763 #define CFG_DP_IPA_TX_COMP_RING_SIZE \ 1764 CFG_INI_UINT("dp_ipa_tx_comp_ring_size", \ 1765 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MIN, \ 1766 WLAN_CFG_IPA_TX_COMP_RING_SIZE_MAX, \ 1767 WLAN_CFG_IPA_TX_COMP_RING_SIZE, \ 1768 CFG_VALUE_OR_DEFAULT, "IPA tx comp ring size") 1769 1770 #ifdef IPA_WDI3_TX_TWO_PIPES 1771 /* 1772 * <ini> 1773 * dp_ipa_tx_alt_ring_size - Set alt tcl ring size for IPA 1774 * @Min: 1024 1775 * @Max: 8096 1776 * @Default: 1024 1777 * 1778 * This ini sets the alt tcl ring size for IPA 1779 * 1780 * Related: N/A 1781 * 1782 * Supported Feature: IPA 1783 * 1784 * Usage: Internal 1785 * 1786 * </ini> 1787 */ 1788 #define CFG_DP_IPA_TX_ALT_RING_SIZE \ 1789 CFG_INI_UINT("dp_ipa_tx_alt_ring_size", \ 1790 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MIN, \ 1791 WLAN_CFG_IPA_TX_ALT_RING_SIZE_MAX, \ 1792 WLAN_CFG_IPA_TX_ALT_RING_SIZE, \ 1793 CFG_VALUE_OR_DEFAULT, \ 1794 "DP IPA TX Alternative Ring Size") 1795 1796 /* 1797 * <ini> 1798 * dp_ipa_tx_alt_comp_ring_size - Set tx alt comp ring size for IPA 1799 * @Min: 1024 1800 * @Max: 8096 1801 * @Default: 1024 1802 * 1803 * This ini sets the tx alt comp ring size for IPA 1804 * 1805 * Related: N/A 1806 * 1807 * Supported Feature: IPA 1808 * 1809 * Usage: Internal 1810 * 1811 * </ini> 1812 */ 1813 #define CFG_DP_IPA_TX_ALT_COMP_RING_SIZE \ 1814 CFG_INI_UINT("dp_ipa_tx_alt_comp_ring_size", \ 1815 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MIN, \ 1816 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE_MAX, \ 1817 WLAN_CFG_IPA_TX_ALT_COMP_RING_SIZE, \ 1818 CFG_VALUE_OR_DEFAULT, \ 1819 "DP IPA TX Alternative Completion Ring Size") 1820 1821 #define CFG_DP_IPA_TX_ALT_RING_CFG \ 1822 CFG(CFG_DP_IPA_TX_ALT_RING_SIZE) \ 1823 CFG(CFG_DP_IPA_TX_ALT_COMP_RING_SIZE) 1824 1825 #else 1826 #define CFG_DP_IPA_TX_ALT_RING_CFG 1827 #endif 1828 1829 #define CFG_DP_IPA_TX_RING_CFG \ 1830 CFG(CFG_DP_IPA_TX_RING_SIZE) \ 1831 CFG(CFG_DP_IPA_TX_COMP_RING_SIZE) 1832 #else 1833 #define CFG_DP_IPA_TX_RING_CFG 1834 #define CFG_DP_IPA_TX_ALT_RING_CFG 1835 #endif 1836 1837 #ifdef WLAN_SUPPORT_PPEDS 1838 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MIN 16 1839 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0xFA00 1840 #define WLAN_CFG_NUM_PPEDS_TX_DESC 0x8000 1841 1842 #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MIN 8 1843 #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MAX 256 1844 #define WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI 64 1845 1846 #define WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MIN 0 1847 #define WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MAX 0x2000 1848 #define WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN 0x400 1849 1850 #define CFG_DP_PPEDS_TX_DESC \ 1851 CFG_INI_UINT("dp_ppeds_tx_desc", \ 1852 WLAN_CFG_NUM_PPEDS_TX_DESC_MIN, \ 1853 WLAN_CFG_NUM_PPEDS_TX_DESC_MAX, \ 1854 WLAN_CFG_NUM_PPEDS_TX_DESC, \ 1855 CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Descriptors") 1856 1857 #define CFG_DP_PPEDS_TX_DESC_HOTLIST_LEN \ 1858 CFG_INI_UINT("dp_ppeds_tx_desc_hotlist_len", \ 1859 WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MIN, \ 1860 WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN_MAX, \ 1861 WLAN_CFG_PPEDS_TX_DESC_HOTLIST_LEN, \ 1862 CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Desc hotlist length") 1863 1864 #define CFG_DP_PPEDS_TX_CMP_NAPI_BUDGET \ 1865 CFG_INI_UINT("dp_ppeds_tx_cmp_napi_budget", \ 1866 WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MIN, \ 1867 WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI_MAX, \ 1868 WLAN_CFG_NUM_PPEDS_TX_CMP_NAPI, \ 1869 CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Comp handler napi budget") 1870 1871 #define CFG_DP_PPEDS_ENABLE \ 1872 CFG_INI_BOOL("ppe_ds_enable", true, \ 1873 "DP ppe enable flag") 1874 1875 #define CFG_DP_REO2PPE_RING \ 1876 CFG_INI_UINT("dp_reo2ppe_ring", \ 1877 WLAN_CFG_REO2PPE_RING_SIZE_MIN, \ 1878 WLAN_CFG_REO2PPE_RING_SIZE_MAX, \ 1879 WLAN_CFG_REO2PPE_RING_SIZE, \ 1880 CFG_VALUE_OR_DEFAULT, "DP REO2PPE ring") 1881 1882 #define CFG_DP_PPE2TCL_RING \ 1883 CFG_INI_UINT("dp_ppe2tcl_ring", \ 1884 WLAN_CFG_PPE2TCL_RING_SIZE_MIN, \ 1885 WLAN_CFG_PPE2TCL_RING_SIZE_MAX, \ 1886 WLAN_CFG_PPE2TCL_RING_SIZE, \ 1887 CFG_VALUE_OR_DEFAULT, "DP PPE2TCL rings") 1888 1889 #define CFG_DP_PPEDS_WIFI_SOC_CFG \ 1890 CFG_INI_UINT("ppeds_wifi_soc_cfg", \ 1891 CFG_DP_PPEDS_WIFI_SOC_CFG_NONE, \ 1892 CFG_DP_PPEDS_WIFI_SOC_CFG_ALL, \ 1893 CFG_DP_PPEDS_WIFI_SOC_CFG_DEFAULT, \ 1894 CFG_VALUE_OR_DEFAULT, "PPEDS enable per WiFi SoC") 1895 1896 #define CFG_DP_PPEDS_CONFIG \ 1897 CFG(CFG_DP_PPEDS_TX_CMP_NAPI_BUDGET) \ 1898 CFG(CFG_DP_PPEDS_TX_DESC_HOTLIST_LEN) \ 1899 CFG(CFG_DP_PPEDS_TX_DESC) \ 1900 CFG(CFG_DP_PPEDS_ENABLE) \ 1901 CFG(CFG_DP_REO2PPE_RING) \ 1902 CFG(CFG_DP_PPE2TCL_RING) \ 1903 CFG(CFG_DP_PPEDS_WIFI_SOC_CFG) 1904 #else 1905 #define CFG_DP_PPEDS_CONFIG 1906 #define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0 1907 #endif 1908 1909 #define WLAN_CFG_SPECIAL_MSK_MIN 0 1910 #define WLAN_CFG_SPECIAL_MSK_MAX 0xFFFFFFFF 1911 #define WLAN_CFG_SPECIAL_MSK 0xF 1912 1913 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP) 1914 /* 1915 * <ini> 1916 * dp_chip0_rx_ring_map - Set Rx ring map for CHIP 0 1917 * @Min: 0x0 1918 * @Max: 0xFF 1919 * @Default: 0xF 1920 * 1921 * This ini sets Rx ring map for CHIP 0 1922 * 1923 * Usage: Internal 1924 * 1925 * </ini> 1926 */ 1927 #define CFG_DP_MLO_RX_RING_MAP \ 1928 CFG_INI_UINT("dp_mlo_reo_rings_map", \ 1929 WLAN_CFG_MLO_RX_RING_MAP_MIN, \ 1930 WLAN_CFG_MLO_RX_RING_MAP_MAX, \ 1931 WLAN_CFG_MLO_RX_RING_MAP, \ 1932 CFG_VALUE_OR_DEFAULT, "DP MLO Rx ring map") 1933 1934 1935 #define CFG_DP_MLO_CONFIG \ 1936 CFG(CFG_DP_MLO_RX_RING_MAP) 1937 #else 1938 #define CFG_DP_MLO_CONFIG 1939 #endif 1940 1941 /* 1942 * <ini> 1943 * dp_mpdu_retry_threshold_1 - threshold to increment mpdu success with retries 1944 * @Min: 0 1945 * @Max: 255 1946 * @Default: 0 1947 * 1948 * This ini entry is used to set first threshold to increment the value of 1949 * mpdu_success_with_retries 1950 * 1951 * Usage: Internal 1952 * 1953 * </ini> 1954 */ 1955 #define CFG_DP_MPDU_RETRY_THRESHOLD_1 \ 1956 CFG_INI_UINT("dp_mpdu_retry_threshold_1", \ 1957 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1958 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1959 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1960 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 1") 1961 1962 /* 1963 * <ini> 1964 * dp_mpdu_retry_threshold_2 - threshold to increment mpdu success with retries 1965 * @Min: 0 1966 * @Max: 255 1967 * @Default: 0 1968 * 1969 * This ini entry is used to set second threshold to increment the value of 1970 * mpdu_success_with_retries 1971 * 1972 * Usage: Internal 1973 * 1974 * </ini> 1975 */ 1976 #define CFG_DP_MPDU_RETRY_THRESHOLD_2 \ 1977 CFG_INI_UINT("dp_mpdu_retry_threshold_2", \ 1978 CFG_DP_MPDU_RETRY_THRESHOLD_MIN, \ 1979 CFG_DP_MPDU_RETRY_THRESHOLD_MAX, \ 1980 CFG_DP_MPDU_RETRY_THRESHOLD, \ 1981 CFG_VALUE_OR_DEFAULT, "DP mpdu retry threshold 2") 1982 1983 #ifdef QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES 1984 /* Macro enabling support marking of notify frames by host */ 1985 #define DP_MARK_NOTIFY_FRAME_SUPPORT 1 1986 #else 1987 #define DP_MARK_NOTIFY_FRAME_SUPPORT 0 1988 #endif /* QCA_SUPPORT_TX_MIN_RATES_FOR_SPECIAL_FRAMES */ 1989 1990 /* 1991 * <ini> 1992 * Host DP AST entries database - Enable/Disable 1993 * 1994 * @Default: 0 1995 * 1996 * This ini enables/disables AST entries database on host 1997 * 1998 * Usage: Internal 1999 * 2000 * </ini> 2001 */ 2002 #define CFG_DP_HOST_AST_DB_ENABLE \ 2003 CFG_INI_BOOL("host_ast_db_enable", false, \ 2004 "Host AST entries database Enable/Disable") 2005 2006 #ifdef DP_TX_PACKET_INSPECT_FOR_ILP 2007 /* 2008 * <ini> 2009 * TX packet inspect for ILP - Enable/Disable 2010 * 2011 * @Default: true 2012 * 2013 * This ini enable/disables TX packet inspection for ILP feature 2014 * 2015 * Usage: Internal 2016 * 2017 * </ini> 2018 */ 2019 #define CFG_TX_PKT_INSPECT_FOR_ILP \ 2020 CFG_INI_BOOL("tx_pkt_inspect_for_ilp", true, \ 2021 "TX packet inspect for ILP") 2022 #define CFG_TX_PKT_INSPECT_FOR_ILP_CFG CFG(CFG_TX_PKT_INSPECT_FOR_ILP) 2023 #else 2024 #define CFG_TX_PKT_INSPECT_FOR_ILP_CFG 2025 #endif 2026 2027 /* 2028 * <ini> 2029 * special_frame_msk - frame mask to mark special frame type 2030 * @Min: 0 2031 * @Max: 0xFFFFFFFF 2032 * @Default: 15 2033 * 2034 * This ini entry is used to set frame types to deliver to stack 2035 * in error receive path 2036 * 2037 * Usage: External 2038 * 2039 * </ini> 2040 */ 2041 #define CFG_SPECIAL_FRAME_MSK \ 2042 CFG_INI_UINT("special_frame_msk", \ 2043 WLAN_CFG_SPECIAL_MSK_MIN, \ 2044 WLAN_CFG_SPECIAL_MSK_MAX, \ 2045 WLAN_CFG_SPECIAL_MSK, \ 2046 CFG_VALUE_OR_DEFAULT, "special frame to deliver to stack") 2047 2048 #ifdef DP_UMAC_HW_RESET_SUPPORT 2049 #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_MIN 100 2050 #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_MAX 10000 2051 #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_DEFAULT 1000 2052 2053 #define CFG_DP_UMAC_RESET_BUFFER_WINDOW \ 2054 CFG_INI_UINT("umac_reset_buffer_window", \ 2055 CFG_DP_UMAC_RESET_BUFFER_WINDOW_MIN, \ 2056 CFG_DP_UMAC_RESET_BUFFER_WINDOW_MAX, \ 2057 CFG_DP_UMAC_RESET_BUFFER_WINDOW_DEFAULT, \ 2058 CFG_VALUE_OR_DEFAULT, \ 2059 "Buffer time to check if umac reset was in progress during this window, configured time is in milliseconds") 2060 #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_CFG CFG(CFG_DP_UMAC_RESET_BUFFER_WINDOW) 2061 #else 2062 #define CFG_DP_UMAC_RESET_BUFFER_WINDOW_CFG 2063 #endif /* DP_UMAC_HW_RESET_SUPPORT */ 2064 2065 #define CFG_DP \ 2066 CFG(CFG_DP_HTT_PACKET_TYPE) \ 2067 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \ 2068 CFG(CFG_DP_INT_BATCH_THRESHOLD_MON_DEST) \ 2069 CFG(CFG_DP_INT_BATCH_THRESHOLD_PPE2TCL) \ 2070 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \ 2071 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \ 2072 CFG(CFG_DP_INT_TIMER_THRESHOLD_PPE2TCL) \ 2073 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \ 2074 CFG(CFG_DP_INT_TIMER_THRESHOLD_MON_DEST) \ 2075 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \ 2076 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \ 2077 CFG(CFG_DP_MAX_ALLOC_SIZE) \ 2078 CFG(CFG_DP_MAX_CLIENTS) \ 2079 CFG(CFG_DP_MAX_PEER_ID) \ 2080 CFG(CFG_DP_REO_DEST_RINGS) \ 2081 CFG(CFG_DP_TX_COMP_RINGS) \ 2082 CFG(CFG_DP_TCL_DATA_RINGS) \ 2083 CFG(CFG_DP_NSS_REO_DEST_RINGS) \ 2084 CFG(CFG_DP_NSS_TCL_DATA_RINGS) \ 2085 CFG(CFG_DP_TX_DESC) \ 2086 CFG(CFG_DP_TX_DESC_POOL_3) \ 2087 CFG(CFG_DP_TX_SPL_DESC) \ 2088 CFG(CFG_DP_TX_EXT_DESC) \ 2089 CFG(CFG_DP_TX_EXT_DESC_POOLS) \ 2090 CFG(CFG_DP_PDEV_RX_RING) \ 2091 CFG(CFG_DP_PDEV_TX_RING) \ 2092 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \ 2093 CFG(CFG_DP_TX_COMPL_RING_SIZE) \ 2094 CFG(CFG_DP_TX_RING_SIZE) \ 2095 CFG(CFG_DP_NSS_COMP_RING_SIZE) \ 2096 CFG(CFG_DP_PDEV_LMAC_RING) \ 2097 CFG(CFG_DP_TIME_CONTROL_BP) \ 2098 CFG(CFG_DP_QREF_CONTROL_SIZE) \ 2099 CFG(CFG_DP_BASE_HW_MAC_ID) \ 2100 CFG(CFG_DP_RX_HASH) \ 2101 CFG(CFG_DP_RX_RR) \ 2102 CFG(CFG_DP_TSO) \ 2103 CFG(CFG_DP_LRO) \ 2104 CFG(CFG_DP_SG) \ 2105 CFG(CFG_DP_GRO) \ 2106 CFG(CFG_DP_TC_INGRESS_PRIO) \ 2107 CFG(CFG_DP_OL_TX_CSUM) \ 2108 CFG(CFG_DP_OL_RX_CSUM) \ 2109 CFG(CFG_DP_RAWMODE) \ 2110 CFG(CFG_DP_PEER_FLOW_CTRL) \ 2111 CFG(CFG_DP_NAPI) \ 2112 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \ 2113 CFG(CFG_DP_NAN_TCP_UDP_CKSUM_OFFLOAD) \ 2114 CFG(CFG_DP_P2P_TCP_UDP_CKSUM_OFFLOAD) \ 2115 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \ 2116 CFG(CFG_DP_WBM_RELEASE_RING) \ 2117 CFG(CFG_DP_TCL_CMD_CREDIT_RING) \ 2118 CFG(CFG_DP_TCL_STATUS_RING) \ 2119 CFG(CFG_DP_REO_REINJECT_RING) \ 2120 CFG(CFG_DP_RX_RELEASE_RING) \ 2121 CFG(CFG_DP_REO_EXCEPTION_RING) \ 2122 CFG(CFG_DP_RX_DESTINATION_RING) \ 2123 CFG(CFG_DP_REO_CMD_RING) \ 2124 CFG(CFG_DP_REO_STATUS_RING) \ 2125 CFG(CFG_DP_RXDMA_BUF_RING) \ 2126 CFG(CFG_DP_RXDMA_REFILL_RING) \ 2127 CFG(CFG_DP_RXDMA_REFILL_LT_DISABLE) \ 2128 CFG(CFG_DP_TX_DESC_LIMIT_0) \ 2129 CFG(CFG_DP_TX_DESC_LIMIT_1) \ 2130 CFG(CFG_DP_TX_DESC_LIMIT_2) \ 2131 CFG(CFG_DP_TX_DEVICE_LIMIT) \ 2132 CFG(CFG_DP_TX_SPL_DEVICE_LIMIT) \ 2133 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \ 2134 CFG(CFG_DP_TX_DESC_GLOBAL_COUNT) \ 2135 CFG(CFG_DP_SPCL_TX_DESC_GLOBAL_COUNT) \ 2136 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \ 2137 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \ 2138 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \ 2139 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \ 2140 CFG(CFG_DP_RXDMA_ERR_DST_RING) \ 2141 CFG(CFG_DP_PER_PKT_LOGGING) \ 2142 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \ 2143 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \ 2144 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \ 2145 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \ 2146 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \ 2147 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \ 2148 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \ 2149 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \ 2150 CFG(CFG_DP_RX_SW_DESC_NUM) \ 2151 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \ 2152 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \ 2153 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \ 2154 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \ 2155 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD) \ 2156 CFG(CFG_DP_PKTLOG_BUFFER_SIZE) \ 2157 CFG(CFG_DP_FULL_MON_MODE) \ 2158 CFG(CFG_DP_REO_RINGS_MAP) \ 2159 CFG(CFG_DP_PEER_EXT_STATS) \ 2160 CFG(CFG_DP_PEER_JITTER_STATS) \ 2161 CFG(CFG_DP_PEER_LINK_STATS) \ 2162 CFG(CFG_DP_RX_BUFF_POOL_ENABLE) \ 2163 CFG(CFG_DP_RX_REFILL_BUFF_POOL_ENABLE) \ 2164 CFG(CFG_DP_BUFS_PAGE_FRAG_ALLOCS) \ 2165 CFG(CFG_DP_RX_PENDING_HL_THRESHOLD) \ 2166 CFG(CFG_DP_RX_PENDING_LO_THRESHOLD) \ 2167 CFG(CFG_DP_LEGACY_MODE_CSUM_DISABLE) \ 2168 CFG(CFG_DP_POLL_MODE_ENABLE) \ 2169 CFG(CFG_DP_SWLM_ENABLE) \ 2170 CFG(CFG_DP_TX_PER_PKT_VDEV_ID_CHECK) \ 2171 CFG(CFG_DP_RX_FST_IN_CMEM) \ 2172 CFG(CFG_DP_RX_RADIO_0_DEFAULT_REO) \ 2173 CFG(CFG_DP_RX_RADIO_1_DEFAULT_REO) \ 2174 CFG(CFG_DP_RX_RADIO_2_DEFAULT_REO) \ 2175 CFG(CFG_DP_WOW_CHECK_RX_PENDING) \ 2176 CFG(CFG_DP_HW_CC_ENABLE) \ 2177 CFG(CFG_DP_DELAY_MON_REPLENISH) \ 2178 CFG(CFG_DP_TX_MONITOR_BUF_RING) \ 2179 CFG(CFG_DP_TX_MONITOR_DST_RING) \ 2180 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_1) \ 2181 CFG(CFG_DP_MPDU_RETRY_THRESHOLD_2) \ 2182 CFG_DP_IPA_TX_RING_CFG \ 2183 CFG_DP_PPEDS_CONFIG \ 2184 CFG_DP_IPA_TX_ALT_RING_CFG \ 2185 CFG_DP_MLO_CONFIG \ 2186 CFG_DP_INI_SECTION_PARAMS \ 2187 CFG_DP_VDEV_STATS_HW_OFFLOAD \ 2188 CFG(CFG_DP_TX_CAPT_MAX_MEM_MB) \ 2189 CFG(CFG_DP_NAPI_SCALE_FACTOR) \ 2190 CFG(CFG_DP_HOST_AST_DB_ENABLE) \ 2191 CFG_DP_SAWF_STATS_CONFIG \ 2192 CFG(CFG_DP_HANDLE_INVALID_DECAP_TYPE_DISABLE) \ 2193 CFG(CFG_DP_TXMON_SW_PEER_FILTERING) \ 2194 CFG_TX_PKT_INSPECT_FOR_ILP_CFG \ 2195 CFG(CFG_DP_POINTER_TIMER_THRESHOLD_RX) \ 2196 CFG(CFG_DP_POINTER_NUM_THRESHOLD_RX) \ 2197 CFG_DP_LOCAL_PKT_CAPTURE_CONFIG \ 2198 CFG(CFG_SPECIAL_FRAME_MSK) \ 2199 CFG(CFG_DP_SW2RXDMA_LINK_RING) \ 2200 CFG(CFG_DP_TX_CAPT_RADIO_0_RBM_ID) \ 2201 CFG(CFG_DP_TX_CAPT_RADIO_1_RBM_ID) \ 2202 CFG(CFG_DP_TX_CAPT_RADIO_2_RBM_ID) \ 2203 CFG(CFG_DP_TX_CAPT_RADIO_3_RBM_ID) \ 2204 CFG_DP_UMAC_RESET_BUFFER_WINDOW_CFG \ 2205 CFG(CFG_DP_RX_BUFFER_SIZE) \ 2206 CFG(CFG_DP_STATS_AVG_RATE_FILTER) 2207 #endif /* _CFG_DP_H_ */ 2208