1 /* 2 * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef TARGET_REG_INIT_H 21 #define TARGET_REG_INIT_H 22 #include "reg_struct.h" 23 #include "targaddrs.h" 24 /*** WARNING : Add to the end of the TABLE! do not change the order ****/ 25 struct targetdef_s; 26 27 28 29 #define ATH_UNSUPPORTED_REG_OFFSET UNSUPPORTED_REGISTER_OFFSET 30 #define ATH_SUPPORTED_BY_TARGET(reg_offset) \ 31 ((reg_offset) != ATH_UNSUPPORTED_REG_OFFSET) 32 33 #if defined(MY_TARGET_DEF) 34 35 /* Cross-platform compatibility */ 36 #if !defined(SOC_RESET_CONTROL_OFFSET) && defined(RESET_CONTROL_OFFSET) 37 #define SOC_RESET_CONTROL_OFFSET RESET_CONTROL_OFFSET 38 #endif 39 40 #if !defined(CLOCK_GPIO_OFFSET) 41 #define CLOCK_GPIO_OFFSET ATH_UNSUPPORTED_REG_OFFSET 42 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 43 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 44 #endif 45 46 #if !defined(WLAN_MAC_BASE_ADDRESS) 47 #define WLAN_MAC_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 48 #endif 49 50 #if !defined(CE0_BASE_ADDRESS) 51 #define CE0_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 52 #define CE1_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 53 #define CE_COUNT 0 54 #endif 55 56 #if !defined(MSI_NUM_REQUEST) 57 #define MSI_NUM_REQUEST 0 58 #define MSI_ASSIGN_FW 0 59 #define MSI_ASSIGN_CE_INITIAL 0 60 #endif 61 62 #if !defined(FW_INDICATOR_ADDRESS) 63 #define FW_INDICATOR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 64 #endif 65 66 #if !defined(FW_CPU_PLL_CONFIG) 67 #define FW_CPU_PLL_CONFIG ATH_UNSUPPORTED_REG_OFFSET 68 #endif 69 70 #if !defined(DRAM_BASE_ADDRESS) 71 #define DRAM_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 72 #endif 73 74 #if !defined(SOC_CORE_BASE_ADDRESS) 75 #define SOC_CORE_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 76 #endif 77 78 #if !defined(CPU_INTR_ADDRESS) 79 #define CPU_INTR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 80 #endif 81 82 #if !defined(SOC_LF_TIMER_CONTROL0_ADDRESS) 83 #define SOC_LF_TIMER_CONTROL0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 84 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK ATH_UNSUPPORTED_REG_OFFSET 85 #endif 86 87 #if !defined(SOC_LF_TIMER_STATUS0_ADDRESS) 88 #define SOC_LF_TIMER_STATUS0_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 89 #endif 90 91 #if !defined(SOC_RESET_CONTROL_ADDRESS) 92 #define SOC_RESET_CONTROL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 93 #define SOC_RESET_CONTROL_CE_RST_MASK ATH_UNSUPPORTED_REG_OFFSET 94 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK ATH_UNSUPPORTED_REG_OFFSET 95 #endif 96 97 #if !defined(CORE_CTRL_ADDRESS) 98 #define CORE_CTRL_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 99 #define CORE_CTRL_CPU_INTR_MASK 0 100 #endif 101 102 #if !defined(PCIE_INTR_ENABLE_ADDRESS) 103 #define PCIE_INTR_ENABLE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 104 #define PCIE_INTR_CLR_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 105 #define PCIE_INTR_FIRMWARE_MASK ATH_UNSUPPORTED_REG_OFFSET 106 #define PCIE_INTR_CE_MASK_ALL ATH_UNSUPPORTED_REG_OFFSET 107 #define PCIE_INTR_CAUSE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 108 #endif 109 110 #if !defined(WIFICMN_PCIE_BAR_REG_ADDRESS) 111 #define WIFICMN_PCIE_BAR_REG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 112 #endif 113 114 #if !defined(WIFICMN_INT_STATUS_ADDRESS) 115 #define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 116 #endif 117 118 #if !defined(FW_AXI_MSI_ADDR) 119 #define FW_AXI_MSI_ADDR ATH_UNSUPPORTED_REG_OFFSET 120 #endif 121 122 #if !defined(FW_AXI_MSI_DATA) 123 #define FW_AXI_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET 124 #endif 125 126 #if !defined(WLAN_SUBSYSTEM_CORE_ID_ADDRESS) 127 #define WLAN_SUBSYSTEM_CORE_ID_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 128 #endif 129 130 #if !defined(FPGA_VERSION_ADDRESS) 131 #define FPGA_VERSION_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 132 #endif 133 134 #if !defined(SI_CONFIG_ADDRESS) 135 #define SI_CONFIG_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 136 #define SI_CONFIG_BIDIR_OD_DATA_LSB 0 137 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0 138 #define SI_CONFIG_I2C_LSB 0 139 #define SI_CONFIG_I2C_MASK 0 140 #define SI_CONFIG_POS_SAMPLE_LSB 0 141 #define SI_CONFIG_POS_SAMPLE_MASK 0 142 #define SI_CONFIG_INACTIVE_CLK_LSB 0 143 #define SI_CONFIG_INACTIVE_CLK_MASK 0 144 #define SI_CONFIG_INACTIVE_DATA_LSB 0 145 #define SI_CONFIG_INACTIVE_DATA_MASK 0 146 #define SI_CONFIG_DIVIDER_LSB 0 147 #define SI_CONFIG_DIVIDER_MASK 0 148 #define SI_CONFIG_OFFSET 0 149 #define SI_TX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET 150 #define SI_TX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET 151 #define SI_RX_DATA0_OFFSET ATH_UNSUPPORTED_REG_OFFSET 152 #define SI_RX_DATA1_OFFSET ATH_UNSUPPORTED_REG_OFFSET 153 #define SI_CS_OFFSET ATH_UNSUPPORTED_REG_OFFSET 154 #define SI_CS_DONE_ERR_MASK 0 155 #define SI_CS_DONE_INT_MASK 0 156 #define SI_CS_START_LSB 0 157 #define SI_CS_START_MASK 0 158 #define SI_CS_RX_CNT_LSB 0 159 #define SI_CS_RX_CNT_MASK 0 160 #define SI_CS_TX_CNT_LSB 0 161 #define SI_CS_TX_CNT_MASK 0 162 #endif 163 164 #ifndef SI_BASE_ADDRESS 165 #define SI_BASE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 166 #endif 167 168 #ifndef WLAN_GPIO_PIN10_ADDRESS 169 #define WLAN_GPIO_PIN10_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 170 #endif 171 172 #ifndef WLAN_GPIO_PIN11_ADDRESS 173 #define WLAN_GPIO_PIN11_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 174 #endif 175 176 #ifndef WLAN_GPIO_PIN12_ADDRESS 177 #define WLAN_GPIO_PIN12_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 178 #endif 179 180 #ifndef WLAN_GPIO_PIN13_ADDRESS 181 #define WLAN_GPIO_PIN13_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 182 #endif 183 184 #ifndef WIFICMN_INT_STATUS_ADDRESS 185 #define WIFICMN_INT_STATUS_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 186 #endif 187 188 static struct targetdef_s my_target_def = { 189 .d_RTC_SOC_BASE_ADDRESS = RTC_SOC_BASE_ADDRESS, 190 .d_RTC_WMAC_BASE_ADDRESS = RTC_WMAC_BASE_ADDRESS, 191 .d_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET, 192 .d_WLAN_SYSTEM_SLEEP_OFFSET = WLAN_SYSTEM_SLEEP_OFFSET, 193 .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = WLAN_SYSTEM_SLEEP_DISABLE_LSB, 194 .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = WLAN_SYSTEM_SLEEP_DISABLE_MASK, 195 .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET, 196 .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK, 197 .d_RESET_CONTROL_OFFSET = SOC_RESET_CONTROL_OFFSET, 198 .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK, 199 .d_WLAN_RESET_CONTROL_OFFSET = WLAN_RESET_CONTROL_OFFSET, 200 .d_WLAN_RESET_CONTROL_COLD_RST_MASK = WLAN_RESET_CONTROL_COLD_RST_MASK, 201 .d_WLAN_RESET_CONTROL_WARM_RST_MASK = WLAN_RESET_CONTROL_WARM_RST_MASK, 202 .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS, 203 .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET, 204 .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET, 205 .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK, 206 .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK, 207 .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB, 208 .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK, 209 .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB, 210 .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK, 211 .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB, 212 .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK, 213 .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB, 214 .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK, 215 .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB, 216 .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK, 217 .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB, 218 .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK, 219 .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS, 220 .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET, 221 .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET, 222 .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET, 223 .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET, 224 .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET, 225 .d_SI_CS_OFFSET = SI_CS_OFFSET, 226 .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK, 227 .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK, 228 .d_SI_CS_START_LSB = SI_CS_START_LSB, 229 .d_SI_CS_START_MASK = SI_CS_START_MASK, 230 .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB, 231 .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK, 232 .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB, 233 .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK, 234 .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ, 235 .d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ, 236 .d_MBOX_BASE_ADDRESS = MBOX_BASE_ADDRESS, 237 .d_LOCAL_SCRATCH_OFFSET = LOCAL_SCRATCH_OFFSET, 238 .d_CPU_CLOCK_OFFSET = CPU_CLOCK_OFFSET, 239 .d_GPIO_PIN10_OFFSET = GPIO_PIN10_OFFSET, 240 .d_GPIO_PIN11_OFFSET = GPIO_PIN11_OFFSET, 241 .d_GPIO_PIN12_OFFSET = GPIO_PIN12_OFFSET, 242 .d_GPIO_PIN13_OFFSET = GPIO_PIN13_OFFSET, 243 .d_CLOCK_GPIO_OFFSET = CLOCK_GPIO_OFFSET, 244 .d_CPU_CLOCK_STANDARD_LSB = CPU_CLOCK_STANDARD_LSB, 245 .d_CPU_CLOCK_STANDARD_MASK = CPU_CLOCK_STANDARD_MASK, 246 .d_LPO_CAL_ENABLE_LSB = LPO_CAL_ENABLE_LSB, 247 .d_LPO_CAL_ENABLE_MASK = LPO_CAL_ENABLE_MASK, 248 .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = CLOCK_GPIO_BT_CLK_OUT_EN_LSB, 249 .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = CLOCK_GPIO_BT_CLK_OUT_EN_MASK, 250 .d_ANALOG_INTF_BASE_ADDRESS = ANALOG_INTF_BASE_ADDRESS, 251 .d_WLAN_MAC_BASE_ADDRESS = WLAN_MAC_BASE_ADDRESS, 252 .d_FW_INDICATOR_ADDRESS = FW_INDICATOR_ADDRESS, 253 .d_FW_CPU_PLL_CONFIG = FW_CPU_PLL_CONFIG, 254 .d_DRAM_BASE_ADDRESS = DRAM_BASE_ADDRESS, 255 .d_SOC_CORE_BASE_ADDRESS = SOC_CORE_BASE_ADDRESS, 256 .d_CORE_CTRL_ADDRESS = CORE_CTRL_ADDRESS, 257 .d_CE_COUNT = CE_COUNT, 258 .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, 259 .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, 260 .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, 261 .d_PCIE_INTR_ENABLE_ADDRESS = PCIE_INTR_ENABLE_ADDRESS, 262 .d_PCIE_INTR_CLR_ADDRESS = PCIE_INTR_CLR_ADDRESS, 263 .d_PCIE_INTR_FIRMWARE_MASK = PCIE_INTR_FIRMWARE_MASK, 264 .d_PCIE_INTR_CE_MASK_ALL = PCIE_INTR_CE_MASK_ALL, 265 .d_CORE_CTRL_CPU_INTR_MASK = CORE_CTRL_CPU_INTR_MASK, 266 .d_WIFICMN_PCIE_BAR_REG_ADDRESS = WIFICMN_PCIE_BAR_REG_ADDRESS, 267 /* htt_rx.c */ 268 /* htt tx */ 269 .d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 270 = MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK, 271 .d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 272 = MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK, 273 .d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 274 = MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK, 275 .d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 276 = MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK, 277 .d_MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 278 = MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB, 279 .d_MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 280 = MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB, 281 .d_MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 282 = MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB, 283 .d_MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 284 = MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB, 285 /* copy_engine.c */ 286 .d_SR_WR_INDEX_ADDRESS = SR_WR_INDEX_ADDRESS, 287 .d_DST_WATERMARK_ADDRESS = DST_WATERMARK_ADDRESS, 288 289 .d_PCIE_INTR_CAUSE_ADDRESS = PCIE_INTR_CAUSE_ADDRESS, 290 .d_SOC_RESET_CONTROL_ADDRESS = SOC_RESET_CONTROL_ADDRESS, 291 .d_SOC_RESET_CONTROL_CE_RST_MASK = SOC_RESET_CONTROL_CE_RST_MASK, 292 .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 293 = SOC_RESET_CONTROL_CPU_WARM_RST_MASK, 294 .d_CPU_INTR_ADDRESS = CPU_INTR_ADDRESS, 295 .d_SOC_LF_TIMER_CONTROL0_ADDRESS = SOC_LF_TIMER_CONTROL0_ADDRESS, 296 .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 297 = SOC_LF_TIMER_CONTROL0_ENABLE_MASK, 298 .d_SOC_LF_TIMER_STATUS0_ADDRESS = SOC_LF_TIMER_STATUS0_ADDRESS, 299 .d_SI_CONFIG_ERR_INT_MASK = SI_CONFIG_ERR_INT_MASK, 300 .d_SI_CONFIG_ERR_INT_LSB = SI_CONFIG_ERR_INT_LSB, 301 .d_GPIO_ENABLE_W1TS_LOW_ADDRESS = GPIO_ENABLE_W1TS_LOW_ADDRESS, 302 .d_GPIO_PIN0_CONFIG_LSB = GPIO_PIN0_CONFIG_LSB, 303 .d_GPIO_PIN0_PAD_PULL_LSB = GPIO_PIN0_PAD_PULL_LSB, 304 .d_GPIO_PIN0_PAD_PULL_MASK = GPIO_PIN0_PAD_PULL_MASK, 305 .d_SOC_CHIP_ID_ADDRESS = SOC_CHIP_ID_ADDRESS, 306 .d_SOC_CHIP_ID_REVISION_MASK = SOC_CHIP_ID_REVISION_MASK, 307 .d_SOC_CHIP_ID_REVISION_LSB = SOC_CHIP_ID_REVISION_LSB, 308 .d_SOC_CHIP_ID_REVISION_MSB = SOC_CHIP_ID_REVISION_MSB, 309 .d_WIFICMN_PCIE_BAR_REG_ADDRESS = WIFICMN_PCIE_BAR_REG_ADDRESS, 310 .d_FW_AXI_MSI_ADDR = FW_AXI_MSI_ADDR, 311 .d_FW_AXI_MSI_DATA = FW_AXI_MSI_DATA, 312 .d_WLAN_SUBSYSTEM_CORE_ID_ADDRESS = WLAN_SUBSYSTEM_CORE_ID_ADDRESS, 313 .d_WIFICMN_INT_STATUS_ADDRESS = WIFICMN_INT_STATUS_ADDRESS, 314 }; 315 316 struct targetdef_s *MY_TARGET_DEF = &my_target_def; 317 #else 318 #endif 319 320 #if defined(MY_CEREG_DEF) 321 322 #if !defined(CE_DDR_ADDRESS_FOR_RRI_LOW) 323 #define CE_DDR_ADDRESS_FOR_RRI_LOW ATH_UNSUPPORTED_REG_OFFSET 324 #endif 325 #if !defined(CE_DDR_ADDRESS_FOR_RRI_HIGH) 326 #define CE_DDR_ADDRESS_FOR_RRI_HIGH ATH_UNSUPPORTED_REG_OFFSET 327 #endif 328 #if !defined(SR_BA_ADDRESS_HIGH) 329 #define SR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET 330 #endif 331 #if !defined(DR_BA_ADDRESS_HIGH) 332 #define DR_BA_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET 333 #endif 334 #if !defined(CE_CMD_REGISTER) 335 #define CE_CMD_REGISTER ATH_UNSUPPORTED_REG_OFFSET 336 #endif 337 #if !defined(CE_MSI_ADDRESS) 338 #define CE_MSI_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 339 #endif 340 #if !defined(CE_MSI_ADDRESS_HIGH) 341 #define CE_MSI_ADDRESS_HIGH ATH_UNSUPPORTED_REG_OFFSET 342 #endif 343 #if !defined(CE_MSI_DATA) 344 #define CE_MSI_DATA ATH_UNSUPPORTED_REG_OFFSET 345 #endif 346 #if !defined(CE_MSI_ENABLE_BIT) 347 #define CE_MSI_ENABLE_BIT ATH_UNSUPPORTED_REG_OFFSET 348 #endif 349 #if !defined(CE_CTRL1_IDX_UPD_EN_MASK) 350 #define CE_CTRL1_IDX_UPD_EN_MASK ATH_UNSUPPORTED_REG_OFFSET 351 #endif 352 #if !defined(CE_WRAPPER_DEBUG_OFFSET) 353 #define CE_WRAPPER_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET 354 #endif 355 #if !defined(CE_DEBUG_OFFSET) 356 #define CE_DEBUG_OFFSET ATH_UNSUPPORTED_REG_OFFSET 357 #endif 358 #if !defined(A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES) 359 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES ATH_UNSUPPORTED_REG_OFFSET 360 #endif 361 #if !defined(A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS) 362 #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS ATH_UNSUPPORTED_REG_OFFSET 363 #endif 364 #if !defined(HOST_IE_ADDRESS_2) 365 #define HOST_IE_ADDRESS_2 ATH_UNSUPPORTED_REG_OFFSET 366 #endif 367 #if !defined(HOST_IE_ADDRESS_3) 368 #define HOST_IE_ADDRESS_3 ATH_UNSUPPORTED_REG_OFFSET 369 #endif 370 #if !defined(HOST_IE_REG1_CE_LSB) 371 #define HOST_IE_REG1_CE_LSB 0 372 #endif 373 #if !defined(HOST_IE_REG2_CE_LSB) 374 #define HOST_IE_REG2_CE_LSB 0 375 #endif 376 #if !defined(HOST_IE_REG3_CE_LSB) 377 #define HOST_IE_REG3_CE_LSB 0 378 #endif 379 #if !defined(HOST_CE_ADDRESS) 380 #define HOST_CE_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 381 #endif 382 #if !defined(HOST_CMEM_ADDRESS) 383 #define HOST_CMEM_ADDRESS ATH_UNSUPPORTED_REG_OFFSET 384 #endif 385 #if !defined(PMM_SCRATCH_BASE) 386 #define PMM_SCRATCH_BASE ATH_UNSUPPORTED_REG_OFFSET 387 #endif 388 389 390 391 static struct ce_reg_def my_ce_reg_def = { 392 /* copy_engine.c */ 393 .d_DST_WR_INDEX_ADDRESS = DST_WR_INDEX_ADDRESS, 394 .d_SRC_WATERMARK_ADDRESS = SRC_WATERMARK_ADDRESS, 395 .d_SRC_WATERMARK_LOW_MASK = SRC_WATERMARK_LOW_MASK, 396 .d_SRC_WATERMARK_HIGH_MASK = SRC_WATERMARK_HIGH_MASK, 397 .d_DST_WATERMARK_LOW_MASK = DST_WATERMARK_LOW_MASK, 398 .d_DST_WATERMARK_HIGH_MASK = DST_WATERMARK_HIGH_MASK, 399 .d_CURRENT_SRRI_ADDRESS = CURRENT_SRRI_ADDRESS, 400 .d_CURRENT_DRRI_ADDRESS = CURRENT_DRRI_ADDRESS, 401 .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 402 = HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, 403 .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 404 = HOST_IS_SRC_RING_LOW_WATERMARK_MASK, 405 .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 406 = HOST_IS_DST_RING_HIGH_WATERMARK_MASK, 407 .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK 408 = HOST_IS_DST_RING_LOW_WATERMARK_MASK, 409 .d_HOST_IS_ADDRESS = HOST_IS_ADDRESS, 410 .d_MISC_IS_ADDRESS = MISC_IS_ADDRESS, 411 .d_HOST_IS_COPY_COMPLETE_MASK = HOST_IS_COPY_COMPLETE_MASK, 412 .d_CE_WRAPPER_BASE_ADDRESS = CE_WRAPPER_BASE_ADDRESS, 413 .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 414 = CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, 415 .d_CE_DDR_ADDRESS_FOR_RRI_LOW = CE_DDR_ADDRESS_FOR_RRI_LOW, 416 .d_CE_DDR_ADDRESS_FOR_RRI_HIGH = CE_DDR_ADDRESS_FOR_RRI_HIGH, 417 .d_HOST_IE_ADDRESS = HOST_IE_ADDRESS, 418 .d_HOST_IE_REG1_CE_LSB = HOST_IE_REG1_CE_LSB, 419 .d_HOST_IE_ADDRESS_2 = HOST_IE_ADDRESS_2, 420 .d_HOST_IE_REG2_CE_LSB = HOST_IE_REG2_CE_LSB, 421 .d_HOST_IE_ADDRESS_3 = HOST_IE_ADDRESS_3, 422 .d_HOST_IE_REG3_CE_LSB = HOST_IE_REG3_CE_LSB, 423 .d_HOST_IE_COPY_COMPLETE_MASK = HOST_IE_COPY_COMPLETE_MASK, 424 .d_SR_BA_ADDRESS = SR_BA_ADDRESS, 425 .d_SR_BA_ADDRESS_HIGH = SR_BA_ADDRESS_HIGH, 426 .d_SR_SIZE_ADDRESS = SR_SIZE_ADDRESS, 427 .d_CE_CTRL1_ADDRESS = CE_CTRL1_ADDRESS, 428 .d_CE_CTRL1_DMAX_LENGTH_MASK = CE_CTRL1_DMAX_LENGTH_MASK, 429 .d_DR_BA_ADDRESS = DR_BA_ADDRESS, 430 .d_DR_BA_ADDRESS_HIGH = DR_BA_ADDRESS_HIGH, 431 .d_DR_SIZE_ADDRESS = DR_SIZE_ADDRESS, 432 .d_CE_CMD_REGISTER = CE_CMD_REGISTER, 433 .d_CE_MSI_ADDRESS = CE_MSI_ADDRESS, 434 .d_CE_MSI_ADDRESS_HIGH = CE_MSI_ADDRESS_HIGH, 435 .d_CE_MSI_DATA = CE_MSI_DATA, 436 .d_CE_MSI_ENABLE_BIT = CE_MSI_ENABLE_BIT, 437 .d_MISC_IE_ADDRESS = MISC_IE_ADDRESS, 438 .d_MISC_IS_AXI_ERR_MASK = MISC_IS_AXI_ERR_MASK, 439 .d_MISC_IS_DST_ADDR_ERR_MASK = MISC_IS_DST_ADDR_ERR_MASK, 440 .d_MISC_IS_SRC_LEN_ERR_MASK = MISC_IS_SRC_LEN_ERR_MASK, 441 .d_MISC_IS_DST_MAX_LEN_VIO_MASK = MISC_IS_DST_MAX_LEN_VIO_MASK, 442 .d_MISC_IS_DST_RING_OVERFLOW_MASK = MISC_IS_DST_RING_OVERFLOW_MASK, 443 .d_MISC_IS_SRC_RING_OVERFLOW_MASK = MISC_IS_SRC_RING_OVERFLOW_MASK, 444 .d_SRC_WATERMARK_LOW_LSB = SRC_WATERMARK_LOW_LSB, 445 .d_SRC_WATERMARK_HIGH_LSB = SRC_WATERMARK_HIGH_LSB, 446 .d_DST_WATERMARK_LOW_LSB = DST_WATERMARK_LOW_LSB, 447 .d_DST_WATERMARK_HIGH_LSB = DST_WATERMARK_HIGH_LSB, 448 .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 449 = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, 450 .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 451 = CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, 452 .d_CE_CTRL1_DMAX_LENGTH_LSB = CE_CTRL1_DMAX_LENGTH_LSB, 453 .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 454 = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, 455 .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 456 = CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, 457 .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 458 = CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, 459 .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 460 = CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, 461 .d_CE_CTRL1_IDX_UPD_EN_MASK = CE_CTRL1_IDX_UPD_EN_MASK, 462 .d_CE_WRAPPER_DEBUG_OFFSET = CE_WRAPPER_DEBUG_OFFSET, 463 .d_CE_WRAPPER_DEBUG_SEL_MSB = CE_WRAPPER_DEBUG_SEL_MSB, 464 .d_CE_WRAPPER_DEBUG_SEL_LSB = CE_WRAPPER_DEBUG_SEL_LSB, 465 .d_CE_WRAPPER_DEBUG_SEL_MASK = CE_WRAPPER_DEBUG_SEL_MASK, 466 .d_CE_DEBUG_OFFSET = CE_DEBUG_OFFSET, 467 .d_CE_DEBUG_SEL_MSB = CE_DEBUG_SEL_MSB, 468 .d_CE_DEBUG_SEL_LSB = CE_DEBUG_SEL_LSB, 469 .d_CE_DEBUG_SEL_MASK = CE_DEBUG_SEL_MASK, 470 .d_CE0_BASE_ADDRESS = CE0_BASE_ADDRESS, 471 .d_CE1_BASE_ADDRESS = CE1_BASE_ADDRESS, 472 .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES 473 = A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES, 474 .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS 475 = A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS, 476 .d_HOST_CE_ADDRESS = HOST_CE_ADDRESS, 477 .d_HOST_CMEM_ADDRESS = HOST_CMEM_ADDRESS, 478 .d_PMM_SCRATCH_BASE = PMM_SCRATCH_BASE 479 }; 480 481 struct ce_reg_def *MY_CEREG_DEF = &my_ce_reg_def; 482 483 #else 484 #endif 485 #endif 486