xref: /wlan-driver/platform/cnss2/power.c (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/of.h>
10 #include <linux/of_gpio.h>
11 #include <linux/pinctrl/consumer.h>
12 #include <linux/pinctrl/qcom-pinctrl.h>
13 #include <linux/regulator/consumer.h>
14 #if IS_ENABLED(CONFIG_QCOM_COMMAND_DB)
15 #include <soc/qcom/cmd-db.h>
16 #endif
17 
18 #include "main.h"
19 #include "debug.h"
20 #include "bus.h"
21 #include <linux/soc/qcom/qcom_aoss.h>
22 
23 #if IS_ENABLED(CONFIG_ARCH_QCOM)
24 static struct cnss_vreg_cfg cnss_vreg_list[] = {
25 	{"vdd-wlan-m2", 3300000, 3300000, 0, 0, 0},
26 	{"vdd-wlan-core", 1300000, 1300000, 0, 0, 0},
27 	{"vdd-wlan-io", 1800000, 1800000, 0, 0, 0},
28 	{"vdd-wlan-io12", 1200000, 1200000, 0, 0, 0},
29 	{"vdd-wlan-ant-share", 1800000, 1800000, 0, 0, 0},
30 	{"vdd-wlan-xtal-aon", 0, 0, 0, 0, 0},
31 	{"vdd-wlan-xtal", 1800000, 1800000, 0, 2, 0},
32 	{"vdd-wlan", 0, 0, 0, 0, 0},
33 	{"vdd-wlan-ctrl1", 0, 0, 0, 0, 0},
34 	{"vdd-wlan-ctrl2", 0, 0, 0, 0, 0},
35 	{"vdd-wlan-sp2t", 2700000, 2700000, 0, 0, 0},
36 	{"wlan-ant-switch", 1800000, 1800000, 0, 0, 0},
37 	{"wlan-soc-swreg", 1200000, 1200000, 0, 0, 0},
38 	{"vdd-wlan-aon", 950000, 950000, 0, 0, 0},
39 	{"vdd-wlan-dig", 950000, 952000, 0, 0, 0},
40 	{"vdd-wlan-rfa1", 1900000, 1900000, 0, 0, 0},
41 	{"vdd-wlan-rfa2", 1350000, 1350000, 0, 0, 0},
42 	{"vdd-wlan-rfa3", 1900000, 1900000, 450000, 0, 0},
43 	{"alt-sleep-clk", 0, 0, 0, 0, 0},
44 	{"vdd-wlan-en", 0, 0, 0, 10, 0},
45 };
46 
47 static struct cnss_clk_cfg cnss_clk_list[] = {
48 	{"rf_clk", 0, 0},
49 };
50 #else
51 static struct cnss_vreg_cfg cnss_vreg_list[] = {
52 };
53 
54 static struct cnss_clk_cfg cnss_clk_list[] = {
55 };
56 #endif
57 
58 #define CNSS_VREG_INFO_SIZE		ARRAY_SIZE(cnss_vreg_list)
59 #define CNSS_CLK_INFO_SIZE		ARRAY_SIZE(cnss_clk_list)
60 #define MAX_PROP_SIZE			32
61 
62 #define BOOTSTRAP_GPIO			"qcom,enable-bootstrap-gpio"
63 #define BOOTSTRAP_ACTIVE		"bootstrap_active"
64 #define HOST_SOL_GPIO			"wlan-host-sol-gpio"
65 #define DEV_SOL_GPIO			"wlan-dev-sol-gpio"
66 #define SOL_DEFAULT			"sol_default"
67 #define WLAN_EN_GPIO			"wlan-en-gpio"
68 #define BT_EN_GPIO			"qcom,bt-en-gpio"
69 #define XO_CLK_GPIO			"qcom,xo-clk-gpio"
70 #define SW_CTRL_GPIO			"qcom,sw-ctrl-gpio"
71 #define WLAN_SW_CTRL_GPIO		"qcom,wlan-sw-ctrl-gpio"
72 #define WLAN_EN_ACTIVE			"wlan_en_active"
73 #define WLAN_EN_SLEEP			"wlan_en_sleep"
74 #define WLAN_VREGS_PROP			"wlan_vregs"
75 
76 /* unit us */
77 #define BOOTSTRAP_DELAY			1000
78 #define WLAN_ENABLE_DELAY		1000
79 /* unit ms */
80 #define WLAN_ENABLE_DELAY_ROME		10
81 
82 #define TCS_CMD_DATA_ADDR_OFFSET	0x4
83 #define TCS_OFFSET			0xC8
84 #define TCS_CMD_OFFSET			0x10
85 #define MAX_TCS_NUM			8
86 #define MAX_TCS_CMD_NUM			5
87 #define BT_CXMX_VOLTAGE_MV		950
88 #define CNSS_MBOX_MSG_MAX_LEN 64
89 #define CNSS_MBOX_TIMEOUT_MS 1000
90 /* Platform HW config */
91 #define CNSS_PMIC_VOLTAGE_STEP 4
92 #define CNSS_PMIC_AUTO_HEADROOM 16
93 #define CNSS_IR_DROP_WAKE 30
94 #define CNSS_IR_DROP_SLEEP 10
95 #define VREG_NOTFOUND 1
96 
97 /**
98  * enum cnss_aop_vreg_param: Voltage regulator TCS param
99  * @CNSS_VREG_VOLTAGE: Provides voltage level in mV to be configured in TCS
100  * @CNSS_VREG_MODE: Regulator mode
101  * @CNSS_VREG_TCS_ENABLE: Set bool Voltage regulator enable config in TCS.
102  */
103 enum cnss_aop_vreg_param {
104 	CNSS_VREG_VOLTAGE,
105 	CNSS_VREG_MODE,
106 	CNSS_VREG_ENABLE,
107 	CNSS_VREG_PARAM_MAX
108 };
109 
110 /** enum cnss_aop_vreg_param_mode: Voltage modes supported by AOP*/
111 enum cnss_aop_vreg_param_mode {
112 	CNSS_VREG_RET_MODE = 3,
113 	CNSS_VREG_LPM_MODE = 4,
114 	CNSS_VREG_AUTO_MODE = 6,
115 	CNSS_VREG_NPM_MODE = 7,
116 	CNSS_VREG_MODE_MAX
117 };
118 
119 /**
120  * enum cnss_aop_tcs_seq: TCS sequence ID for trigger
121  * @CNSS_TCS_UP_SEQ: TCS Sequence based on up trigger / Wake TCS
122  * @CNSS_TCS_DOWN_SEQ: TCS Sequence based on down trigger / Sleep TCS
123  * @CNSS_TCS_ENABLE_SEQ: Enable this TCS seq entry
124  */
125 enum cnss_aop_tcs_seq_param {
126 	CNSS_TCS_UP_SEQ,
127 	CNSS_TCS_DOWN_SEQ,
128 	CNSS_TCS_ENABLE_SEQ,
129 	CNSS_TCS_SEQ_MAX
130 };
131 
cnss_get_vreg_single(struct cnss_plat_data * plat_priv,struct cnss_vreg_info * vreg)132 static int cnss_get_vreg_single(struct cnss_plat_data *plat_priv,
133 				struct cnss_vreg_info *vreg)
134 {
135 	int ret = 0;
136 	struct device *dev;
137 	struct regulator *reg;
138 	const __be32 *prop;
139 	char prop_name[MAX_PROP_SIZE] = {0};
140 	int len;
141 	struct device_node *dt_node;
142 
143 	dev = &plat_priv->plat_dev->dev;
144 	dt_node = (plat_priv->dev_node ? plat_priv->dev_node : dev->of_node);
145 
146 	reg = devm_regulator_get_optional(dev, vreg->cfg.name);
147 	if (IS_ERR(reg)) {
148 		ret = PTR_ERR(reg);
149 		if (ret == -ENODEV)
150 			return ret;
151 		else if (ret == -EPROBE_DEFER)
152 			cnss_pr_info("EPROBE_DEFER for regulator: %s\n",
153 				     vreg->cfg.name);
154 		else
155 			cnss_pr_err("Failed to get regulator %s, err = %d\n",
156 				    vreg->cfg.name, ret);
157 		return ret;
158 	}
159 
160 	vreg->reg = reg;
161 
162 	snprintf(prop_name, MAX_PROP_SIZE, "qcom,%s-config",
163 		 vreg->cfg.name);
164 
165 	prop = of_get_property(dt_node, prop_name, &len);
166 	if (!prop || len != (5 * sizeof(__be32))) {
167 		cnss_pr_dbg("Property %s %s, use default\n", prop_name,
168 			    prop ? "invalid format" : "doesn't exist");
169 	} else {
170 		vreg->cfg.min_uv = be32_to_cpup(&prop[0]);
171 		vreg->cfg.max_uv = be32_to_cpup(&prop[1]);
172 		vreg->cfg.load_ua = be32_to_cpup(&prop[2]);
173 		vreg->cfg.delay_us = be32_to_cpup(&prop[3]);
174 		vreg->cfg.need_unvote = be32_to_cpup(&prop[4]);
175 	}
176 
177 	cnss_pr_dbg("Got regulator: %s, min_uv: %u, max_uv: %u, load_ua: %u, delay_us: %u, need_unvote: %u\n",
178 		    vreg->cfg.name, vreg->cfg.min_uv,
179 		    vreg->cfg.max_uv, vreg->cfg.load_ua,
180 		    vreg->cfg.delay_us, vreg->cfg.need_unvote);
181 
182 	return 0;
183 }
184 
cnss_put_vreg_single(struct cnss_plat_data * plat_priv,struct cnss_vreg_info * vreg)185 static void cnss_put_vreg_single(struct cnss_plat_data *plat_priv,
186 				 struct cnss_vreg_info *vreg)
187 {
188 	struct device *dev = &plat_priv->plat_dev->dev;
189 
190 	cnss_pr_dbg("Put regulator: %s\n", vreg->cfg.name);
191 	devm_regulator_put(vreg->reg);
192 	devm_kfree(dev, vreg);
193 }
194 
cnss_vreg_on_single(struct cnss_vreg_info * vreg)195 static int cnss_vreg_on_single(struct cnss_vreg_info *vreg)
196 {
197 	int ret = 0;
198 
199 	if (vreg->enabled) {
200 		cnss_pr_dbg("Regulator %s is already enabled\n",
201 			    vreg->cfg.name);
202 		return 0;
203 	}
204 
205 	cnss_pr_dbg("Regulator %s is being enabled\n", vreg->cfg.name);
206 
207 	if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
208 		ret = regulator_set_voltage(vreg->reg,
209 					    vreg->cfg.min_uv,
210 					    vreg->cfg.max_uv);
211 
212 		if (ret) {
213 			cnss_pr_err("Failed to set voltage for regulator %s, min_uv: %u, max_uv: %u, err = %d\n",
214 				    vreg->cfg.name, vreg->cfg.min_uv,
215 				    vreg->cfg.max_uv, ret);
216 			goto out;
217 		}
218 	}
219 
220 	if (vreg->cfg.load_ua) {
221 		ret = regulator_set_load(vreg->reg,
222 					 vreg->cfg.load_ua);
223 
224 		if (ret < 0) {
225 			cnss_pr_err("Failed to set load for regulator %s, load: %u, err = %d\n",
226 				    vreg->cfg.name, vreg->cfg.load_ua,
227 				    ret);
228 			goto out;
229 		}
230 	}
231 
232 	if (vreg->cfg.delay_us)
233 		udelay(vreg->cfg.delay_us);
234 
235 	ret = regulator_enable(vreg->reg);
236 	if (ret) {
237 		cnss_pr_err("Failed to enable regulator %s, err = %d\n",
238 			    vreg->cfg.name, ret);
239 		goto out;
240 	}
241 	vreg->enabled = true;
242 
243 out:
244 	return ret;
245 }
246 
cnss_vreg_unvote_single(struct cnss_vreg_info * vreg)247 static int cnss_vreg_unvote_single(struct cnss_vreg_info *vreg)
248 {
249 	int ret = 0;
250 
251 	if (!vreg->enabled) {
252 		cnss_pr_dbg("Regulator %s is already disabled\n",
253 			    vreg->cfg.name);
254 		return 0;
255 	}
256 
257 	cnss_pr_dbg("Removing vote for Regulator %s\n", vreg->cfg.name);
258 
259 	if (vreg->cfg.load_ua) {
260 		ret = regulator_set_load(vreg->reg, 0);
261 		if (ret < 0)
262 			cnss_pr_err("Failed to set load for regulator %s, err = %d\n",
263 				    vreg->cfg.name, ret);
264 	}
265 
266 	if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
267 		ret = regulator_set_voltage(vreg->reg, 0,
268 					    vreg->cfg.max_uv);
269 		if (ret)
270 			cnss_pr_err("Failed to set voltage for regulator %s, err = %d\n",
271 				    vreg->cfg.name, ret);
272 	}
273 
274 	return ret;
275 }
276 
cnss_vreg_off_single(struct cnss_vreg_info * vreg)277 static int cnss_vreg_off_single(struct cnss_vreg_info *vreg)
278 {
279 	int ret = 0;
280 
281 	if (!vreg->enabled) {
282 		cnss_pr_dbg("Regulator %s is already disabled\n",
283 			    vreg->cfg.name);
284 		return 0;
285 	}
286 
287 	cnss_pr_dbg("Regulator %s is being disabled\n",
288 		    vreg->cfg.name);
289 
290 	ret = regulator_disable(vreg->reg);
291 	if (ret)
292 		cnss_pr_err("Failed to disable regulator %s, err = %d\n",
293 			    vreg->cfg.name, ret);
294 
295 	if (vreg->cfg.load_ua) {
296 		ret = regulator_set_load(vreg->reg, 0);
297 		if (ret < 0)
298 			cnss_pr_err("Failed to set load for regulator %s, err = %d\n",
299 				    vreg->cfg.name, ret);
300 	}
301 
302 	if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
303 		ret = regulator_set_voltage(vreg->reg, 0,
304 					    vreg->cfg.max_uv);
305 		if (ret)
306 			cnss_pr_err("Failed to set voltage for regulator %s, err = %d\n",
307 				    vreg->cfg.name, ret);
308 	}
309 	vreg->enabled = false;
310 
311 	return ret;
312 }
313 
get_vreg_list(u32 * vreg_list_size,enum cnss_vreg_type type)314 static struct cnss_vreg_cfg *get_vreg_list(u32 *vreg_list_size,
315 					   enum cnss_vreg_type type)
316 {
317 	switch (type) {
318 	case CNSS_VREG_PRIM:
319 		*vreg_list_size = CNSS_VREG_INFO_SIZE;
320 		return cnss_vreg_list;
321 	default:
322 		cnss_pr_err("Unsupported vreg type 0x%x\n", type);
323 		*vreg_list_size = 0;
324 		return NULL;
325 	}
326 }
327 
328 /*
329  * For multi-exchg dt node, get the required vregs' names from property
330  * 'wlan_vregs', which is string array;
331  *
332  * If the property is not present or present but no value is set, then no
333  * additional wlan verg is required, function return VREG_NOTFOUND.
334  * If property is present with valid value, function return 0.
335  * Other cases a negative value is returned.
336  *
337  * For non-multi-exchg dt, go through all vregs in the static array
338  * 'cnss_vreg_list'.
339  */
cnss_get_vreg(struct cnss_plat_data * plat_priv,struct list_head * vreg_list,struct cnss_vreg_cfg * vreg_cfg,u32 vreg_list_size)340 static int cnss_get_vreg(struct cnss_plat_data *plat_priv,
341 			 struct list_head *vreg_list,
342 			 struct cnss_vreg_cfg *vreg_cfg,
343 			 u32 vreg_list_size)
344 {
345 	int ret = 0;
346 	int i;
347 	struct cnss_vreg_info *vreg;
348 	struct device *dev = &plat_priv->plat_dev->dev;
349 	int id_n;
350 	struct device_node *dt_node;
351 
352 	if (!list_empty(vreg_list) &&
353 	    (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG)) {
354 		cnss_pr_dbg("Vregs have already been updated\n");
355 		return 0;
356 	}
357 
358 	dt_node = (plat_priv->dev_node ? plat_priv->dev_node : dev->of_node);
359 	if (plat_priv->dt_type == CNSS_DTT_MULTIEXCHG) {
360 		id_n = of_property_count_strings(dt_node,
361 						 WLAN_VREGS_PROP);
362 		if (id_n <= 0) {
363 			if (id_n == -ENODATA || id_n == -EINVAL) {
364 				cnss_pr_dbg("No additional vregs for: %s:%lx\n",
365 					    dt_node->name,
366 					    plat_priv->device_id);
367 				/* By returning a positive value, give the caller a
368 				 * chance to know no additional regulator is needed
369 				 * by this device, and shall not treat this case as
370 				 * an error.
371 				 */
372 				return VREG_NOTFOUND;
373 			}
374 
375 			cnss_pr_err("property %s is invalid: %s:%lx\n",
376 				    WLAN_VREGS_PROP, dt_node->name,
377 				    plat_priv->device_id);
378 			return -EINVAL;
379 		}
380 	} else {
381 		id_n = vreg_list_size;
382 	}
383 
384 	for (i = 0; i < id_n; i++) {
385 		vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
386 		if (!vreg)
387 			return -ENOMEM;
388 
389 		if (plat_priv->dt_type == CNSS_DTT_MULTIEXCHG) {
390 			ret = of_property_read_string_index(dt_node,
391 							    WLAN_VREGS_PROP, i,
392 							    &vreg->cfg.name);
393 			if (ret) {
394 				cnss_pr_err("Failed to read vreg ids\n");
395 				return ret;
396 			}
397 		} else {
398 			memcpy(&vreg->cfg, &vreg_cfg[i], sizeof(vreg->cfg));
399 		}
400 
401 		ret = cnss_get_vreg_single(plat_priv, vreg);
402 		if (ret != 0) {
403 			if (ret == -ENODEV) {
404 				devm_kfree(dev, vreg);
405 				continue;
406 			} else {
407 				devm_kfree(dev, vreg);
408 				return ret;
409 			}
410 		}
411 		list_add_tail(&vreg->list, vreg_list);
412 	}
413 
414 	return 0;
415 }
416 
cnss_put_vreg(struct cnss_plat_data * plat_priv,struct list_head * vreg_list)417 static void cnss_put_vreg(struct cnss_plat_data *plat_priv,
418 			  struct list_head *vreg_list)
419 {
420 	struct cnss_vreg_info *vreg;
421 
422 	while (!list_empty(vreg_list)) {
423 		vreg = list_first_entry(vreg_list,
424 					struct cnss_vreg_info, list);
425 		list_del(&vreg->list);
426 		if (IS_ERR_OR_NULL(vreg->reg))
427 			continue;
428 		cnss_put_vreg_single(plat_priv, vreg);
429 	}
430 }
431 
cnss_vreg_on(struct cnss_plat_data * plat_priv,struct list_head * vreg_list)432 static int cnss_vreg_on(struct cnss_plat_data *plat_priv,
433 			struct list_head *vreg_list)
434 {
435 	struct cnss_vreg_info *vreg;
436 	int ret = 0;
437 
438 	list_for_each_entry(vreg, vreg_list, list) {
439 		if (IS_ERR_OR_NULL(vreg->reg))
440 			continue;
441 		ret = cnss_vreg_on_single(vreg);
442 		if (ret)
443 			break;
444 	}
445 
446 	if (!ret)
447 		return 0;
448 
449 	list_for_each_entry_continue_reverse(vreg, vreg_list, list) {
450 		if (IS_ERR_OR_NULL(vreg->reg) || !vreg->enabled)
451 			continue;
452 
453 		cnss_vreg_off_single(vreg);
454 	}
455 
456 	return ret;
457 }
458 
cnss_vreg_off(struct cnss_plat_data * plat_priv,struct list_head * vreg_list)459 static int cnss_vreg_off(struct cnss_plat_data *plat_priv,
460 			 struct list_head *vreg_list)
461 {
462 	struct cnss_vreg_info *vreg;
463 
464 	list_for_each_entry_reverse(vreg, vreg_list, list) {
465 		if (IS_ERR_OR_NULL(vreg->reg))
466 			continue;
467 
468 		cnss_vreg_off_single(vreg);
469 	}
470 
471 	return 0;
472 }
473 
cnss_vreg_unvote(struct cnss_plat_data * plat_priv,struct list_head * vreg_list)474 static int cnss_vreg_unvote(struct cnss_plat_data *plat_priv,
475 			    struct list_head *vreg_list)
476 {
477 	struct cnss_vreg_info *vreg;
478 
479 	list_for_each_entry_reverse(vreg, vreg_list, list) {
480 		if (IS_ERR_OR_NULL(vreg->reg))
481 			continue;
482 
483 		if (vreg->cfg.need_unvote)
484 			cnss_vreg_unvote_single(vreg);
485 	}
486 
487 	return 0;
488 }
489 
cnss_get_vreg_type(struct cnss_plat_data * plat_priv,enum cnss_vreg_type type)490 int cnss_get_vreg_type(struct cnss_plat_data *plat_priv,
491 		       enum cnss_vreg_type type)
492 {
493 	struct cnss_vreg_cfg *vreg_cfg;
494 	u32 vreg_list_size = 0;
495 	int ret = 0;
496 
497 	vreg_cfg = get_vreg_list(&vreg_list_size, type);
498 	if (!vreg_cfg)
499 		return -EINVAL;
500 
501 	switch (type) {
502 	case CNSS_VREG_PRIM:
503 		ret = cnss_get_vreg(plat_priv, &plat_priv->vreg_list,
504 				    vreg_cfg, vreg_list_size);
505 		break;
506 	default:
507 		cnss_pr_err("Unsupported vreg type 0x%x\n", type);
508 		return -EINVAL;
509 	}
510 
511 	return ret;
512 }
513 
cnss_put_vreg_type(struct cnss_plat_data * plat_priv,enum cnss_vreg_type type)514 void cnss_put_vreg_type(struct cnss_plat_data *plat_priv,
515 			enum cnss_vreg_type type)
516 {
517 	switch (type) {
518 	case CNSS_VREG_PRIM:
519 		cnss_put_vreg(plat_priv, &plat_priv->vreg_list);
520 		break;
521 	default:
522 		return;
523 	}
524 }
525 
cnss_vreg_on_type(struct cnss_plat_data * plat_priv,enum cnss_vreg_type type)526 int cnss_vreg_on_type(struct cnss_plat_data *plat_priv,
527 		      enum cnss_vreg_type type)
528 {
529 	int ret = 0;
530 
531 	switch (type) {
532 	case CNSS_VREG_PRIM:
533 		ret = cnss_vreg_on(plat_priv, &plat_priv->vreg_list);
534 		break;
535 	default:
536 		cnss_pr_err("Unsupported vreg type 0x%x\n", type);
537 		return -EINVAL;
538 	}
539 
540 	return ret;
541 }
542 
cnss_vreg_off_type(struct cnss_plat_data * plat_priv,enum cnss_vreg_type type)543 int cnss_vreg_off_type(struct cnss_plat_data *plat_priv,
544 		       enum cnss_vreg_type type)
545 {
546 	int ret = 0;
547 
548 	switch (type) {
549 	case CNSS_VREG_PRIM:
550 		ret = cnss_vreg_off(plat_priv, &plat_priv->vreg_list);
551 		break;
552 	default:
553 		cnss_pr_err("Unsupported vreg type 0x%x\n", type);
554 		return -EINVAL;
555 	}
556 
557 	return ret;
558 }
559 
cnss_vreg_unvote_type(struct cnss_plat_data * plat_priv,enum cnss_vreg_type type)560 int cnss_vreg_unvote_type(struct cnss_plat_data *plat_priv,
561 			  enum cnss_vreg_type type)
562 {
563 	int ret = 0;
564 
565 	switch (type) {
566 	case CNSS_VREG_PRIM:
567 		ret = cnss_vreg_unvote(plat_priv, &plat_priv->vreg_list);
568 		break;
569 	default:
570 		cnss_pr_err("Unsupported vreg type 0x%x\n", type);
571 		return -EINVAL;
572 	}
573 
574 	return ret;
575 }
576 
cnss_get_clk_single(struct cnss_plat_data * plat_priv,struct cnss_clk_info * clk_info)577 static int cnss_get_clk_single(struct cnss_plat_data *plat_priv,
578 			       struct cnss_clk_info *clk_info)
579 {
580 	struct device *dev = &plat_priv->plat_dev->dev;
581 	struct clk *clk;
582 	int ret;
583 
584 	clk = devm_clk_get(dev, clk_info->cfg.name);
585 	if (IS_ERR(clk)) {
586 		ret = PTR_ERR(clk);
587 		if (clk_info->cfg.required)
588 			cnss_pr_err("Failed to get clock %s, err = %d\n",
589 				    clk_info->cfg.name, ret);
590 		else
591 			cnss_pr_dbg("Failed to get optional clock %s, err = %d\n",
592 				    clk_info->cfg.name, ret);
593 		return ret;
594 	}
595 
596 	clk_info->clk = clk;
597 	cnss_pr_dbg("Got clock: %s, freq: %u\n",
598 		    clk_info->cfg.name, clk_info->cfg.freq);
599 
600 	return 0;
601 }
602 
cnss_put_clk_single(struct cnss_plat_data * plat_priv,struct cnss_clk_info * clk_info)603 static void cnss_put_clk_single(struct cnss_plat_data *plat_priv,
604 				struct cnss_clk_info *clk_info)
605 {
606 	struct device *dev = &plat_priv->plat_dev->dev;
607 
608 	cnss_pr_dbg("Put clock: %s\n", clk_info->cfg.name);
609 	devm_clk_put(dev, clk_info->clk);
610 }
611 
cnss_clk_on_single(struct cnss_clk_info * clk_info)612 static int cnss_clk_on_single(struct cnss_clk_info *clk_info)
613 {
614 	int ret;
615 
616 	if (clk_info->enabled) {
617 		cnss_pr_dbg("Clock %s is already enabled\n",
618 			    clk_info->cfg.name);
619 		return 0;
620 	}
621 
622 	cnss_pr_dbg("Clock %s is being enabled\n", clk_info->cfg.name);
623 
624 	if (clk_info->cfg.freq) {
625 		ret = clk_set_rate(clk_info->clk, clk_info->cfg.freq);
626 		if (ret) {
627 			cnss_pr_err("Failed to set frequency %u for clock %s, err = %d\n",
628 				    clk_info->cfg.freq, clk_info->cfg.name,
629 				    ret);
630 			return ret;
631 		}
632 	}
633 
634 	ret = clk_prepare_enable(clk_info->clk);
635 	if (ret) {
636 		cnss_pr_err("Failed to enable clock %s, err = %d\n",
637 			    clk_info->cfg.name, ret);
638 		return ret;
639 	}
640 
641 	clk_info->enabled = true;
642 
643 	return 0;
644 }
645 
cnss_clk_off_single(struct cnss_clk_info * clk_info)646 static int cnss_clk_off_single(struct cnss_clk_info *clk_info)
647 {
648 	if (!clk_info->enabled) {
649 		cnss_pr_dbg("Clock %s is already disabled\n",
650 			    clk_info->cfg.name);
651 		return 0;
652 	}
653 
654 	cnss_pr_dbg("Clock %s is being disabled\n", clk_info->cfg.name);
655 
656 	clk_disable_unprepare(clk_info->clk);
657 	clk_info->enabled = false;
658 
659 	return 0;
660 }
661 
cnss_get_clk(struct cnss_plat_data * plat_priv)662 int cnss_get_clk(struct cnss_plat_data *plat_priv)
663 {
664 	struct device *dev;
665 	struct list_head *clk_list;
666 	struct cnss_clk_info *clk_info;
667 	int ret, i;
668 
669 	if (!plat_priv)
670 		return -ENODEV;
671 
672 	dev = &plat_priv->plat_dev->dev;
673 	clk_list = &plat_priv->clk_list;
674 
675 	if (!list_empty(clk_list)) {
676 		cnss_pr_dbg("Clocks have already been updated\n");
677 		return 0;
678 	}
679 
680 	for (i = 0; i < CNSS_CLK_INFO_SIZE; i++) {
681 		clk_info = devm_kzalloc(dev, sizeof(*clk_info), GFP_KERNEL);
682 		if (!clk_info) {
683 			ret = -ENOMEM;
684 			goto cleanup;
685 		}
686 
687 		memcpy(&clk_info->cfg, &cnss_clk_list[i],
688 		       sizeof(clk_info->cfg));
689 		ret = cnss_get_clk_single(plat_priv, clk_info);
690 		if (ret != 0) {
691 			if (clk_info->cfg.required) {
692 				devm_kfree(dev, clk_info);
693 				goto cleanup;
694 			} else {
695 				devm_kfree(dev, clk_info);
696 				continue;
697 			}
698 		}
699 		list_add_tail(&clk_info->list, clk_list);
700 	}
701 
702 	return 0;
703 
704 cleanup:
705 	while (!list_empty(clk_list)) {
706 		clk_info = list_first_entry(clk_list, struct cnss_clk_info,
707 					    list);
708 		list_del(&clk_info->list);
709 		if (IS_ERR_OR_NULL(clk_info->clk))
710 			continue;
711 		cnss_put_clk_single(plat_priv, clk_info);
712 		devm_kfree(dev, clk_info);
713 	}
714 
715 	return ret;
716 }
717 
cnss_put_clk(struct cnss_plat_data * plat_priv)718 void cnss_put_clk(struct cnss_plat_data *plat_priv)
719 {
720 	struct device *dev;
721 	struct list_head *clk_list;
722 	struct cnss_clk_info *clk_info;
723 
724 	if (!plat_priv)
725 		return;
726 
727 	dev = &plat_priv->plat_dev->dev;
728 	clk_list = &plat_priv->clk_list;
729 
730 	while (!list_empty(clk_list)) {
731 		clk_info = list_first_entry(clk_list, struct cnss_clk_info,
732 					    list);
733 		list_del(&clk_info->list);
734 		if (IS_ERR_OR_NULL(clk_info->clk))
735 			continue;
736 		cnss_put_clk_single(plat_priv, clk_info);
737 		devm_kfree(dev, clk_info);
738 	}
739 }
740 
cnss_clk_on(struct cnss_plat_data * plat_priv,struct list_head * clk_list)741 static int cnss_clk_on(struct cnss_plat_data *plat_priv,
742 		       struct list_head *clk_list)
743 {
744 	struct cnss_clk_info *clk_info;
745 	int ret = 0;
746 
747 	list_for_each_entry(clk_info, clk_list, list) {
748 		if (IS_ERR_OR_NULL(clk_info->clk))
749 			continue;
750 		ret = cnss_clk_on_single(clk_info);
751 		if (ret)
752 			break;
753 	}
754 
755 	if (!ret)
756 		return 0;
757 
758 	list_for_each_entry_continue_reverse(clk_info, clk_list, list) {
759 		if (IS_ERR_OR_NULL(clk_info->clk))
760 			continue;
761 
762 		cnss_clk_off_single(clk_info);
763 	}
764 
765 	return ret;
766 }
767 
cnss_clk_off(struct cnss_plat_data * plat_priv,struct list_head * clk_list)768 static int cnss_clk_off(struct cnss_plat_data *plat_priv,
769 			struct list_head *clk_list)
770 {
771 	struct cnss_clk_info *clk_info;
772 
773 	list_for_each_entry_reverse(clk_info, clk_list, list) {
774 		if (IS_ERR_OR_NULL(clk_info->clk))
775 			continue;
776 
777 		cnss_clk_off_single(clk_info);
778 	}
779 
780 	return 0;
781 }
782 
cnss_get_pinctrl(struct cnss_plat_data * plat_priv)783 int cnss_get_pinctrl(struct cnss_plat_data *plat_priv)
784 {
785 	int ret = 0;
786 	struct device *dev;
787 	struct cnss_pinctrl_info *pinctrl_info;
788 	u32 gpio_id, i;
789 	int gpio_id_n;
790 
791 	dev = &plat_priv->plat_dev->dev;
792 	pinctrl_info = &plat_priv->pinctrl_info;
793 
794 	pinctrl_info->pinctrl = devm_pinctrl_get(dev);
795 	if (IS_ERR_OR_NULL(pinctrl_info->pinctrl)) {
796 		ret = PTR_ERR(pinctrl_info->pinctrl);
797 		cnss_pr_err("Failed to get pinctrl, err = %d\n", ret);
798 		goto out;
799 	}
800 
801 	if (of_find_property(dev->of_node, BOOTSTRAP_GPIO, NULL)) {
802 		pinctrl_info->bootstrap_active =
803 			pinctrl_lookup_state(pinctrl_info->pinctrl,
804 					     BOOTSTRAP_ACTIVE);
805 		if (IS_ERR_OR_NULL(pinctrl_info->bootstrap_active)) {
806 			ret = PTR_ERR(pinctrl_info->bootstrap_active);
807 			cnss_pr_err("Failed to get bootstrap active state, err = %d\n",
808 				    ret);
809 			goto out;
810 		}
811 	}
812 
813 	if (of_find_property(dev->of_node, HOST_SOL_GPIO, NULL) &&
814 	    of_find_property(dev->of_node, DEV_SOL_GPIO, NULL)) {
815 		pinctrl_info->sol_default =
816 			pinctrl_lookup_state(pinctrl_info->pinctrl,
817 					     SOL_DEFAULT);
818 		if (IS_ERR_OR_NULL(pinctrl_info->sol_default)) {
819 			ret = PTR_ERR(pinctrl_info->sol_default);
820 			cnss_pr_err("Failed to get sol default state, err = %d\n",
821 				    ret);
822 			goto out;
823 		}
824 		cnss_pr_dbg("Got sol default state\n");
825 	}
826 
827 	if (of_find_property(dev->of_node, WLAN_EN_GPIO, NULL)) {
828 		pinctrl_info->wlan_en_gpio = of_get_named_gpio(dev->of_node,
829 							       WLAN_EN_GPIO, 0);
830 		cnss_pr_dbg("WLAN_EN GPIO: %d\n", pinctrl_info->wlan_en_gpio);
831 		pinctrl_info->wlan_en_active =
832 			pinctrl_lookup_state(pinctrl_info->pinctrl,
833 					     WLAN_EN_ACTIVE);
834 		if (IS_ERR_OR_NULL(pinctrl_info->wlan_en_active)) {
835 			ret = PTR_ERR(pinctrl_info->wlan_en_active);
836 			cnss_pr_err("Failed to get wlan_en active state, err = %d\n",
837 				    ret);
838 			goto out;
839 		}
840 
841 		pinctrl_info->wlan_en_sleep =
842 			pinctrl_lookup_state(pinctrl_info->pinctrl,
843 					     WLAN_EN_SLEEP);
844 		if (IS_ERR_OR_NULL(pinctrl_info->wlan_en_sleep)) {
845 			ret = PTR_ERR(pinctrl_info->wlan_en_sleep);
846 			cnss_pr_err("Failed to get wlan_en sleep state, err = %d\n",
847 				    ret);
848 			goto out;
849 		}
850 
851 		cnss_set_feature_list(plat_priv, CNSS_WLAN_EN_SUPPORT_V01);
852 	} else {
853 		pinctrl_info->wlan_en_gpio = -EINVAL;
854 	}
855 
856 	/* Added for QCA6490 PMU delayed WLAN_EN_GPIO */
857 	if (of_find_property(dev->of_node, BT_EN_GPIO, NULL)) {
858 		pinctrl_info->bt_en_gpio = of_get_named_gpio(dev->of_node,
859 							     BT_EN_GPIO, 0);
860 		cnss_pr_dbg("BT GPIO: %d\n", pinctrl_info->bt_en_gpio);
861 	} else {
862 		pinctrl_info->bt_en_gpio = -EINVAL;
863 	}
864 
865 	/* Added for QCA6490 to minimize XO CLK selection leakage prevention */
866 	if (of_find_property(dev->of_node, XO_CLK_GPIO, NULL)) {
867 		pinctrl_info->xo_clk_gpio = of_get_named_gpio(dev->of_node,
868 							      XO_CLK_GPIO, 0);
869 		cnss_pr_dbg("QCA6490 XO_CLK GPIO: %d\n",
870 			    pinctrl_info->xo_clk_gpio);
871 		cnss_set_feature_list(plat_priv, BOOTSTRAP_CLOCK_SELECT_V01);
872 	} else {
873 		pinctrl_info->xo_clk_gpio = -EINVAL;
874 	}
875 
876 	if (of_find_property(dev->of_node, SW_CTRL_GPIO, NULL)) {
877 		pinctrl_info->sw_ctrl_gpio = of_get_named_gpio(dev->of_node,
878 							       SW_CTRL_GPIO,
879 							       0);
880 		cnss_pr_dbg("Switch control GPIO: %d\n",
881 			    pinctrl_info->sw_ctrl_gpio);
882 
883 		pinctrl_info->sw_ctrl =
884 			pinctrl_lookup_state(pinctrl_info->pinctrl,
885 					     "sw_ctrl");
886 		if (IS_ERR_OR_NULL(pinctrl_info->sw_ctrl)) {
887 			ret = PTR_ERR(pinctrl_info->sw_ctrl);
888 			cnss_pr_dbg("Failed to get sw_ctrl state, err = %d\n",
889 				    ret);
890 		} else {
891 			ret = pinctrl_select_state(pinctrl_info->pinctrl,
892 						   pinctrl_info->sw_ctrl);
893 			if (ret)
894 				cnss_pr_err("Failed to select sw_ctrl state, err = %d\n",
895 					    ret);
896 		}
897 	} else {
898 		pinctrl_info->sw_ctrl_gpio = -EINVAL;
899 	}
900 
901 	if (of_find_property(dev->of_node, WLAN_SW_CTRL_GPIO, NULL)) {
902 		pinctrl_info->sw_ctrl_wl_cx =
903 			pinctrl_lookup_state(pinctrl_info->pinctrl,
904 					     "sw_ctrl_wl_cx");
905 		if (IS_ERR_OR_NULL(pinctrl_info->sw_ctrl_wl_cx)) {
906 			ret = PTR_ERR(pinctrl_info->sw_ctrl_wl_cx);
907 			cnss_pr_dbg("Failed to get sw_ctrl_wl_cx state, err = %d\n",
908 				    ret);
909 		} else {
910 
911 			ret = pinctrl_select_state(pinctrl_info->pinctrl,
912 						   pinctrl_info->sw_ctrl_wl_cx);
913 			if (ret)
914 				cnss_pr_err("Failed to select sw_ctrl_wl_cx state, err = %d\n",
915 					    ret);
916 		}
917 	}
918 
919 	/* Find out and configure all those GPIOs which need to be setup
920 	 * for interrupt wakeup capable
921 	 */
922 	gpio_id_n = of_property_count_u32_elems(dev->of_node, "mpm_wake_set_gpios");
923 	if (gpio_id_n > 0) {
924 		cnss_pr_dbg("Num of GPIOs to be setup for interrupt wakeup capable: %d\n",
925 			    gpio_id_n);
926 		for (i = 0; i < gpio_id_n; i++) {
927 			ret = of_property_read_u32_index(dev->of_node,
928 							 "mpm_wake_set_gpios",
929 							 i, &gpio_id);
930 			if (ret) {
931 				cnss_pr_err("Failed to read gpio_id at index: %d\n", i);
932 				continue;
933 			}
934 
935 			ret = msm_gpio_mpm_wake_set(gpio_id, 1);
936 			if (ret < 0) {
937 				cnss_pr_err("Failed to setup gpio_id: %d as interrupt wakeup capable, ret: %d\n",
938 					    ret);
939 			} else {
940 				cnss_pr_dbg("gpio_id: %d successfully setup for interrupt wakeup capable\n",
941 					    gpio_id);
942 			}
943 		}
944 	} else {
945 		cnss_pr_dbg("No GPIOs to be setup for interrupt wakeup capable\n");
946 	}
947 
948 	return 0;
949 out:
950 	return ret;
951 }
952 
cnss_get_wlan_sw_ctrl(struct cnss_plat_data * plat_priv)953 int cnss_get_wlan_sw_ctrl(struct cnss_plat_data *plat_priv)
954 {
955 	struct device *dev;
956 	struct cnss_pinctrl_info *pinctrl_info;
957 
958 	dev = &plat_priv->plat_dev->dev;
959 	pinctrl_info = &plat_priv->pinctrl_info;
960 
961 	if (of_find_property(dev->of_node, WLAN_SW_CTRL_GPIO, NULL)) {
962 		pinctrl_info->wlan_sw_ctrl_gpio = of_get_named_gpio(dev->of_node,
963 								    WLAN_SW_CTRL_GPIO,
964 								    0);
965 		cnss_pr_dbg("WLAN Switch control GPIO: %d\n",
966 			    pinctrl_info->wlan_sw_ctrl_gpio);
967 	} else {
968 		pinctrl_info->wlan_sw_ctrl_gpio = -EINVAL;
969 	}
970 
971 	return 0;
972 }
973 
974 #define CNSS_XO_CLK_RETRY_COUNT_MAX 5
cnss_set_xo_clk_gpio_state(struct cnss_plat_data * plat_priv,bool enable)975 static void cnss_set_xo_clk_gpio_state(struct cnss_plat_data *plat_priv,
976 				       bool enable)
977 {
978 	int xo_clk_gpio = plat_priv->pinctrl_info.xo_clk_gpio, retry = 0, ret;
979 
980 	if (xo_clk_gpio < 0 || plat_priv->device_id != QCA6490_DEVICE_ID)
981 		return;
982 
983 retry_gpio_req:
984 	ret = gpio_request(xo_clk_gpio, "XO_CLK_GPIO");
985 	if (ret) {
986 		if (retry++ < CNSS_XO_CLK_RETRY_COUNT_MAX) {
987 			/* wait for ~(10 - 20) ms */
988 			usleep_range(10000, 20000);
989 			goto retry_gpio_req;
990 		}
991 	}
992 
993 	if (ret) {
994 		cnss_pr_err("QCA6490 XO CLK Gpio request failed\n");
995 		return;
996 	}
997 
998 	if (enable) {
999 		gpio_direction_output(xo_clk_gpio, 1);
1000 		/*XO CLK must be asserted for some time before WLAN_EN */
1001 		usleep_range(100, 200);
1002 	} else {
1003 		/* Assert XO CLK ~(2-5)ms before off for valid latch in HW */
1004 		usleep_range(2000, 5000);
1005 		gpio_direction_output(xo_clk_gpio, 0);
1006 	}
1007 
1008 	gpio_free(xo_clk_gpio);
1009 }
1010 
cnss_select_pinctrl_state(struct cnss_plat_data * plat_priv,bool state)1011 static int cnss_select_pinctrl_state(struct cnss_plat_data *plat_priv,
1012 				     bool state)
1013 {
1014 	int ret = 0;
1015 	struct cnss_pinctrl_info *pinctrl_info;
1016 
1017 	if (!plat_priv) {
1018 		cnss_pr_err("plat_priv is NULL!\n");
1019 		ret = -ENODEV;
1020 		goto out;
1021 	}
1022 
1023 	pinctrl_info = &plat_priv->pinctrl_info;
1024 
1025 	if (state) {
1026 		if (!IS_ERR_OR_NULL(pinctrl_info->bootstrap_active)) {
1027 			ret = pinctrl_select_state
1028 				(pinctrl_info->pinctrl,
1029 				 pinctrl_info->bootstrap_active);
1030 			if (ret) {
1031 				cnss_pr_err("Failed to select bootstrap active state, err = %d\n",
1032 					    ret);
1033 				goto out;
1034 			}
1035 			udelay(BOOTSTRAP_DELAY);
1036 		}
1037 		if (!IS_ERR_OR_NULL(pinctrl_info->sol_default)) {
1038 			ret = pinctrl_select_state
1039 				(pinctrl_info->pinctrl,
1040 				 pinctrl_info->sol_default);
1041 			if (ret) {
1042 				cnss_pr_err("Failed to select sol default state, err = %d\n",
1043 					    ret);
1044 				goto out;
1045 			}
1046 			cnss_pr_dbg("Selected sol default state\n");
1047 		}
1048 		cnss_set_xo_clk_gpio_state(plat_priv, true);
1049 		if (!IS_ERR_OR_NULL(pinctrl_info->wlan_en_active)) {
1050 			ret = pinctrl_select_state
1051 				(pinctrl_info->pinctrl,
1052 				 pinctrl_info->wlan_en_active);
1053 			if (ret) {
1054 				cnss_pr_err("Failed to select wlan_en active state, err = %d\n",
1055 					    ret);
1056 				goto out;
1057 			}
1058 
1059 			if (plat_priv->device_id == QCA6174_DEVICE_ID ||
1060 			    plat_priv->device_id == 0)
1061 				mdelay(WLAN_ENABLE_DELAY_ROME);
1062 			else
1063 				udelay(WLAN_ENABLE_DELAY);
1064 
1065 			cnss_set_xo_clk_gpio_state(plat_priv, false);
1066 		} else {
1067 			cnss_set_xo_clk_gpio_state(plat_priv, false);
1068 			goto out;
1069 		}
1070 
1071 	} else {
1072 		if (!IS_ERR_OR_NULL(pinctrl_info->wlan_en_sleep)) {
1073 			cnss_wlan_hw_disable_check(plat_priv);
1074 			if (test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
1075 				cnss_pr_dbg("Avoid WLAN_EN low. WLAN HW Disbaled");
1076 				goto out;
1077 			}
1078 			ret = pinctrl_select_state(pinctrl_info->pinctrl,
1079 						   pinctrl_info->wlan_en_sleep);
1080 			if (ret) {
1081 				cnss_pr_err("Failed to select wlan_en sleep state, err = %d\n",
1082 					    ret);
1083 				goto out;
1084 			}
1085 		} else {
1086 			goto out;
1087 		}
1088 	}
1089 
1090 	cnss_pr_dbg("WLAN_EN Value: %d\n", gpio_get_value(pinctrl_info->wlan_en_gpio));
1091 	cnss_pr_dbg("%s WLAN_EN GPIO successfully\n",
1092 		    state ? "Assert" : "De-assert");
1093 
1094 	return 0;
1095 out:
1096 	return ret;
1097 }
1098 
1099 /**
1100  * cnss_select_pinctrl_enable - select WLAN_GPIO for Active pinctrl status
1101  * @plat_priv: Platform private data structure pointer
1102  *
1103  * For QCA6490, PMU requires minimum 100ms delay between BT_EN_GPIO off and
1104  * WLAN_EN_GPIO on. This is done to avoid power up issues.
1105  *
1106  * Return: Status of pinctrl select operation. 0 - Success.
1107  */
cnss_select_pinctrl_enable(struct cnss_plat_data * plat_priv)1108 static int cnss_select_pinctrl_enable(struct cnss_plat_data *plat_priv)
1109 {
1110 	int ret = 0, bt_en_gpio = plat_priv->pinctrl_info.bt_en_gpio;
1111 	u8 wlan_en_state = 0;
1112 
1113 	if (bt_en_gpio < 0 || plat_priv->device_id != QCA6490_DEVICE_ID)
1114 		goto set_wlan_en;
1115 
1116 	if (gpio_get_value(bt_en_gpio)) {
1117 		cnss_pr_dbg("BT_EN_GPIO State: On\n");
1118 		ret = cnss_select_pinctrl_state(plat_priv, true);
1119 		if (!ret)
1120 			return ret;
1121 		wlan_en_state = 1;
1122 	}
1123 	if (!gpio_get_value(bt_en_gpio)) {
1124 		cnss_pr_dbg("BT_EN_GPIO State: Off. Delay WLAN_GPIO enable\n");
1125 		/* check for BT_EN_GPIO down race during above operation */
1126 		if (wlan_en_state) {
1127 			cnss_pr_dbg("Reset WLAN_EN as BT got turned off during enable\n");
1128 			cnss_select_pinctrl_state(plat_priv, false);
1129 			wlan_en_state = 0;
1130 		}
1131 		/* 100 ms delay for BT_EN and WLAN_EN QCA6490 PMU sequencing */
1132 		msleep(100);
1133 	}
1134 set_wlan_en:
1135 	if (!wlan_en_state)
1136 		ret = cnss_select_pinctrl_state(plat_priv, true);
1137 	return ret;
1138 }
1139 
cnss_get_input_gpio_value(struct cnss_plat_data * plat_priv,int gpio_num)1140 int cnss_get_input_gpio_value(struct cnss_plat_data *plat_priv, int gpio_num)
1141 {
1142 	int ret;
1143 
1144 	if (gpio_num < 0)
1145 		return -EINVAL;
1146 
1147 	ret = gpio_direction_input(gpio_num);
1148 	if (ret) {
1149 		cnss_pr_err("Failed to set direction of GPIO(%d), err = %d",
1150 			    gpio_num, ret);
1151 		return -EINVAL;
1152 	}
1153 
1154 	return gpio_get_value(gpio_num);
1155 }
1156 
cnss_power_on_device(struct cnss_plat_data * plat_priv,bool reset)1157 int cnss_power_on_device(struct cnss_plat_data *plat_priv, bool reset)
1158 {
1159 	int ret = 0;
1160 
1161 	if (plat_priv->powered_on) {
1162 		cnss_pr_dbg("Already powered up");
1163 		return 0;
1164 	}
1165 
1166 	cnss_wlan_hw_disable_check(plat_priv);
1167 	if (test_bit(CNSS_WLAN_HW_DISABLED, &plat_priv->driver_state)) {
1168 		cnss_pr_dbg("Avoid WLAN Power On. WLAN HW Disbaled");
1169 		return -EINVAL;
1170 	}
1171 
1172 	ret = cnss_vreg_on_type(plat_priv, CNSS_VREG_PRIM);
1173 	if (ret) {
1174 		cnss_pr_err("Failed to turn on vreg, err = %d\n", ret);
1175 		goto out;
1176 	}
1177 
1178 	ret = cnss_clk_on(plat_priv, &plat_priv->clk_list);
1179 	if (ret) {
1180 		cnss_pr_err("Failed to turn on clocks, err = %d\n", ret);
1181 		goto vreg_off;
1182 	}
1183 
1184 #ifdef CONFIG_PULLDOWN_WLANEN
1185 	if (reset) {
1186 		/* The default state of wlan_en maybe not low,
1187 		 * according to datasheet, we should put wlan_en
1188 		 * to low first, and trigger high.
1189 		 * And the default delay for qca6390 is at least 4ms,
1190 		 * for qcn7605/qca6174, it is 10us. For safe, set 5ms delay
1191 		 * here.
1192 		 */
1193 		ret = cnss_select_pinctrl_state(plat_priv, false);
1194 		if (ret) {
1195 			cnss_pr_err("Failed to select pinctrl state, err = %d\n",
1196 				    ret);
1197 			goto clk_off;
1198 		}
1199 
1200 		usleep_range(4000, 5000);
1201 	}
1202 #endif
1203 
1204 	ret = cnss_select_pinctrl_enable(plat_priv);
1205 	if (ret) {
1206 		cnss_pr_err("Failed to select pinctrl state, err = %d\n", ret);
1207 		goto clk_off;
1208 	}
1209 
1210 	plat_priv->powered_on = true;
1211 	clear_bit(CNSS_POWER_OFF, &plat_priv->driver_state);
1212 	cnss_enable_dev_sol_irq(plat_priv);
1213 	cnss_set_host_sol_value(plat_priv, 0);
1214 
1215 	return 0;
1216 
1217 clk_off:
1218 	cnss_clk_off(plat_priv, &plat_priv->clk_list);
1219 vreg_off:
1220 	cnss_vreg_off_type(plat_priv, CNSS_VREG_PRIM);
1221 out:
1222 	return ret;
1223 }
1224 
cnss_power_off_device(struct cnss_plat_data * plat_priv)1225 void cnss_power_off_device(struct cnss_plat_data *plat_priv)
1226 {
1227 	if (!plat_priv->powered_on) {
1228 		cnss_pr_dbg("Already powered down");
1229 		return;
1230 	}
1231 
1232 	set_bit(CNSS_POWER_OFF, &plat_priv->driver_state);
1233 	cnss_bus_shutdown_cleanup(plat_priv);
1234 	cnss_disable_dev_sol_irq(plat_priv);
1235 	cnss_select_pinctrl_state(plat_priv, false);
1236 	cnss_clk_off(plat_priv, &plat_priv->clk_list);
1237 	cnss_vreg_off_type(plat_priv, CNSS_VREG_PRIM);
1238 	plat_priv->powered_on = false;
1239 }
1240 
cnss_is_device_powered_on(struct cnss_plat_data * plat_priv)1241 bool cnss_is_device_powered_on(struct cnss_plat_data *plat_priv)
1242 {
1243 	return plat_priv->powered_on;
1244 }
1245 
cnss_set_pin_connect_status(struct cnss_plat_data * plat_priv)1246 void cnss_set_pin_connect_status(struct cnss_plat_data *plat_priv)
1247 {
1248 	unsigned long pin_status = 0;
1249 
1250 	set_bit(CNSS_WLAN_EN, &pin_status);
1251 	set_bit(CNSS_PCIE_TXN, &pin_status);
1252 	set_bit(CNSS_PCIE_TXP, &pin_status);
1253 	set_bit(CNSS_PCIE_RXN, &pin_status);
1254 	set_bit(CNSS_PCIE_RXP, &pin_status);
1255 	set_bit(CNSS_PCIE_REFCLKN, &pin_status);
1256 	set_bit(CNSS_PCIE_REFCLKP, &pin_status);
1257 	set_bit(CNSS_PCIE_RST, &pin_status);
1258 
1259 	plat_priv->pin_result.host_pin_result = pin_status;
1260 }
1261 
1262 #if IS_ENABLED(CONFIG_QCOM_COMMAND_DB)
cnss_cmd_db_ready(struct cnss_plat_data * plat_priv)1263 static int cnss_cmd_db_ready(struct cnss_plat_data *plat_priv)
1264 {
1265 	return cmd_db_ready();
1266 }
1267 
cnss_cmd_db_read_addr(struct cnss_plat_data * plat_priv,const char * res_id)1268 static u32 cnss_cmd_db_read_addr(struct cnss_plat_data *plat_priv,
1269 				 const char *res_id)
1270 {
1271 	return cmd_db_read_addr(res_id);
1272 }
1273 #else
cnss_cmd_db_ready(struct cnss_plat_data * plat_priv)1274 static int cnss_cmd_db_ready(struct cnss_plat_data *plat_priv)
1275 {
1276 	return -EOPNOTSUPP;
1277 }
1278 
cnss_cmd_db_read_addr(struct cnss_plat_data * plat_priv,const char * res_id)1279 static u32 cnss_cmd_db_read_addr(struct cnss_plat_data *plat_priv,
1280 				 const char *res_id)
1281 {
1282 	return 0;
1283 }
1284 #endif
1285 
cnss_get_tcs_info(struct cnss_plat_data * plat_priv)1286 int cnss_get_tcs_info(struct cnss_plat_data *plat_priv)
1287 {
1288 	struct platform_device *plat_dev = plat_priv->plat_dev;
1289 	struct resource *res;
1290 	resource_size_t addr_len;
1291 	void __iomem *tcs_cmd_base_addr;
1292 	int ret = 0;
1293 
1294 	res = platform_get_resource_byname(plat_dev, IORESOURCE_MEM, "tcs_cmd");
1295 	if (!res) {
1296 		cnss_pr_dbg("TCS CMD address is not present for CPR\n");
1297 		goto out;
1298 	}
1299 
1300 	plat_priv->tcs_info.cmd_base_addr = res->start;
1301 	addr_len = resource_size(res);
1302 	cnss_pr_dbg("TCS CMD base address is %pa with length %pa\n",
1303 		    &plat_priv->tcs_info.cmd_base_addr, &addr_len);
1304 
1305 	tcs_cmd_base_addr = devm_ioremap(&plat_dev->dev, res->start, addr_len);
1306 	if (!tcs_cmd_base_addr) {
1307 		ret = -EINVAL;
1308 		cnss_pr_err("Failed to map TCS CMD address, err = %d\n",
1309 			    ret);
1310 		goto out;
1311 	}
1312 	plat_priv->tcs_info.cmd_base_addr_io = tcs_cmd_base_addr;
1313 	return 0;
1314 out:
1315 	return ret;
1316 }
1317 
cnss_get_cpr_info(struct cnss_plat_data * plat_priv)1318 int cnss_get_cpr_info(struct cnss_plat_data *plat_priv)
1319 {
1320 	struct platform_device *plat_dev = plat_priv->plat_dev;
1321 	struct cnss_cpr_info *cpr_info = &plat_priv->cpr_info;
1322 	const char *cmd_db_name;
1323 	u32 cpr_pmic_addr = 0;
1324 	int ret = 0;
1325 
1326 	if (plat_priv->tcs_info.cmd_base_addr == 0) {
1327 		cnss_pr_dbg("TCS CMD not configured\n");
1328 		return 0;
1329 	}
1330 
1331 	ret = of_property_read_string(plat_dev->dev.of_node,
1332 				      "qcom,cmd_db_name", &cmd_db_name);
1333 	if (ret) {
1334 		cnss_pr_dbg("CommandDB name is not present for CPR\n");
1335 		goto out;
1336 	}
1337 
1338 	ret = cnss_cmd_db_ready(plat_priv);
1339 	if (ret) {
1340 		cnss_pr_err("CommandDB is not ready, err = %d\n", ret);
1341 		goto out;
1342 	}
1343 
1344 	cpr_pmic_addr = cnss_cmd_db_read_addr(plat_priv, cmd_db_name);
1345 	if (cpr_pmic_addr > 0) {
1346 		cpr_info->cpr_pmic_addr = cpr_pmic_addr;
1347 		cnss_pr_dbg("Get CPR PMIC address 0x%x from %s\n",
1348 			    cpr_info->cpr_pmic_addr, cmd_db_name);
1349 	} else {
1350 		cnss_pr_err("CPR PMIC address is not available for %s\n",
1351 			    cmd_db_name);
1352 		ret = -EINVAL;
1353 		goto out;
1354 	}
1355 	return 0;
1356 out:
1357 	return ret;
1358 }
1359 
1360 #if IS_ENABLED(CONFIG_MSM_QMP)
1361 /**
1362  * cnss_mbox_init: Initialize mbox interface
1363  * @plat_priv: Pointer to cnss platform data
1364  *
1365  * Try to get property 'mboxes' from device tree and
1366  * initialize the interface for AOP configuration.
1367  *
1368  * Return: 0 for success, otherwise error code
1369  */
cnss_mbox_init(struct cnss_plat_data * plat_priv)1370 static int cnss_mbox_init(struct cnss_plat_data *plat_priv)
1371 {
1372 	struct mbox_client *mbox = &plat_priv->mbox_client_data;
1373 	struct mbox_chan *chan;
1374 	int ret = 0;
1375 
1376 	plat_priv->mbox_chan = NULL;
1377 	mbox->dev = &plat_priv->plat_dev->dev;
1378 	mbox->tx_block = true;
1379 	mbox->tx_tout = CNSS_MBOX_TIMEOUT_MS;
1380 	mbox->knows_txdone = false;
1381 	chan = mbox_request_channel(mbox, 0);
1382 	if (IS_ERR(chan)) {
1383 		ret = PTR_ERR(chan);
1384 		cnss_pr_dbg("Failed to get mbox channel[%d]\n", ret);
1385 	} else {
1386 		plat_priv->mbox_chan = chan;
1387 		cnss_pr_dbg("Mbox channel initialized\n");
1388 	}
1389 
1390 	return ret;
1391 }
1392 
1393 /**
1394  * cnss_mbox_deinit: De-Initialize mbox interface
1395  * @plat_priv: Pointer to cnss platform data
1396  *
1397  * Return: None
1398  */
cnss_mbox_deinit(struct cnss_plat_data * plat_priv)1399 static void cnss_mbox_deinit(struct cnss_plat_data *plat_priv)
1400 {
1401 	if (!plat_priv->mbox_chan) {
1402 		mbox_free_channel(plat_priv->mbox_chan);
1403 		plat_priv->mbox_chan = NULL;
1404 	}
1405 }
1406 
1407 /**
1408  * cnss_mbox_send_msg: Send json message to AOP using mbox channel
1409  * @plat_priv: Pointer to cnss platform data
1410  * @msg: String in json format
1411  *
1412  * Return: 0 for success, otherwise error code
1413  */
1414 static int
cnss_mbox_send_msg(struct cnss_plat_data * plat_priv,char * mbox_msg)1415 cnss_mbox_send_msg(struct cnss_plat_data *plat_priv, char *mbox_msg)
1416 {
1417 	struct qmp_pkt pkt;
1418 	int ret = 0;
1419 
1420 	if (!plat_priv->mbox_chan)
1421 		return -ENODEV;
1422 
1423 	cnss_pr_dbg("Sending AOP Mbox msg: %s\n", mbox_msg);
1424 	pkt.size = CNSS_MBOX_MSG_MAX_LEN;
1425 	pkt.data = mbox_msg;
1426 	ret = mbox_send_message(plat_priv->mbox_chan, &pkt);
1427 	if (ret < 0)
1428 		cnss_pr_err("Failed to send AOP mbox msg: %s\n", mbox_msg);
1429 
1430 	return ret;
1431 }
1432 #else
cnss_mbox_init(struct cnss_plat_data * plat_priv)1433 static inline int cnss_mbox_init(struct cnss_plat_data *plat_priv)
1434 {
1435 	return -EOPNOTSUPP;
1436 }
1437 
cnss_mbox_deinit(struct cnss_plat_data * plat_priv)1438 static inline void cnss_mbox_deinit(struct cnss_plat_data *plat_priv)
1439 {
1440 }
1441 
1442 static inline int
cnss_mbox_send_msg(struct cnss_plat_data * plat_priv,char * mbox_msg)1443 cnss_mbox_send_msg(struct cnss_plat_data *plat_priv, char *mbox_msg)
1444 {
1445 	return -EOPNOTSUPP;
1446 }
1447 #endif
1448 
1449 /**
1450  * cnss_qmp_init: Initialize direct QMP interface
1451  * @plat_priv: Pointer to cnss platform data
1452  *
1453  * Try to get property 'qcom,qmp' from device tree and
1454  * initialize the interface for AOP configuration.
1455  *
1456  * Return: 0 for success, otherwise error code
1457  */
cnss_qmp_init(struct cnss_plat_data * plat_priv)1458 static int cnss_qmp_init(struct cnss_plat_data *plat_priv)
1459 {
1460 	struct qmp *qmp;
1461 
1462 	plat_priv->qmp = NULL;
1463 	qmp = qmp_get(&plat_priv->plat_dev->dev);
1464 	if (IS_ERR(qmp)) {
1465 		cnss_pr_err("Failed to get qmp: %d\n",
1466 			    PTR_ERR(qmp));
1467 		return PTR_ERR(qmp);
1468 	}
1469 
1470 	plat_priv->qmp = qmp;
1471 	cnss_pr_dbg("QMP initialized\n");
1472 	return 0;
1473 }
1474 
1475 /**
1476  * cnss_qmp_deinit: De-Initialize direct QMP interface
1477  * @plat_priv: Pointer to cnss platform data
1478  *
1479  * Return: None
1480  */
cnss_qmp_deinit(struct cnss_plat_data * plat_priv)1481 static void cnss_qmp_deinit(struct cnss_plat_data *plat_priv)
1482 {
1483 	if (plat_priv->qmp) {
1484 		qmp_put(plat_priv->qmp);
1485 		plat_priv->qmp = NULL;
1486 	}
1487 }
1488 
1489 /**
1490  * cnss_qmp_send_msg: Send json message to AOP using direct QMP
1491  * @plat_priv: Pointer to cnss platform data
1492  * @msg: String in json format
1493  *
1494  * Return: 0 for success, otherwise error code
1495  */
1496 static int
cnss_qmp_send_msg(struct cnss_plat_data * plat_priv,char * mbox_msg)1497 cnss_qmp_send_msg(struct cnss_plat_data *plat_priv, char *mbox_msg)
1498 {
1499 	int ret;
1500 
1501 	if (!plat_priv->qmp)
1502 		return -ENODEV;
1503 
1504 	cnss_pr_dbg("Sending AOP QMP msg: %s\n", mbox_msg);
1505 	ret = qmp_send(plat_priv->qmp, mbox_msg, CNSS_MBOX_MSG_MAX_LEN);
1506 	if (ret)
1507 		cnss_pr_err("Failed to send AOP QMP msg: %d[%s]\n", ret, mbox_msg);
1508 
1509 	return ret;
1510 }
1511 
1512 /**
1513  * cnss_aop_interface_init: Initialize AOP interface: either mbox channel or direct QMP
1514  * @plat_priv: Pointer to cnss platform data
1515  *
1516  * Device tree file should have either mbox or qmp configured, but not both.
1517  * Based on device tree configuration setup mbox channel or QMP
1518  *
1519  * Return: 0 for success, otherwise error code
1520  */
cnss_aop_interface_init(struct cnss_plat_data * plat_priv)1521 int cnss_aop_interface_init(struct cnss_plat_data *plat_priv)
1522 {
1523 	int ret;
1524 
1525 	/* First try to get mbox channel, if it fails then try qmp_get
1526 	 * In device tree file there should be either mboxes or qmp,
1527 	 * cannot have both properties at the same time.
1528 	 */
1529 	ret = cnss_mbox_init(plat_priv);
1530 	if (ret) {
1531 		ret = cnss_qmp_init(plat_priv);
1532 		if (ret)
1533 			return ret;
1534 	}
1535 
1536 	ret = cnss_aop_pdc_reconfig(plat_priv);
1537 	if (ret)
1538 		cnss_pr_err("Failed to reconfig WLAN PDC, err = %d\n", ret);
1539 
1540 	return ret;
1541 }
1542 
1543 /**
1544  * cnss_aop_interface_deinit: Cleanup AOP interface
1545  * @plat_priv: Pointer to cnss platform data
1546  *
1547  * Cleanup mbox channel or QMP whichever was configured during initialization.
1548  *
1549  * Return: None
1550  */
cnss_aop_interface_deinit(struct cnss_plat_data * plat_priv)1551 void cnss_aop_interface_deinit(struct cnss_plat_data *plat_priv)
1552 {
1553 	cnss_mbox_deinit(plat_priv);
1554 	cnss_qmp_deinit(plat_priv);
1555 }
1556 
1557 /**
1558  * cnss_aop_send_msg: Sends json message to AOP using either mbox channel or direct QMP
1559  * @plat_priv: Pointer to cnss platform data
1560  * @msg: String in json format
1561  *
1562  * AOP accepts JSON message to configure WLAN resources. Format as follows:
1563  * To send VReg config: {class: wlan_pdc, ss: <pdc_name>,
1564  *                       res: <VReg_name>.<param>, <seq_param>: <value>}
1565  * To send PDC Config: {class: wlan_pdc, ss: <pdc_name>, res: pdc,
1566  *                      enable: <Value>}
1567  * QMP returns timeout error if format not correct or AOP operation fails.
1568  *
1569  * Return: 0 for success
1570  */
cnss_aop_send_msg(struct cnss_plat_data * plat_priv,char * mbox_msg)1571 int cnss_aop_send_msg(struct cnss_plat_data *plat_priv, char *mbox_msg)
1572 {
1573 	int ret;
1574 
1575 	ret = cnss_mbox_send_msg(plat_priv, mbox_msg);
1576 	if (ret)
1577 		ret = cnss_qmp_send_msg(plat_priv, mbox_msg);
1578 
1579 	if (ret)
1580 		cnss_pr_err("Failed to send AOP msg: %d\n", ret);
1581 	return ret;
1582 }
1583 
cnss_aop_interface_ready(struct cnss_plat_data * plat_priv)1584 static inline bool cnss_aop_interface_ready(struct cnss_plat_data *plat_priv)
1585 {
1586 	return (plat_priv->mbox_chan || plat_priv->qmp);
1587 }
1588 
1589 /* cnss_pdc_reconfig: Send PDC init table as configured in DT for wlan device */
cnss_aop_pdc_reconfig(struct cnss_plat_data * plat_priv)1590 int cnss_aop_pdc_reconfig(struct cnss_plat_data *plat_priv)
1591 {
1592 	u32 i;
1593 	int ret;
1594 
1595 	if (plat_priv->pdc_init_table_len <= 0 || !plat_priv->pdc_init_table)
1596 		return 0;
1597 
1598 	cnss_pr_dbg("Setting PDC defaults for device ID: %d\n",
1599 		    plat_priv->device_id);
1600 	for (i = 0; i < plat_priv->pdc_init_table_len; i++) {
1601 		ret = cnss_aop_send_msg(plat_priv,
1602 					(char *)plat_priv->pdc_init_table[i]);
1603 		if (ret < 0)
1604 			break;
1605 	}
1606 	return ret;
1607 }
1608 
1609 /* cnss_aop_pdc_name_str: Get PDC name corresponding to VReg from DT Mapiping */
cnss_aop_pdc_name_str(struct cnss_plat_data * plat_priv,const char * vreg_name)1610 static const char *cnss_aop_pdc_name_str(struct cnss_plat_data *plat_priv,
1611 					 const char *vreg_name)
1612 {
1613 	u32 i;
1614 	static const char * const aop_pdc_ss_str[] = {"rf", "bb"};
1615 	const char *pdc = aop_pdc_ss_str[0], *vreg_map_name;
1616 
1617 	if (plat_priv->vreg_pdc_map_len <= 0 || !plat_priv->vreg_pdc_map)
1618 		goto end;
1619 
1620 	for (i = 0; i < plat_priv->vreg_pdc_map_len; i++) {
1621 		vreg_map_name = plat_priv->vreg_pdc_map[i];
1622 		if (strnstr(vreg_map_name, vreg_name, strlen(vreg_map_name))) {
1623 			pdc = plat_priv->vreg_pdc_map[i + 1];
1624 			break;
1625 		}
1626 	}
1627 end:
1628 	cnss_pr_dbg("%s mapped to %s\n", vreg_name, pdc);
1629 	return pdc;
1630 }
1631 
cnss_aop_set_vreg_param(struct cnss_plat_data * plat_priv,const char * vreg_name,enum cnss_aop_vreg_param param,enum cnss_aop_tcs_seq_param seq_param,int val)1632 static int cnss_aop_set_vreg_param(struct cnss_plat_data *plat_priv,
1633 				   const char *vreg_name,
1634 				   enum cnss_aop_vreg_param param,
1635 				   enum cnss_aop_tcs_seq_param seq_param,
1636 				   int val)
1637 {
1638 	char msg[CNSS_MBOX_MSG_MAX_LEN];
1639 	static const char * const aop_vreg_param_str[] = {
1640 		[CNSS_VREG_VOLTAGE] = "v", [CNSS_VREG_MODE] = "m",
1641 		[CNSS_VREG_ENABLE] = "e",};
1642 	static const char * const aop_tcs_seq_str[] = {
1643 		[CNSS_TCS_UP_SEQ] = "upval", [CNSS_TCS_DOWN_SEQ] = "dwnval",
1644 		[CNSS_TCS_ENABLE_SEQ] = "enable",};
1645 
1646 	if (param >= CNSS_VREG_PARAM_MAX || seq_param >= CNSS_TCS_SEQ_MAX ||
1647 	    !vreg_name)
1648 		return -EINVAL;
1649 
1650 	snprintf(msg, CNSS_MBOX_MSG_MAX_LEN,
1651 		 "{class: wlan_pdc, ss: %s, res: %s.%s, %s: %d}",
1652 		 cnss_aop_pdc_name_str(plat_priv, vreg_name),
1653 		 vreg_name, aop_vreg_param_str[param],
1654 		 aop_tcs_seq_str[seq_param], val);
1655 
1656 	return cnss_aop_send_msg(plat_priv, msg);
1657 }
1658 
cnss_aop_ol_cpr_cfg_setup(struct cnss_plat_data * plat_priv,struct wlfw_pmu_cfg_v01 * fw_pmu_cfg)1659 int cnss_aop_ol_cpr_cfg_setup(struct cnss_plat_data *plat_priv,
1660 			      struct wlfw_pmu_cfg_v01 *fw_pmu_cfg)
1661 {
1662 	const char *pmu_pin, *vreg;
1663 	struct wlfw_pmu_param_v01 *fw_pmu_param;
1664 	u32 fw_pmu_param_len, i, j, plat_vreg_param_len = 0;
1665 	int ret = 0;
1666 	struct platform_vreg_param {
1667 		char vreg[MAX_PROP_SIZE];
1668 		u32 wake_volt;
1669 		u32 sleep_volt;
1670 	} plat_vreg_param[QMI_WLFW_PMU_PARAMS_MAX_V01] = {0};
1671 	static bool config_done;
1672 
1673 	if (config_done)
1674 		return 0;
1675 
1676 	if (plat_priv->pmu_vreg_map_len <= 0 ||
1677 	    !plat_priv->pmu_vreg_map ||
1678 	    (!plat_priv->mbox_chan && !plat_priv->qmp)) {
1679 		cnss_pr_dbg("Mbox channel / QMP / PMU VReg Map not configured\n");
1680 		goto end;
1681 	}
1682 
1683 	if (!fw_pmu_cfg)
1684 		return -EINVAL;
1685 
1686 	fw_pmu_param = fw_pmu_cfg->pmu_param;
1687 	fw_pmu_param_len = fw_pmu_cfg->pmu_param_len;
1688 	/* Get PMU Pin name to Platfom Vreg Mapping */
1689 	for (i = 0; i < fw_pmu_param_len; i++) {
1690 		cnss_pr_dbg("FW_PMU Data: %s %d %d %d %d\n",
1691 			    fw_pmu_param[i].pin_name,
1692 			    fw_pmu_param[i].wake_volt_valid,
1693 			    fw_pmu_param[i].wake_volt,
1694 			    fw_pmu_param[i].sleep_volt_valid,
1695 			    fw_pmu_param[i].sleep_volt);
1696 
1697 		if (!fw_pmu_param[i].wake_volt_valid &&
1698 		    !fw_pmu_param[i].sleep_volt_valid)
1699 			continue;
1700 
1701 		vreg = NULL;
1702 		for (j = 0; j < plat_priv->pmu_vreg_map_len; j += 2) {
1703 			pmu_pin = plat_priv->pmu_vreg_map[j];
1704 			if (strnstr(pmu_pin, fw_pmu_param[i].pin_name,
1705 				    strlen(pmu_pin))) {
1706 				vreg = plat_priv->pmu_vreg_map[j + 1];
1707 				break;
1708 			}
1709 		}
1710 		if (!vreg) {
1711 			cnss_pr_err("No VREG mapping for %s\n",
1712 				    fw_pmu_param[i].pin_name);
1713 			continue;
1714 		} else {
1715 			cnss_pr_dbg("%s mapped to %s\n",
1716 				    fw_pmu_param[i].pin_name, vreg);
1717 		}
1718 		for (j = 0; j < QMI_WLFW_PMU_PARAMS_MAX_V01; j++) {
1719 			u32 wake_volt = 0, sleep_volt = 0;
1720 
1721 			if (plat_vreg_param[j].vreg[0] == '\0')
1722 				strlcpy(plat_vreg_param[j].vreg, vreg,
1723 					sizeof(plat_vreg_param[j].vreg));
1724 			else if (!strnstr(plat_vreg_param[j].vreg, vreg,
1725 					  strlen(plat_vreg_param[j].vreg)))
1726 				continue;
1727 
1728 			if (fw_pmu_param[i].wake_volt_valid)
1729 				wake_volt = roundup(fw_pmu_param[i].wake_volt,
1730 						    CNSS_PMIC_VOLTAGE_STEP) -
1731 						    CNSS_PMIC_AUTO_HEADROOM +
1732 						    CNSS_IR_DROP_WAKE;
1733 			if (fw_pmu_param[i].sleep_volt_valid)
1734 				sleep_volt = roundup(fw_pmu_param[i].sleep_volt,
1735 						     CNSS_PMIC_VOLTAGE_STEP) -
1736 						     CNSS_PMIC_AUTO_HEADROOM +
1737 						     CNSS_IR_DROP_SLEEP;
1738 
1739 			plat_vreg_param[j].wake_volt =
1740 				(wake_volt > plat_vreg_param[j].wake_volt ?
1741 				 wake_volt : plat_vreg_param[j].wake_volt);
1742 			plat_vreg_param[j].sleep_volt =
1743 				(sleep_volt > plat_vreg_param[j].sleep_volt ?
1744 				 sleep_volt : plat_vreg_param[j].sleep_volt);
1745 
1746 			plat_vreg_param_len = (plat_vreg_param_len > j ?
1747 					       plat_vreg_param_len : j);
1748 			cnss_pr_dbg("Plat VReg Data: %s %d %d\n",
1749 				    plat_vreg_param[j].vreg,
1750 				    plat_vreg_param[j].wake_volt,
1751 				    plat_vreg_param[j].sleep_volt);
1752 			break;
1753 		}
1754 	}
1755 
1756 	for (i = 0; i <= plat_vreg_param_len; i++) {
1757 		if (plat_vreg_param[i].wake_volt > 0) {
1758 			ret =
1759 			cnss_aop_set_vreg_param(plat_priv,
1760 						plat_vreg_param[i].vreg,
1761 						CNSS_VREG_VOLTAGE,
1762 						CNSS_TCS_UP_SEQ,
1763 						plat_vreg_param[i].wake_volt);
1764 		}
1765 		if (plat_vreg_param[i].sleep_volt > 0) {
1766 			ret =
1767 			cnss_aop_set_vreg_param(plat_priv,
1768 						plat_vreg_param[i].vreg,
1769 						CNSS_VREG_VOLTAGE,
1770 						CNSS_TCS_DOWN_SEQ,
1771 						plat_vreg_param[i].sleep_volt);
1772 		}
1773 		if (ret < 0)
1774 			break;
1775 	}
1776 end:
1777 	config_done = true;
1778 	return ret;
1779 }
1780 
cnss_power_misc_params_init(struct cnss_plat_data * plat_priv)1781 void cnss_power_misc_params_init(struct cnss_plat_data *plat_priv)
1782 {
1783 	struct device *dev = &plat_priv->plat_dev->dev;
1784 	int ret;
1785 	u32 cfg_arr_size = 0, *cfg_arr = NULL;
1786 
1787 	/* common DT Entries */
1788 	plat_priv->pdc_init_table_len =
1789 				of_property_count_strings(dev->of_node,
1790 							  "qcom,pdc_init_table");
1791 	if (plat_priv->pdc_init_table_len > 0) {
1792 		plat_priv->pdc_init_table =
1793 			kcalloc(plat_priv->pdc_init_table_len,
1794 				sizeof(char *), GFP_KERNEL);
1795 		if (plat_priv->pdc_init_table) {
1796 			ret = of_property_read_string_array(dev->of_node,
1797 							    "qcom,pdc_init_table",
1798 							    plat_priv->pdc_init_table,
1799 							    plat_priv->pdc_init_table_len);
1800 			if (ret < 0)
1801 				cnss_pr_err("Failed to get PDC Init Table\n");
1802 		} else {
1803 			cnss_pr_err("Failed to alloc PDC Init Table mem\n");
1804 		}
1805 	} else {
1806 		cnss_pr_dbg("PDC Init Table not configured\n");
1807 	}
1808 
1809 	plat_priv->vreg_pdc_map_len =
1810 			of_property_count_strings(dev->of_node,
1811 						  "qcom,vreg_pdc_map");
1812 	if (plat_priv->vreg_pdc_map_len > 0) {
1813 		plat_priv->vreg_pdc_map =
1814 			kcalloc(plat_priv->vreg_pdc_map_len,
1815 				sizeof(char *), GFP_KERNEL);
1816 		if (plat_priv->vreg_pdc_map) {
1817 			ret = of_property_read_string_array(dev->of_node,
1818 							    "qcom,vreg_pdc_map",
1819 							    plat_priv->vreg_pdc_map,
1820 							    plat_priv->vreg_pdc_map_len);
1821 			if (ret < 0)
1822 				cnss_pr_err("Failed to get VReg PDC Mapping\n");
1823 		} else {
1824 			cnss_pr_err("Failed to alloc VReg PDC mem\n");
1825 		}
1826 	} else {
1827 		cnss_pr_dbg("VReg PDC Mapping not configured\n");
1828 	}
1829 
1830 	plat_priv->pmu_vreg_map_len =
1831 			of_property_count_strings(dev->of_node,
1832 						  "qcom,pmu_vreg_map");
1833 	if (plat_priv->pmu_vreg_map_len > 0) {
1834 		plat_priv->pmu_vreg_map = kcalloc(plat_priv->pmu_vreg_map_len,
1835 						  sizeof(char *), GFP_KERNEL);
1836 		if (plat_priv->pmu_vreg_map) {
1837 			ret = of_property_read_string_array(dev->of_node,
1838 							    "qcom,pmu_vreg_map",
1839 							    plat_priv->pmu_vreg_map,
1840 							    plat_priv->pmu_vreg_map_len);
1841 			if (ret < 0)
1842 				cnss_pr_err("Fail to get PMU VReg Mapping\n");
1843 		} else {
1844 			cnss_pr_err("Failed to alloc PMU VReg mem\n");
1845 		}
1846 	} else {
1847 		cnss_pr_dbg("PMU VReg Mapping not configured\n");
1848 	}
1849 
1850 	/* Device DT Specific */
1851 	if (plat_priv->device_id == QCA6390_DEVICE_ID ||
1852 	    plat_priv->device_id == QCA6490_DEVICE_ID) {
1853 		ret = of_property_read_string(dev->of_node,
1854 					      "qcom,vreg_ol_cpr",
1855 					      &plat_priv->vreg_ol_cpr);
1856 		if (ret)
1857 			cnss_pr_dbg("VReg for QCA6490 OL CPR not configured\n");
1858 
1859 		ret = of_property_read_string(dev->of_node,
1860 					      "qcom,vreg_ipa",
1861 					      &plat_priv->vreg_ipa);
1862 		if (ret)
1863 			cnss_pr_dbg("VReg for QCA6490 Int Power Amp not configured\n");
1864 	}
1865 	ret = of_property_count_u32_elems(plat_priv->plat_dev->dev.of_node,
1866 					  "qcom,on-chip-pmic-support");
1867 	if (ret > 0) {
1868 		cfg_arr_size = ret;
1869 		cfg_arr = kcalloc(cfg_arr_size, sizeof(*cfg_arr), GFP_KERNEL);
1870 		if (cfg_arr) {
1871 			ret = of_property_read_u32_array(plat_priv->plat_dev->dev.of_node,
1872 							 "qcom,on-chip-pmic-support",
1873 							 cfg_arr, cfg_arr_size);
1874 			if (!ret) {
1875 				plat_priv->on_chip_pmic_devices_count = cfg_arr_size;
1876 				plat_priv->on_chip_pmic_board_ids = cfg_arr;
1877 			}
1878 		} else {
1879 			cnss_pr_err("Failed to alloc cfg table mem\n");
1880 		}
1881 	} else {
1882 		cnss_pr_dbg("On chip PMIC device ids not configured\n");
1883 	}
1884 }
1885 
cnss_update_cpr_info(struct cnss_plat_data * plat_priv)1886 int cnss_update_cpr_info(struct cnss_plat_data *plat_priv)
1887 {
1888 	struct cnss_cpr_info *cpr_info = &plat_priv->cpr_info;
1889 	u32 pmic_addr, voltage = 0, voltage_tmp, offset;
1890 	void __iomem *tcs_cmd_addr, *tcs_cmd_data_addr;
1891 	int i, j;
1892 
1893 	if (cpr_info->voltage == 0) {
1894 		cnss_pr_err("OL CPR Voltage %dm is not valid\n",
1895 			    cpr_info->voltage);
1896 		return -EINVAL;
1897 	}
1898 
1899 	if (plat_priv->device_id != QCA6490_DEVICE_ID)
1900 		return -EINVAL;
1901 
1902 	if (!plat_priv->vreg_ol_cpr ||
1903 	    !cnss_aop_interface_ready(plat_priv)) {
1904 		cnss_pr_dbg("AOP interface / OL CPR Vreg not configured\n");
1905 	} else {
1906 		return cnss_aop_set_vreg_param(plat_priv,
1907 					       plat_priv->vreg_ol_cpr,
1908 					       CNSS_VREG_VOLTAGE,
1909 					       CNSS_TCS_DOWN_SEQ,
1910 					       cpr_info->voltage);
1911 	}
1912 
1913 	if (plat_priv->tcs_info.cmd_base_addr == 0) {
1914 		cnss_pr_dbg("TCS CMD not configured for OL CPR update\n");
1915 		return 0;
1916 	}
1917 
1918 	if (cpr_info->cpr_pmic_addr == 0) {
1919 		cnss_pr_err("PMIC address 0x%x is not valid\n",
1920 			    cpr_info->cpr_pmic_addr);
1921 		return -EINVAL;
1922 	}
1923 
1924 	if (cpr_info->tcs_cmd_data_addr_io)
1925 		goto update_cpr;
1926 
1927 	for (i = 0; i < MAX_TCS_NUM; i++) {
1928 		for (j = 0; j < MAX_TCS_CMD_NUM; j++) {
1929 			offset = i * TCS_OFFSET + j * TCS_CMD_OFFSET;
1930 			tcs_cmd_addr = plat_priv->tcs_info.cmd_base_addr_io +
1931 									offset;
1932 			pmic_addr = readl_relaxed(tcs_cmd_addr);
1933 			if (pmic_addr == cpr_info->cpr_pmic_addr) {
1934 				tcs_cmd_data_addr = tcs_cmd_addr +
1935 					TCS_CMD_DATA_ADDR_OFFSET;
1936 				voltage_tmp = readl_relaxed(tcs_cmd_data_addr);
1937 				cnss_pr_dbg("Got voltage %dmV from i: %d, j: %d\n",
1938 					    voltage_tmp, i, j);
1939 
1940 				if (voltage_tmp > voltage) {
1941 					voltage = voltage_tmp;
1942 					cpr_info->tcs_cmd_data_addr =
1943 					plat_priv->tcs_info.cmd_base_addr +
1944 					offset + TCS_CMD_DATA_ADDR_OFFSET;
1945 					cpr_info->tcs_cmd_data_addr_io =
1946 						tcs_cmd_data_addr;
1947 				}
1948 			}
1949 		}
1950 	}
1951 
1952 	if (!cpr_info->tcs_cmd_data_addr_io) {
1953 		cnss_pr_err("Failed to find proper TCS CMD data address\n");
1954 		return -EINVAL;
1955 	}
1956 
1957 update_cpr:
1958 	cpr_info->voltage = cpr_info->voltage > BT_CXMX_VOLTAGE_MV ?
1959 		cpr_info->voltage : BT_CXMX_VOLTAGE_MV;
1960 	cnss_pr_dbg("Update TCS CMD data address %pa with voltage %dmV\n",
1961 		    &cpr_info->tcs_cmd_data_addr, cpr_info->voltage);
1962 	writel_relaxed(cpr_info->voltage, cpr_info->tcs_cmd_data_addr_io);
1963 
1964 	return 0;
1965 }
1966 
cnss_enable_int_pow_amp_vreg(struct cnss_plat_data * plat_priv)1967 int cnss_enable_int_pow_amp_vreg(struct cnss_plat_data *plat_priv)
1968 {
1969 	struct platform_device *plat_dev = plat_priv->plat_dev;
1970 	u32 offset, addr_val, data_val;
1971 	void __iomem *tcs_cmd;
1972 	int ret;
1973 	static bool config_done;
1974 
1975 	if (plat_priv->device_id != QCA6490_DEVICE_ID)
1976 		return -EINVAL;
1977 
1978 	if (config_done) {
1979 		cnss_pr_dbg("IPA Vreg already configured\n");
1980 		return 0;
1981 	}
1982 
1983 	if (!plat_priv->vreg_ipa ||
1984 	    !cnss_aop_interface_ready(plat_priv)) {
1985 		cnss_pr_dbg("AOP interface / IPA Vreg not configured\n");
1986 	} else {
1987 		ret = cnss_aop_set_vreg_param(plat_priv,
1988 					      plat_priv->vreg_ipa,
1989 					      CNSS_VREG_ENABLE,
1990 					      CNSS_TCS_UP_SEQ, 1);
1991 		if (ret == 0)
1992 			config_done = true;
1993 		return ret;
1994 	}
1995 
1996 	if (!plat_priv->tcs_info.cmd_base_addr_io) {
1997 		cnss_pr_err("TCS CMD not configured for IPA Vreg enable\n");
1998 		return -EINVAL;
1999 	}
2000 
2001 	ret = of_property_read_u32(plat_dev->dev.of_node,
2002 				   "qcom,tcs_offset_int_pow_amp_vreg",
2003 				   &offset);
2004 	if (ret) {
2005 		cnss_pr_dbg("Internal Power Amp Vreg not configured\n");
2006 		return -EINVAL;
2007 	}
2008 	tcs_cmd = plat_priv->tcs_info.cmd_base_addr_io + offset;
2009 	addr_val = readl_relaxed(tcs_cmd);
2010 	tcs_cmd += TCS_CMD_DATA_ADDR_OFFSET;
2011 
2012 	/* 1 = enable Vreg */
2013 	writel_relaxed(1, tcs_cmd);
2014 
2015 	data_val = readl_relaxed(tcs_cmd);
2016 	cnss_pr_dbg("Setup S3E TCS Addr: %x Data: %d\n", addr_val, data_val);
2017 	config_done = true;
2018 
2019 	return 0;
2020 }
2021 
cnss_dev_specific_power_on(struct cnss_plat_data * plat_priv)2022 int cnss_dev_specific_power_on(struct cnss_plat_data *plat_priv)
2023 {
2024 	int ret;
2025 
2026 	if (plat_priv->dt_type != CNSS_DTT_MULTIEXCHG)
2027 		return 0;
2028 
2029 	ret = cnss_get_vreg_type(plat_priv, CNSS_VREG_PRIM);
2030 	if (ret)
2031 		return ret;
2032 
2033 	plat_priv->powered_on = false;
2034 	return cnss_power_on_device(plat_priv, false);
2035 }
2036