1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */
3
4 #ifndef _CNSS_PCI_PLATFORM_H
5 #define _CNSS_PCI_PLATFORM_H
6
7 #include "pci.h"
8
9 #if IS_ENABLED(CONFIG_PCI_MSM)
10 /**
11 * _cnss_pci_enumerate() - Enumerate PCIe endpoints
12 * @plat_priv: driver platform context pointer
13 * @rc_num: root complex index that an endpoint connects to
14 *
15 * This function shall call corresponding PCIe root complex driver APIs
16 * to power on root complex and enumerate the endpoint connected to it.
17 *
18 * Return: 0 for success, negative value for error
19 */
20 int _cnss_pci_enumerate(struct cnss_plat_data *plat_priv, u32 rc_num);
21
22 /**
23 * cnss_pci_assert_perst() - Assert PCIe PERST GPIO
24 * @pci_priv: driver PCI bus context pointer
25 *
26 * This function shall call corresponding PCIe root complex driver APIs
27 * to assert PCIe PERST GPIO.
28 *
29 * Return: 0 for success, negative value for error
30 */
31 int cnss_pci_assert_perst(struct cnss_pci_data *pci_priv);
32
33 /**
34 * cnss_pci_disable_pc() - Disable PCIe link power collapse from RC driver
35 * @pci_priv: driver PCI bus context pointer
36 * @vote: value to indicate disable (true) or enable (false)
37 *
38 * This function shall call corresponding PCIe root complex driver APIs
39 * to disable PCIe power collapse. The purpose of this API is to avoid
40 * root complex driver still controlling PCIe link from callbacks of
41 * system suspend/resume. Device driver itself should take full control
42 * of the link in such cases.
43 *
44 * Return: 0 for success, negative value for error
45 */
46 int cnss_pci_disable_pc(struct cnss_pci_data *pci_priv, bool vote);
47
48 /**
49 * cnss_pci_set_link_bandwidth() - Update number of lanes and speed of
50 * PCIe link
51 * @pci_priv: driver PCI bus context pointer
52 * @link_speed: PCIe link gen speed
53 * @link_width: number of lanes for PCIe link
54 *
55 * This function shall call corresponding PCIe root complex driver APIs
56 * to update number of lanes and speed of the link.
57 *
58 * Return: 0 for success, negative value for error
59 */
60 int cnss_pci_set_link_bandwidth(struct cnss_pci_data *pci_priv,
61 u16 link_speed, u16 link_width);
62
63 /**
64 * cnss_pci_set_max_link_speed() - Set the maximum speed PCIe can link up with
65 * @pci_priv: driver PCI bus context pointer
66 * @rc_num: root complex index that an endpoint connects to
67 * @link_speed: PCIe link gen speed
68 *
69 * This function shall call corresponding PCIe root complex driver APIs
70 * to update the maximum speed that PCIe can link up with.
71 *
72 * Return: 0 for success, negative value for error
73 */
74 int cnss_pci_set_max_link_speed(struct cnss_pci_data *pci_priv,
75 u32 rc_num, u16 link_speed);
76
77 /**
78 * cnss_reg_pci_event() - Register for PCIe events
79 * @pci_priv: driver PCI bus context pointer
80 *
81 * This function shall call corresponding PCIe root complex driver APIs
82 * to register for PCIe events like link down or WAKE GPIO toggling etc.
83 * The events should be based on PCIe root complex driver's capability.
84 *
85 * Return: 0 for success, negative value for error
86 */
87 int cnss_reg_pci_event(struct cnss_pci_data *pci_priv);
88 void cnss_dereg_pci_event(struct cnss_pci_data *pci_priv);
89
90 /**
91 * cnss_wlan_adsp_pc_enable: Control ADSP power collapse setup
92 * @dev: Platform driver pci private data structure
93 * @control: Power collapse enable / disable
94 *
95 * This function controls ADSP power collapse (PC). It must be called
96 * based on wlan state. ADSP power collapse during wlan RTPM suspend state
97 * results in delay during periodic QMI stats PCI link up/down. This delay
98 * causes additional power consumption.
99 *
100 * Result: 0 Success. negative error codes.
101 */
102 int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv,
103 bool control);
104 int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up);
105 int cnss_pci_prevent_l1(struct device *dev);
106 void cnss_pci_allow_l1(struct device *dev);
107 int cnss_pci_get_msi_assignment(struct cnss_pci_data *pci_priv);
108 int cnss_pci_get_one_msi_assignment(struct cnss_pci_data *pci_priv);
109 bool cnss_pci_fallback_one_msi(struct cnss_pci_data *pci_priv,
110 int *num_vectors);
111 bool cnss_pci_is_one_msi(struct cnss_pci_data *pci_priv);
112 int cnss_pci_get_one_msi_mhi_irq_array_size(struct cnss_pci_data *pci_priv);
113 bool cnss_pci_is_force_one_msi(struct cnss_pci_data *pci_priv);
114 int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv);
115 void cnss_pci_update_drv_supported(struct cnss_pci_data *pci_priv);
116
117 /**
118 * _cnss_pci_get_reg_dump() - Dump PCIe RC registers for debug
119 * @pci_priv: driver PCI bus context pointer
120 * @buf: destination buffer pointer
121 * @len: length of the buffer
122 *
123 * This function shall call corresponding PCIe root complex driver API
124 * to dump PCIe RC registers for debug purpose.
125 *
126 * Return: 0 for success, negative value for error
127 */
128 int _cnss_pci_get_reg_dump(struct cnss_pci_data *pci_priv,
129 u8 *buf, u32 len);
130 #else
_cnss_pci_enumerate(struct cnss_plat_data * plat_priv,u32 rc_num)131 int _cnss_pci_enumerate(struct cnss_plat_data *plat_priv, u32 rc_num)
132 {
133 return -EOPNOTSUPP;
134 }
135
cnss_pci_assert_perst(struct cnss_pci_data * pci_priv)136 int cnss_pci_assert_perst(struct cnss_pci_data *pci_priv)
137 {
138 return -EOPNOTSUPP;
139 }
140
cnss_pci_disable_pc(struct cnss_pci_data * pci_priv,bool vote)141 int cnss_pci_disable_pc(struct cnss_pci_data *pci_priv, bool vote)
142 {
143 return 0;
144 }
145
cnss_pci_set_link_bandwidth(struct cnss_pci_data * pci_priv,u16 link_speed,u16 link_width)146 int cnss_pci_set_link_bandwidth(struct cnss_pci_data *pci_priv,
147 u16 link_speed, u16 link_width)
148 {
149 return 0;
150 }
151
cnss_pci_set_max_link_speed(struct cnss_pci_data * pci_priv,u32 rc_num,u16 link_speed)152 int cnss_pci_set_max_link_speed(struct cnss_pci_data *pci_priv,
153 u32 rc_num, u16 link_speed)
154 {
155 return 0;
156 }
157
cnss_reg_pci_event(struct cnss_pci_data * pci_priv)158 int cnss_reg_pci_event(struct cnss_pci_data *pci_priv)
159 {
160 return 0;
161 }
162
cnss_dereg_pci_event(struct cnss_pci_data * pci_priv)163 void cnss_dereg_pci_event(struct cnss_pci_data *pci_priv) {}
164
cnss_wlan_adsp_pc_enable(struct cnss_pci_data * pci_priv,bool control)165 int cnss_wlan_adsp_pc_enable(struct cnss_pci_data *pci_priv, bool control)
166 {
167 return 0;
168 }
169
cnss_set_pci_link(struct cnss_pci_data * pci_priv,bool link_up)170 int cnss_set_pci_link(struct cnss_pci_data *pci_priv, bool link_up)
171 {
172 return 0;
173 }
174
cnss_pci_prevent_l1(struct device * dev)175 int cnss_pci_prevent_l1(struct device *dev)
176 {
177 return 0;
178 }
179 EXPORT_SYMBOL(cnss_pci_prevent_l1);
180
cnss_pci_allow_l1(struct device * dev)181 void cnss_pci_allow_l1(struct device *dev)
182 {
183 }
184 EXPORT_SYMBOL(cnss_pci_allow_l1);
185
cnss_pci_get_msi_assignment(struct cnss_pci_data * pci_priv)186 int cnss_pci_get_msi_assignment(struct cnss_pci_data *pci_priv)
187 {
188 return 0;
189 }
190
cnss_pci_init_smmu(struct cnss_pci_data * pci_priv)191 int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv)
192 {
193 return 0;
194 }
195
_cnss_pci_get_reg_dump(struct cnss_pci_data * pci_priv,u8 * buf,u32 len)196 int _cnss_pci_get_reg_dump(struct cnss_pci_data *pci_priv,
197 u8 *buf, u32 len)
198 {
199 return 0;
200 }
201
cnss_pci_update_drv_supported(struct cnss_pci_data * pci_priv)202 void cnss_pci_update_drv_supported(struct cnss_pci_data *pci_priv)
203 {
204 pci_priv->drv_supported = false;
205 }
206
207 #endif /* CONFIG_PCI_MSM */
208
cnss_pci_get_drv_supported(struct cnss_pci_data * pci_priv)209 static inline bool cnss_pci_get_drv_supported(struct cnss_pci_data *pci_priv)
210 {
211 return pci_priv->drv_supported;
212 }
213
214 #if IS_ENABLED(CONFIG_ARCH_QCOM)
215 int cnss_pci_of_reserved_mem_device_init(struct cnss_pci_data *pci_priv);
216 int cnss_pci_wake_gpio_init(struct cnss_pci_data *pci_priv);
217 void cnss_pci_wake_gpio_deinit(struct cnss_pci_data *pci_priv);
218 #endif /* CONFIG_ARCH_QCOM */
219 #endif /* _CNSS_PCI_PLATFORM_H*/
220