1 /*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10 #include <linux/pci.h>
11 #include <misc/cxl.h>
12 #include "cxl.h"
13
cxl_dma_set_mask(struct pci_dev * pdev,u64 dma_mask)14 static int cxl_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
15 {
16 if (dma_mask < DMA_BIT_MASK(64)) {
17 pr_info("%s only 64bit DMA supported on CXL", __func__);
18 return -EIO;
19 }
20
21 *(pdev->dev.dma_mask) = dma_mask;
22 return 0;
23 }
24
cxl_pci_probe_mode(struct pci_bus * bus)25 static int cxl_pci_probe_mode(struct pci_bus *bus)
26 {
27 return PCI_PROBE_NORMAL;
28 }
29
cxl_setup_msi_irqs(struct pci_dev * pdev,int nvec,int type)30 static int cxl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
31 {
32 return -ENODEV;
33 }
34
cxl_teardown_msi_irqs(struct pci_dev * pdev)35 static void cxl_teardown_msi_irqs(struct pci_dev *pdev)
36 {
37 /*
38 * MSI should never be set but need still need to provide this call
39 * back.
40 */
41 }
42
cxl_pci_enable_device_hook(struct pci_dev * dev)43 static bool cxl_pci_enable_device_hook(struct pci_dev *dev)
44 {
45 struct pci_controller *phb;
46 struct cxl_afu *afu;
47 struct cxl_context *ctx;
48
49 phb = pci_bus_to_host(dev->bus);
50 afu = (struct cxl_afu *)phb->private_data;
51
52 if (!cxl_ops->link_ok(afu->adapter, afu)) {
53 dev_warn(&dev->dev, "%s: Device link is down, refusing to enable AFU\n", __func__);
54 return false;
55 }
56
57 set_dma_ops(&dev->dev, &dma_nommu_ops);
58 set_dma_offset(&dev->dev, PAGE_OFFSET);
59
60 /*
61 * Allocate a context to do cxl things too. If we eventually do real
62 * DMA ops, we'll need a default context to attach them to
63 */
64 ctx = cxl_dev_context_init(dev);
65 if (IS_ERR(ctx))
66 return false;
67 dev->dev.archdata.cxl_ctx = ctx;
68
69 return (cxl_ops->afu_check_and_enable(afu) == 0);
70 }
71
cxl_pci_disable_device(struct pci_dev * dev)72 static void cxl_pci_disable_device(struct pci_dev *dev)
73 {
74 struct cxl_context *ctx = cxl_get_context(dev);
75
76 if (ctx) {
77 if (ctx->status == STARTED) {
78 dev_err(&dev->dev, "Default context started\n");
79 return;
80 }
81 dev->dev.archdata.cxl_ctx = NULL;
82 cxl_release_context(ctx);
83 }
84 }
85
cxl_pci_window_alignment(struct pci_bus * bus,unsigned long type)86 static resource_size_t cxl_pci_window_alignment(struct pci_bus *bus,
87 unsigned long type)
88 {
89 return 1;
90 }
91
cxl_pci_reset_secondary_bus(struct pci_dev * dev)92 static void cxl_pci_reset_secondary_bus(struct pci_dev *dev)
93 {
94 /* Should we do an AFU reset here ? */
95 }
96
cxl_pcie_cfg_record(u8 bus,u8 devfn)97 static int cxl_pcie_cfg_record(u8 bus, u8 devfn)
98 {
99 return (bus << 8) + devfn;
100 }
101
pci_bus_to_afu(struct pci_bus * bus)102 static inline struct cxl_afu *pci_bus_to_afu(struct pci_bus *bus)
103 {
104 struct pci_controller *phb = bus ? pci_bus_to_host(bus) : NULL;
105
106 return phb ? phb->private_data : NULL;
107 }
108
cxl_afu_configured_put(struct cxl_afu * afu)109 static void cxl_afu_configured_put(struct cxl_afu *afu)
110 {
111 atomic_dec_if_positive(&afu->configured_state);
112 }
113
cxl_afu_configured_get(struct cxl_afu * afu)114 static bool cxl_afu_configured_get(struct cxl_afu *afu)
115 {
116 return atomic_inc_unless_negative(&afu->configured_state);
117 }
118
cxl_pcie_config_info(struct pci_bus * bus,unsigned int devfn,struct cxl_afu * afu,int * _record)119 static inline int cxl_pcie_config_info(struct pci_bus *bus, unsigned int devfn,
120 struct cxl_afu *afu, int *_record)
121 {
122 int record;
123
124 record = cxl_pcie_cfg_record(bus->number, devfn);
125 if (record > afu->crs_num)
126 return PCIBIOS_DEVICE_NOT_FOUND;
127
128 *_record = record;
129 return 0;
130 }
131
cxl_pcie_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)132 static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
133 int offset, int len, u32 *val)
134 {
135 int rc, record;
136 struct cxl_afu *afu;
137 u8 val8;
138 u16 val16;
139 u32 val32;
140
141 afu = pci_bus_to_afu(bus);
142 /* Grab a reader lock on afu. */
143 if (afu == NULL || !cxl_afu_configured_get(afu))
144 return PCIBIOS_DEVICE_NOT_FOUND;
145
146 rc = cxl_pcie_config_info(bus, devfn, afu, &record);
147 if (rc)
148 goto out;
149
150 switch (len) {
151 case 1:
152 rc = cxl_ops->afu_cr_read8(afu, record, offset, &val8);
153 *val = val8;
154 break;
155 case 2:
156 rc = cxl_ops->afu_cr_read16(afu, record, offset, &val16);
157 *val = val16;
158 break;
159 case 4:
160 rc = cxl_ops->afu_cr_read32(afu, record, offset, &val32);
161 *val = val32;
162 break;
163 default:
164 WARN_ON(1);
165 }
166
167 out:
168 cxl_afu_configured_put(afu);
169 return rc ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
170 }
171
cxl_pcie_write_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 val)172 static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
173 int offset, int len, u32 val)
174 {
175 int rc, record;
176 struct cxl_afu *afu;
177
178 afu = pci_bus_to_afu(bus);
179 /* Grab a reader lock on afu. */
180 if (afu == NULL || !cxl_afu_configured_get(afu))
181 return PCIBIOS_DEVICE_NOT_FOUND;
182
183 rc = cxl_pcie_config_info(bus, devfn, afu, &record);
184 if (rc)
185 goto out;
186
187 switch (len) {
188 case 1:
189 rc = cxl_ops->afu_cr_write8(afu, record, offset, val & 0xff);
190 break;
191 case 2:
192 rc = cxl_ops->afu_cr_write16(afu, record, offset, val & 0xffff);
193 break;
194 case 4:
195 rc = cxl_ops->afu_cr_write32(afu, record, offset, val);
196 break;
197 default:
198 WARN_ON(1);
199 }
200
201 out:
202 cxl_afu_configured_put(afu);
203 return rc ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
204 }
205
206 static struct pci_ops cxl_pcie_pci_ops =
207 {
208 .read = cxl_pcie_read_config,
209 .write = cxl_pcie_write_config,
210 };
211
212
213 static struct pci_controller_ops cxl_pci_controller_ops =
214 {
215 .probe_mode = cxl_pci_probe_mode,
216 .enable_device_hook = cxl_pci_enable_device_hook,
217 .disable_device = cxl_pci_disable_device,
218 .release_device = cxl_pci_disable_device,
219 .window_alignment = cxl_pci_window_alignment,
220 .reset_secondary_bus = cxl_pci_reset_secondary_bus,
221 .setup_msi_irqs = cxl_setup_msi_irqs,
222 .teardown_msi_irqs = cxl_teardown_msi_irqs,
223 .dma_set_mask = cxl_dma_set_mask,
224 };
225
cxl_pci_vphb_add(struct cxl_afu * afu)226 int cxl_pci_vphb_add(struct cxl_afu *afu)
227 {
228 struct pci_controller *phb;
229 struct device_node *vphb_dn;
230 struct device *parent;
231
232 /*
233 * If there are no AFU configuration records we won't have anything to
234 * expose under the vPHB, so skip creating one, returning success since
235 * this is still a valid case. This will also opt us out of EEH
236 * handling since we won't have anything special to do if there are no
237 * kernel drivers attached to the vPHB, and EEH handling is not yet
238 * supported in the peer model.
239 */
240 if (!afu->crs_num)
241 return 0;
242
243 /* The parent device is the adapter. Reuse the device node of
244 * the adapter.
245 * We don't seem to care what device node is used for the vPHB,
246 * but tools such as lsvpd walk up the device parents looking
247 * for a valid location code, so we might as well show devices
248 * attached to the adapter as being located on that adapter.
249 */
250 parent = afu->adapter->dev.parent;
251 vphb_dn = parent->of_node;
252
253 /* Alloc and setup PHB data structure */
254 phb = pcibios_alloc_controller(vphb_dn);
255 if (!phb)
256 return -ENODEV;
257
258 /* Setup parent in sysfs */
259 phb->parent = parent;
260
261 /* Setup the PHB using arch provided callback */
262 phb->ops = &cxl_pcie_pci_ops;
263 phb->cfg_addr = NULL;
264 phb->cfg_data = NULL;
265 phb->private_data = afu;
266 phb->controller_ops = cxl_pci_controller_ops;
267
268 /* Scan the bus */
269 pcibios_scan_phb(phb);
270 if (phb->bus == NULL)
271 return -ENXIO;
272
273 /* Set release hook on root bus */
274 pci_set_host_bridge_release(to_pci_host_bridge(phb->bus->bridge),
275 pcibios_free_controller_deferred,
276 (void *) phb);
277
278 /* Claim resources. This might need some rework as well depending
279 * whether we are doing probe-only or not, like assigning unassigned
280 * resources etc...
281 */
282 pcibios_claim_one_bus(phb->bus);
283
284 /* Add probed PCI devices to the device model */
285 pci_bus_add_devices(phb->bus);
286
287 afu->phb = phb;
288
289 return 0;
290 }
291
cxl_pci_vphb_remove(struct cxl_afu * afu)292 void cxl_pci_vphb_remove(struct cxl_afu *afu)
293 {
294 struct pci_controller *phb;
295
296 /* If there is no configuration record we won't have one of these */
297 if (!afu || !afu->phb)
298 return;
299
300 phb = afu->phb;
301 afu->phb = NULL;
302
303 pci_remove_root_bus(phb->bus);
304 /*
305 * We don't free phb here - that's handled by
306 * pcibios_free_controller_deferred()
307 */
308 }
309
cxl_pci_is_vphb_device(struct pci_dev * dev)310 bool cxl_pci_is_vphb_device(struct pci_dev *dev)
311 {
312 struct pci_controller *phb;
313
314 phb = pci_bus_to_host(dev->bus);
315
316 return (phb->ops == &cxl_pcie_pci_ops);
317 }
318
cxl_pci_to_afu(struct pci_dev * dev)319 struct cxl_afu *cxl_pci_to_afu(struct pci_dev *dev)
320 {
321 struct pci_controller *phb;
322
323 phb = pci_bus_to_host(dev->bus);
324
325 return (struct cxl_afu *)phb->private_data;
326 }
327 EXPORT_SYMBOL_GPL(cxl_pci_to_afu);
328
cxl_pci_to_cfg_record(struct pci_dev * dev)329 unsigned int cxl_pci_to_cfg_record(struct pci_dev *dev)
330 {
331 return cxl_pcie_cfg_record(dev->bus->number, dev->devfn);
332 }
333 EXPORT_SYMBOL_GPL(cxl_pci_to_cfg_record);
334