1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * For more information, please consult the following manuals (look at
10 * http://www.pcisig.com/ for how to get them):
11 *
12 * PCI BIOS Specification
13 * PCI Local Bus Specification
14 * PCI to PCI Bridge Specification
15 * PCI System Design Guide
16 */
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20
21 #include <linux/mod_devicetable.h>
22
23 #include <linux/types.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/list.h>
27 #include <linux/compiler.h>
28 #include <linux/errno.h>
29 #include <linux/kobject.h>
30 #include <linux/atomic.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/resource_ext.h>
35 #include <uapi/linux/pci.h>
36
37 #include <linux/pci_ids.h>
38
39 /*
40 * The PCI interface treats multi-function devices as independent
41 * devices. The slot/function address of each device is encoded
42 * in a single byte as follows:
43 *
44 * 7:3 = slot
45 * 2:0 = function
46 *
47 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here.
50 */
51 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
55 /* pci_slot represents a physical slot */
56 struct pci_slot {
57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 struct kobject kobj;
62 };
63
pci_slot_name(const struct pci_slot * slot)64 static inline const char *pci_slot_name(const struct pci_slot *slot)
65 {
66 return kobject_name(&slot->kobj);
67 }
68
69 /* File state for mmap()s on /proc/bus/pci/X/Y */
70 enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73 };
74
75 /* For PCI devices, the region numbers are assigned this way: */
76 enum {
77 /* #0-5: standard PCI resources */
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81 /* #6: expansion ROM resource */
82 PCI_ROM_RESOURCE,
83
84 /* Device-specific resources */
85 #ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88 #endif
89
90 /* Resources assigned to buses behind the bridge */
91 #define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
97 /* Total resources associated with a PCI device */
98 PCI_NUM_RESOURCES,
99
100 /* Preserve this for compatibility */
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102 };
103
104 /**
105 * enum pci_interrupt_pin - PCI INTx interrupt values
106 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
107 * @PCI_INTERRUPT_INTA: PCI INTA pin
108 * @PCI_INTERRUPT_INTB: PCI INTB pin
109 * @PCI_INTERRUPT_INTC: PCI INTC pin
110 * @PCI_INTERRUPT_INTD: PCI INTD pin
111 *
112 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
113 * PCI_INTERRUPT_PIN register.
114 */
115 enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
117 PCI_INTERRUPT_INTA,
118 PCI_INTERRUPT_INTB,
119 PCI_INTERRUPT_INTC,
120 PCI_INTERRUPT_INTD,
121 };
122
123 /* The number of legacy PCI INTx interrupts */
124 #define PCI_NUM_INTX 4
125
126 /*
127 * pci_power_t values must match the bits in the Capabilities PME_Support
128 * and Control/Status PowerState fields in the Power Management capability.
129 */
130 typedef int __bitwise pci_power_t;
131
132 #define PCI_D0 ((pci_power_t __force) 0)
133 #define PCI_D1 ((pci_power_t __force) 1)
134 #define PCI_D2 ((pci_power_t __force) 2)
135 #define PCI_D3hot ((pci_power_t __force) 3)
136 #define PCI_D3cold ((pci_power_t __force) 4)
137 #define PCI_UNKNOWN ((pci_power_t __force) 5)
138 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
139
140 /* Remember to update this when the list above changes! */
141 extern const char *pci_power_names[];
142
pci_power_name(pci_power_t state)143 static inline const char *pci_power_name(pci_power_t state)
144 {
145 return pci_power_names[1 + (__force int) state];
146 }
147
148 #define PCI_PM_D2_DELAY 200
149 #define PCI_PM_D3_WAIT 10
150 #define PCI_PM_D3COLD_WAIT 100
151 #define PCI_PM_BUS_WAIT 50
152
153 /**
154 * The pci_channel state describes connectivity between the CPU and
155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
157 */
158 typedef unsigned int __bitwise pci_channel_state_t;
159
160 enum pci_channel_state {
161 /* I/O channel is in normal state */
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
163
164 /* I/O to channel is blocked */
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166
167 /* PCI card is dead */
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169 };
170
171 typedef unsigned int __bitwise pcie_reset_state_t;
172
173 enum pcie_reset_state {
174 /* Reset is NOT asserted (Use to deassert reset) */
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176
177 /* Use #PERST to reset PCIe device */
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
179
180 /* Use PCIe Hot Reset to reset device */
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
182 };
183
184 typedef unsigned short __bitwise pci_dev_flags_t;
185 enum pci_dev_flags {
186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188 /* Device configuration is irrevocably lost if disabled into D3 */
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190 /* Provide indication device is assigned by a Virtual Machine Manager */
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192 /* Flag for quirk use to store if quirk-specific ACS is enabled */
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196 /* Do not use bus resets for device */
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198 /* Do not use PM reset even if device advertises NoSoftRst- */
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200 /* Get VPD from function 0 VPD */
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202 /* A non-root bridge where translation occurs, stop alias search here */
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204 /* Do not use FLR even if device advertises PCI_AF_CAP */
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206 /* Don't use Relaxed Ordering for TLPs directed at this device */
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
208 /* Device does honor MSI masking despite saying otherwise */
209 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
210 };
211
212 enum pci_irq_reroute_variant {
213 INTEL_IRQ_REROUTE_VARIANT = 1,
214 MAX_IRQ_REROUTE_VARIANTS = 3
215 };
216
217 typedef unsigned short __bitwise pci_bus_flags_t;
218 enum pci_bus_flags {
219 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
220 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
221 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
222 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
223 };
224
225 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
226 enum pcie_link_width {
227 PCIE_LNK_WIDTH_RESRV = 0x00,
228 PCIE_LNK_X1 = 0x01,
229 PCIE_LNK_X2 = 0x02,
230 PCIE_LNK_X4 = 0x04,
231 PCIE_LNK_X8 = 0x08,
232 PCIE_LNK_X12 = 0x0c,
233 PCIE_LNK_X16 = 0x10,
234 PCIE_LNK_X32 = 0x20,
235 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
236 };
237
238 /* Based on the PCI Hotplug Spec, but some values are made up by us */
239 enum pci_bus_speed {
240 PCI_SPEED_33MHz = 0x00,
241 PCI_SPEED_66MHz = 0x01,
242 PCI_SPEED_66MHz_PCIX = 0x02,
243 PCI_SPEED_100MHz_PCIX = 0x03,
244 PCI_SPEED_133MHz_PCIX = 0x04,
245 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
246 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
247 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
248 PCI_SPEED_66MHz_PCIX_266 = 0x09,
249 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
250 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
251 AGP_UNKNOWN = 0x0c,
252 AGP_1X = 0x0d,
253 AGP_2X = 0x0e,
254 AGP_4X = 0x0f,
255 AGP_8X = 0x10,
256 PCI_SPEED_66MHz_PCIX_533 = 0x11,
257 PCI_SPEED_100MHz_PCIX_533 = 0x12,
258 PCI_SPEED_133MHz_PCIX_533 = 0x13,
259 PCIE_SPEED_2_5GT = 0x14,
260 PCIE_SPEED_5_0GT = 0x15,
261 PCIE_SPEED_8_0GT = 0x16,
262 PCIE_SPEED_16_0GT = 0x17,
263 PCIE_SPEED_32_0GT = 0x18,
264 PCI_SPEED_UNKNOWN = 0xff,
265 };
266
267 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
268 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
269
270 struct pci_cap_saved_data {
271 u16 cap_nr;
272 bool cap_extended;
273 unsigned int size;
274 u32 data[0];
275 };
276
277 struct pci_cap_saved_state {
278 struct hlist_node next;
279 struct pci_cap_saved_data cap;
280 };
281
282 struct irq_affinity;
283 struct pcie_link_state;
284 struct pci_vpd;
285 struct pci_sriov;
286 struct pci_ats;
287
288 /* The pci_dev structure describes PCI devices */
289 struct pci_dev {
290 struct list_head bus_list; /* Node in per-bus list */
291 struct pci_bus *bus; /* Bus this device is on */
292 struct pci_bus *subordinate; /* Bus this device bridges to */
293
294 void *sysdata; /* Hook for sys-specific extension */
295 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
296 struct pci_slot *slot; /* Physical slot this device is in */
297
298 unsigned int devfn; /* Encoded device & function index */
299 unsigned short vendor;
300 unsigned short device;
301 unsigned short subsystem_vendor;
302 unsigned short subsystem_device;
303 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
304 u8 revision; /* PCI revision, low byte of class word */
305 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
306 #ifdef CONFIG_PCIEAER
307 u16 aer_cap; /* AER capability offset */
308 struct aer_stats *aer_stats; /* AER stats for this device */
309 #endif
310 u8 pcie_cap; /* PCIe capability offset */
311 u8 msi_cap; /* MSI capability offset */
312 u8 msix_cap; /* MSI-X capability offset */
313 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
314 u8 rom_base_reg; /* Config register controlling ROM */
315 u8 pin; /* Interrupt pin this device uses */
316 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
317 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
318
319 struct pci_driver *driver; /* Driver bound to this device */
320 u64 dma_mask; /* Mask of the bits of bus address this
321 device implements. Normally this is
322 0xffffffff. You only need to change
323 this if your device has broken DMA
324 or supports 64-bit transfers. */
325
326 struct device_dma_parameters dma_parms;
327
328 pci_power_t current_state; /* Current operating state. In ACPI,
329 this is D0-D3, D0 being fully
330 functional, and D3 being off. */
331 u8 pm_cap; /* PM capability offset */
332 unsigned int pme_support:5; /* Bitmask of states from which PME#
333 can be generated */
334 unsigned int pme_poll:1; /* Poll device's PME status bit */
335 unsigned int d1_support:1; /* Low power state D1 is supported */
336 unsigned int d2_support:1; /* Low power state D2 is supported */
337 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
338 unsigned int no_d3cold:1; /* D3cold is forbidden */
339 unsigned int bridge_d3:1; /* Allow D3 for bridge */
340 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
341 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
342 decoding during BAR sizing */
343 unsigned int wakeup_prepared:1;
344 unsigned int runtime_d3cold:1; /* Whether go through runtime
345 D3cold, not set for devices
346 powered on/off by the
347 corresponding bridge */
348 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
349 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
350 controlled exclusively by
351 user sysfs */
352 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
353 bit manually */
354 unsigned int d3_delay; /* D3->D0 transition time in ms */
355 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
356
357 #ifdef CONFIG_PCIEASPM
358 struct pcie_link_state *link_state; /* ASPM link state */
359 unsigned int ltr_path:1; /* Latency Tolerance Reporting
360 supported from root to here */
361 #endif
362 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
363
364 pci_channel_state_t error_state; /* Current connectivity state */
365 struct device dev; /* Generic device interface */
366
367 int cfg_size; /* Size of config space */
368
369 /*
370 * Instead of touching interrupt line and base address registers
371 * directly, use the values stored here. They might be different!
372 */
373 unsigned int irq;
374 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
375
376 bool match_driver; /* Skip attaching driver */
377
378 unsigned int transparent:1; /* Subtractive decode bridge */
379 unsigned int io_window:1; /* Bridge has I/O window */
380 unsigned int pref_window:1; /* Bridge has pref mem window */
381 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
382 unsigned int multifunction:1; /* Multi-function device */
383
384 unsigned int is_busmaster:1; /* Is busmaster */
385 unsigned int no_msi:1; /* May not use MSI */
386 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
387 unsigned int block_cfg_access:1; /* Config space access blocked */
388 unsigned int broken_parity_status:1; /* Generates false positive parity */
389 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
390 unsigned int msi_enabled:1;
391 unsigned int msix_enabled:1;
392 unsigned int ari_enabled:1; /* ARI forwarding */
393 unsigned int ats_enabled:1; /* Address Translation Svc */
394 unsigned int pasid_enabled:1; /* Process Address Space ID */
395 unsigned int pri_enabled:1; /* Page Request Interface */
396 unsigned int is_managed:1;
397 unsigned int needs_freset:1; /* Requires fundamental reset */
398 unsigned int state_saved:1;
399 unsigned int is_physfn:1;
400 unsigned int is_virtfn:1;
401 unsigned int reset_fn:1;
402 unsigned int is_hotplug_bridge:1;
403 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
404 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
405 unsigned int __aer_firmware_first_valid:1;
406 unsigned int __aer_firmware_first:1;
407 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
408 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
409 unsigned int irq_managed:1;
410 unsigned int has_secondary_link:1;
411 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
412 unsigned int is_probed:1; /* Device probing in progress */
413 pci_dev_flags_t dev_flags;
414 atomic_t enable_cnt; /* pci_enable_device has been called */
415
416 u32 saved_config_space[16]; /* Config space saved at suspend time */
417 struct hlist_head saved_cap_space;
418 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
419 int rom_attr_enabled; /* Display of ROM attribute enabled? */
420 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
421 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
422
423 #ifdef CONFIG_HOTPLUG_PCI_PCIE
424 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
425 #endif
426 #ifdef CONFIG_PCIE_PTM
427 unsigned int ptm_root:1;
428 unsigned int ptm_enabled:1;
429 u8 ptm_granularity;
430 #endif
431 #ifdef CONFIG_PCI_MSI
432 const struct attribute_group **msi_irq_groups;
433 #endif
434 struct pci_vpd *vpd;
435 #ifdef CONFIG_PCI_ATS
436 union {
437 struct pci_sriov *sriov; /* PF: SR-IOV info */
438 struct pci_dev *physfn; /* VF: related PF */
439 };
440 u16 ats_cap; /* ATS Capability offset */
441 u8 ats_stu; /* ATS Smallest Translation Unit */
442 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
443 #endif
444 #ifdef CONFIG_PCI_PRI
445 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
446 #endif
447 #ifdef CONFIG_PCI_PASID
448 u16 pasid_features;
449 #endif
450 phys_addr_t rom; /* Physical address if not from BAR */
451 size_t romlen; /* Length if not from BAR */
452 char *driver_override; /* Driver name to force a match */
453
454 unsigned long priv_flags; /* Private flags for the PCI driver */
455 };
456
pci_physfn(struct pci_dev * dev)457 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
458 {
459 #ifdef CONFIG_PCI_IOV
460 if (dev->is_virtfn)
461 dev = dev->physfn;
462 #endif
463 return dev;
464 }
465
466 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
467
468 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
469 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
470
pci_channel_offline(struct pci_dev * pdev)471 static inline int pci_channel_offline(struct pci_dev *pdev)
472 {
473 return (pdev->error_state != pci_channel_io_normal);
474 }
475
476 struct pci_host_bridge {
477 struct device dev;
478 struct pci_bus *bus; /* Root bus */
479 struct pci_ops *ops;
480 void *sysdata;
481 int busnr;
482 struct list_head windows; /* resource_entry */
483 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
484 int (*map_irq)(const struct pci_dev *, u8, u8);
485 void (*release_fn)(struct pci_host_bridge *);
486 void *release_data;
487 struct msi_controller *msi;
488 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
489 unsigned int no_ext_tags:1; /* No Extended Tags */
490 unsigned int native_aer:1; /* OS may use PCIe AER */
491 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
492 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
493 unsigned int native_pme:1; /* OS may use PCIe PME */
494 unsigned int native_ltr:1; /* OS may use PCIe LTR */
495 /* Resource alignment requirements */
496 resource_size_t (*align_resource)(struct pci_dev *dev,
497 const struct resource *res,
498 resource_size_t start,
499 resource_size_t size,
500 resource_size_t align);
501 unsigned long private[0] ____cacheline_aligned;
502 };
503
504 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
505
pci_host_bridge_priv(struct pci_host_bridge * bridge)506 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
507 {
508 return (void *)bridge->private;
509 }
510
pci_host_bridge_from_priv(void * priv)511 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
512 {
513 return container_of(priv, struct pci_host_bridge, private);
514 }
515
516 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
517 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
518 size_t priv);
519 void pci_free_host_bridge(struct pci_host_bridge *bridge);
520 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
521
522 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
523 void (*release_fn)(struct pci_host_bridge *),
524 void *release_data);
525
526 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
527
528 /*
529 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
530 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
531 * buses below host bridges or subtractive decode bridges) go in the list.
532 * Use pci_bus_for_each_resource() to iterate through all the resources.
533 */
534
535 /*
536 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
537 * and there's no way to program the bridge with the details of the window.
538 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
539 * decode bit set, because they are explicit and can be programmed with _SRS.
540 */
541 #define PCI_SUBTRACTIVE_DECODE 0x1
542
543 struct pci_bus_resource {
544 struct list_head list;
545 struct resource *res;
546 unsigned int flags;
547 };
548
549 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
550
551 struct pci_bus {
552 struct list_head node; /* Node in list of buses */
553 struct pci_bus *parent; /* Parent bus this bridge is on */
554 struct list_head children; /* List of child buses */
555 struct list_head devices; /* List of devices on this bus */
556 struct pci_dev *self; /* Bridge device as seen by parent */
557 struct list_head slots; /* List of slots on this bus;
558 protected by pci_slot_mutex */
559 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
560 struct list_head resources; /* Address space routed to this bus */
561 struct resource busn_res; /* Bus numbers routed to this bus */
562
563 struct pci_ops *ops; /* Configuration access functions */
564 struct msi_controller *msi; /* MSI controller */
565 void *sysdata; /* Hook for sys-specific extension */
566 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
567
568 unsigned char number; /* Bus number */
569 unsigned char primary; /* Number of primary bridge */
570 unsigned char max_bus_speed; /* enum pci_bus_speed */
571 unsigned char cur_bus_speed; /* enum pci_bus_speed */
572 #ifdef CONFIG_PCI_DOMAINS_GENERIC
573 int domain_nr;
574 #endif
575
576 char name[48];
577
578 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
579 pci_bus_flags_t bus_flags; /* Inherited by child buses */
580 struct device *bridge;
581 struct device dev;
582 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
583 struct bin_attribute *legacy_mem; /* Legacy mem */
584 unsigned int is_added:1;
585 unsigned int unsafe_warn:1; /* warned about RW1C config write */
586 };
587
588 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
589
590 /*
591 * Returns true if the PCI bus is root (behind host-PCI bridge),
592 * false otherwise
593 *
594 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
595 * This is incorrect because "virtual" buses added for SR-IOV (via
596 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
597 */
pci_is_root_bus(struct pci_bus * pbus)598 static inline bool pci_is_root_bus(struct pci_bus *pbus)
599 {
600 return !(pbus->parent);
601 }
602
603 /**
604 * pci_is_bridge - check if the PCI device is a bridge
605 * @dev: PCI device
606 *
607 * Return true if the PCI device is bridge whether it has subordinate
608 * or not.
609 */
pci_is_bridge(struct pci_dev * dev)610 static inline bool pci_is_bridge(struct pci_dev *dev)
611 {
612 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
613 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
614 }
615
616 #define for_each_pci_bridge(dev, bus) \
617 list_for_each_entry(dev, &bus->devices, bus_list) \
618 if (!pci_is_bridge(dev)) {} else
619
pci_upstream_bridge(struct pci_dev * dev)620 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
621 {
622 dev = pci_physfn(dev);
623 if (pci_is_root_bus(dev->bus))
624 return NULL;
625
626 return dev->bus->self;
627 }
628
629 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
630 void pci_put_host_bridge_device(struct device *dev);
631
632 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)633 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
634 {
635 return pci_dev->msi_enabled || pci_dev->msix_enabled;
636 }
637 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)638 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
639 #endif
640
641 /* Error values that may be returned by PCI functions */
642 #define PCIBIOS_SUCCESSFUL 0x00
643 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
644 #define PCIBIOS_BAD_VENDOR_ID 0x83
645 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
646 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
647 #define PCIBIOS_SET_FAILED 0x88
648 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
649
650 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)651 static inline int pcibios_err_to_errno(int err)
652 {
653 if (err <= PCIBIOS_SUCCESSFUL)
654 return err; /* Assume already errno */
655
656 switch (err) {
657 case PCIBIOS_FUNC_NOT_SUPPORTED:
658 return -ENOENT;
659 case PCIBIOS_BAD_VENDOR_ID:
660 return -ENOTTY;
661 case PCIBIOS_DEVICE_NOT_FOUND:
662 return -ENODEV;
663 case PCIBIOS_BAD_REGISTER_NUMBER:
664 return -EFAULT;
665 case PCIBIOS_SET_FAILED:
666 return -EIO;
667 case PCIBIOS_BUFFER_TOO_SMALL:
668 return -ENOSPC;
669 }
670
671 return -ERANGE;
672 }
673
674 /* Low-level architecture-dependent routines */
675
676 struct pci_ops {
677 int (*add_bus)(struct pci_bus *bus);
678 void (*remove_bus)(struct pci_bus *bus);
679 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
680 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
681 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
682 };
683
684 /*
685 * ACPI needs to be able to access PCI config space before we've done a
686 * PCI bus scan and created pci_bus structures.
687 */
688 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
689 int reg, int len, u32 *val);
690 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
691 int reg, int len, u32 val);
692
693 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
694 typedef u64 pci_bus_addr_t;
695 #else
696 typedef u32 pci_bus_addr_t;
697 #endif
698
699 struct pci_bus_region {
700 pci_bus_addr_t start;
701 pci_bus_addr_t end;
702 };
703
704 struct pci_dynids {
705 spinlock_t lock; /* Protects list, index */
706 struct list_head list; /* For IDs added at runtime */
707 };
708
709
710 /*
711 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
712 * a set of callbacks in struct pci_error_handlers, that device driver
713 * will be notified of PCI bus errors, and will be driven to recovery
714 * when an error occurs.
715 */
716
717 typedef unsigned int __bitwise pci_ers_result_t;
718
719 enum pci_ers_result {
720 /* No result/none/not supported in device driver */
721 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
722
723 /* Device driver can recover without slot reset */
724 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
725
726 /* Device driver wants slot to be reset */
727 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
728
729 /* Device has completely failed, is unrecoverable */
730 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
731
732 /* Device driver is fully recovered and operational */
733 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
734
735 /* No AER capabilities registered for the driver */
736 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
737 };
738
739 /* PCI bus error event callbacks */
740 struct pci_error_handlers {
741 /* PCI bus error detected on this device */
742 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
743 enum pci_channel_state error);
744
745 /* MMIO has been re-enabled, but not DMA */
746 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
747
748 /* PCI slot has been reset */
749 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
750
751 /* PCI function reset prepare or completed */
752 void (*reset_prepare)(struct pci_dev *dev);
753 void (*reset_done)(struct pci_dev *dev);
754
755 /* Device driver may resume normal operations */
756 void (*resume)(struct pci_dev *dev);
757 };
758
759
760 struct module;
761 struct pci_driver {
762 struct list_head node;
763 const char *name;
764 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
765 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
766 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
767 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
768 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
769 int (*resume_early)(struct pci_dev *dev);
770 int (*resume) (struct pci_dev *dev); /* Device woken up */
771 void (*shutdown) (struct pci_dev *dev);
772 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
773 const struct pci_error_handlers *err_handler;
774 const struct attribute_group **groups;
775 struct device_driver driver;
776 struct pci_dynids dynids;
777 };
778
779 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
780
781 /**
782 * PCI_DEVICE - macro used to describe a specific PCI device
783 * @vend: the 16 bit PCI Vendor ID
784 * @dev: the 16 bit PCI Device ID
785 *
786 * This macro is used to create a struct pci_device_id that matches a
787 * specific device. The subvendor and subdevice fields will be set to
788 * PCI_ANY_ID.
789 */
790 #define PCI_DEVICE(vend,dev) \
791 .vendor = (vend), .device = (dev), \
792 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
793
794 /**
795 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
796 * @vend: the 16 bit PCI Vendor ID
797 * @dev: the 16 bit PCI Device ID
798 * @subvend: the 16 bit PCI Subvendor ID
799 * @subdev: the 16 bit PCI Subdevice ID
800 *
801 * This macro is used to create a struct pci_device_id that matches a
802 * specific device with subsystem information.
803 */
804 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
805 .vendor = (vend), .device = (dev), \
806 .subvendor = (subvend), .subdevice = (subdev)
807
808 /**
809 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
810 * @dev_class: the class, subclass, prog-if triple for this device
811 * @dev_class_mask: the class mask for this device
812 *
813 * This macro is used to create a struct pci_device_id that matches a
814 * specific PCI class. The vendor, device, subvendor, and subdevice
815 * fields will be set to PCI_ANY_ID.
816 */
817 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
818 .class = (dev_class), .class_mask = (dev_class_mask), \
819 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
820 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
821
822 /**
823 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
824 * @vend: the vendor name
825 * @dev: the 16 bit PCI Device ID
826 *
827 * This macro is used to create a struct pci_device_id that matches a
828 * specific PCI device. The subvendor, and subdevice fields will be set
829 * to PCI_ANY_ID. The macro allows the next field to follow as the device
830 * private data.
831 */
832 #define PCI_VDEVICE(vend, dev) \
833 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
834 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
835
836 /**
837 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
838 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
839 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
840 * @data: the driver data to be filled
841 *
842 * This macro is used to create a struct pci_device_id that matches a
843 * specific PCI device. The subvendor, and subdevice fields will be set
844 * to PCI_ANY_ID.
845 */
846 #define PCI_DEVICE_DATA(vend, dev, data) \
847 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
848 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
849 .driver_data = (kernel_ulong_t)(data)
850
851 enum {
852 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
853 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
854 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
855 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
856 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
857 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
858 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
859 };
860
861 /* These external functions are only available when PCI support is enabled */
862 #ifdef CONFIG_PCI
863
864 extern unsigned int pci_flags;
865
pci_set_flags(int flags)866 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)867 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)868 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)869 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
870
871 void pcie_bus_configure_settings(struct pci_bus *bus);
872
873 enum pcie_bus_config_types {
874 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
875 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
876 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
877 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
878 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
879 };
880
881 extern enum pcie_bus_config_types pcie_bus_config;
882
883 extern struct bus_type pci_bus_type;
884
885 /* Do NOT directly access these two variables, unless you are arch-specific PCI
886 * code, or PCI core code. */
887 extern struct list_head pci_root_buses; /* List of all known PCI buses */
888 /* Some device drivers need know if PCI is initiated */
889 int no_pci_devices(void);
890
891 void pcibios_resource_survey_bus(struct pci_bus *bus);
892 void pcibios_bus_add_device(struct pci_dev *pdev);
893 void pcibios_add_bus(struct pci_bus *bus);
894 void pcibios_remove_bus(struct pci_bus *bus);
895 void pcibios_fixup_bus(struct pci_bus *);
896 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
897 /* Architecture-specific versions may override this (weak) */
898 char *pcibios_setup(char *str);
899
900 /* Used only when drivers/pci/setup.c is used */
901 resource_size_t pcibios_align_resource(void *, const struct resource *,
902 resource_size_t,
903 resource_size_t);
904
905 /* Weak but can be overriden by arch */
906 void pci_fixup_cardbus(struct pci_bus *);
907
908 /* Generic PCI functions used internally */
909
910 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
911 struct resource *res);
912 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
913 struct pci_bus_region *region);
914 void pcibios_scan_specific_bus(int busn);
915 struct pci_bus *pci_find_bus(int domain, int busnr);
916 void pci_bus_add_devices(const struct pci_bus *bus);
917 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
918 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
919 struct pci_ops *ops, void *sysdata,
920 struct list_head *resources);
921 int pci_host_probe(struct pci_host_bridge *bridge);
922 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
923 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
924 void pci_bus_release_busn_res(struct pci_bus *b);
925 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
926 struct pci_ops *ops, void *sysdata,
927 struct list_head *resources);
928 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
929 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
930 int busnr);
931 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
932 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
933 const char *name,
934 struct hotplug_slot *hotplug);
935 void pci_destroy_slot(struct pci_slot *slot);
936 #ifdef CONFIG_SYSFS
937 void pci_dev_assign_slot(struct pci_dev *dev);
938 #else
pci_dev_assign_slot(struct pci_dev * dev)939 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
940 #endif
941 int pci_scan_slot(struct pci_bus *bus, int devfn);
942 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
943 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
944 unsigned int pci_scan_child_bus(struct pci_bus *bus);
945 void pci_bus_add_device(struct pci_dev *dev);
946 void pci_read_bridge_bases(struct pci_bus *child);
947 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
948 struct resource *res);
949 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
950 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
951 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
952 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
953 struct pci_dev *pci_dev_get(struct pci_dev *dev);
954 void pci_dev_put(struct pci_dev *dev);
955 void pci_remove_bus(struct pci_bus *b);
956 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
957 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
958 void pci_stop_root_bus(struct pci_bus *bus);
959 void pci_remove_root_bus(struct pci_bus *bus);
960 void pci_setup_cardbus(struct pci_bus *bus);
961 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
962 void pci_sort_breadthfirst(void);
963 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
964 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
965
966 /* Generic PCI functions exported to card drivers */
967
968 enum pci_lost_interrupt_reason {
969 PCI_LOST_IRQ_NO_INFORMATION = 0,
970 PCI_LOST_IRQ_DISABLE_MSI,
971 PCI_LOST_IRQ_DISABLE_MSIX,
972 PCI_LOST_IRQ_DISABLE_ACPI,
973 };
974 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
975 int pci_find_capability(struct pci_dev *dev, int cap);
976 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
977 int pci_find_ext_capability(struct pci_dev *dev, int cap);
978 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
979 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
980 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
981 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
982
983 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
984 struct pci_dev *from);
985 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
986 unsigned int ss_vendor, unsigned int ss_device,
987 struct pci_dev *from);
988 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
989 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
990 unsigned int devfn);
991 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
992 int pci_dev_present(const struct pci_device_id *ids);
993
994 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
995 int where, u8 *val);
996 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
997 int where, u16 *val);
998 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
999 int where, u32 *val);
1000 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1001 int where, u8 val);
1002 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1003 int where, u16 val);
1004 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1005 int where, u32 val);
1006
1007 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1008 int where, int size, u32 *val);
1009 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1010 int where, int size, u32 val);
1011 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1012 int where, int size, u32 *val);
1013 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1014 int where, int size, u32 val);
1015
1016 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1017
1018 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1019 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1020 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1021 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1022 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1023 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1024
1025 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1026 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1027 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1028 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1029 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1030 u16 clear, u16 set);
1031 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1032 u32 clear, u32 set);
1033
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1034 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1035 u16 set)
1036 {
1037 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1038 }
1039
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1040 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1041 u32 set)
1042 {
1043 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1044 }
1045
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1046 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1047 u16 clear)
1048 {
1049 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1050 }
1051
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1052 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1053 u32 clear)
1054 {
1055 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1056 }
1057
1058 /* User-space driven config access */
1059 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1060 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1061 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1062 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1063 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1064 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1065
1066 int __must_check pci_enable_device(struct pci_dev *dev);
1067 int __must_check pci_enable_device_io(struct pci_dev *dev);
1068 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1069 int __must_check pci_reenable_device(struct pci_dev *);
1070 int __must_check pcim_enable_device(struct pci_dev *pdev);
1071 void pcim_pin_device(struct pci_dev *pdev);
1072
pci_intx_mask_supported(struct pci_dev * pdev)1073 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1074 {
1075 /*
1076 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1077 * writable and no quirk has marked the feature broken.
1078 */
1079 return !pdev->broken_intx_masking;
1080 }
1081
pci_is_enabled(struct pci_dev * pdev)1082 static inline int pci_is_enabled(struct pci_dev *pdev)
1083 {
1084 return (atomic_read(&pdev->enable_cnt) > 0);
1085 }
1086
pci_is_managed(struct pci_dev * pdev)1087 static inline int pci_is_managed(struct pci_dev *pdev)
1088 {
1089 return pdev->is_managed;
1090 }
1091
1092 void pci_disable_device(struct pci_dev *dev);
1093
1094 extern unsigned int pcibios_max_latency;
1095 void pci_set_master(struct pci_dev *dev);
1096 void pci_clear_master(struct pci_dev *dev);
1097
1098 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1099 int pci_set_cacheline_size(struct pci_dev *dev);
1100 #define HAVE_PCI_SET_MWI
1101 int __must_check pci_set_mwi(struct pci_dev *dev);
1102 int __must_check pcim_set_mwi(struct pci_dev *dev);
1103 int pci_try_set_mwi(struct pci_dev *dev);
1104 void pci_clear_mwi(struct pci_dev *dev);
1105 void pci_intx(struct pci_dev *dev, int enable);
1106 bool pci_check_and_mask_intx(struct pci_dev *dev);
1107 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1108 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1109 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1110 int pcix_get_max_mmrbc(struct pci_dev *dev);
1111 int pcix_get_mmrbc(struct pci_dev *dev);
1112 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1113 int pcie_get_readrq(struct pci_dev *dev);
1114 int pcie_set_readrq(struct pci_dev *dev, int rq);
1115 int pcie_get_mps(struct pci_dev *dev);
1116 int pcie_set_mps(struct pci_dev *dev, int mps);
1117 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1118 enum pci_bus_speed *speed,
1119 enum pcie_link_width *width);
1120 void pcie_print_link_status(struct pci_dev *dev);
1121 bool pcie_has_flr(struct pci_dev *dev);
1122 int pcie_flr(struct pci_dev *dev);
1123 int __pci_reset_function_locked(struct pci_dev *dev);
1124 int pci_reset_function(struct pci_dev *dev);
1125 int pci_reset_function_locked(struct pci_dev *dev);
1126 int pci_try_reset_function(struct pci_dev *dev);
1127 int pci_probe_reset_slot(struct pci_slot *slot);
1128 int pci_probe_reset_bus(struct pci_bus *bus);
1129 int pci_reset_bus(struct pci_dev *dev);
1130 void pci_reset_secondary_bus(struct pci_dev *dev);
1131 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1132 void pci_update_resource(struct pci_dev *dev, int resno);
1133 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1134 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1135 void pci_release_resource(struct pci_dev *dev, int resno);
1136 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1137 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1138 bool pci_device_is_present(struct pci_dev *pdev);
1139 void pci_ignore_hotplug(struct pci_dev *dev);
1140
1141 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1142 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1143 const char *fmt, ...);
1144 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1145
1146 /* ROM control related routines */
1147 int pci_enable_rom(struct pci_dev *pdev);
1148 void pci_disable_rom(struct pci_dev *pdev);
1149 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1150 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1151
1152 /* Power management related routines */
1153 int pci_save_state(struct pci_dev *dev);
1154 void pci_restore_state(struct pci_dev *dev);
1155 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1156 int pci_load_saved_state(struct pci_dev *dev,
1157 struct pci_saved_state *state);
1158 int pci_load_and_free_saved_state(struct pci_dev *dev,
1159 struct pci_saved_state **state);
1160 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1161 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1162 u16 cap);
1163 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1164 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1165 u16 cap, unsigned int size);
1166 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1167 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1168 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1169 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1170 void pci_pme_active(struct pci_dev *dev, bool enable);
1171 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1172 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1173 int pci_prepare_to_sleep(struct pci_dev *dev);
1174 int pci_back_from_sleep(struct pci_dev *dev);
1175 bool pci_dev_run_wake(struct pci_dev *dev);
1176 bool pci_check_pme_status(struct pci_dev *dev);
1177 void pci_pme_wakeup_bus(struct pci_bus *bus);
1178 void pci_d3cold_enable(struct pci_dev *dev);
1179 void pci_d3cold_disable(struct pci_dev *dev);
1180 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1181 void pci_wakeup_bus(struct pci_bus *bus);
1182 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1183
1184 /* PCI Virtual Channel */
1185 int pci_save_vc_state(struct pci_dev *dev);
1186 void pci_restore_vc_state(struct pci_dev *dev);
1187 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1188
1189 /* For use by arch with custom probe code */
1190 void set_pcie_port_type(struct pci_dev *pdev);
1191 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1192
1193 /* Functions for PCI Hotplug drivers to use */
1194 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1195 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1196 unsigned int pci_rescan_bus(struct pci_bus *bus);
1197 void pci_lock_rescan_remove(void);
1198 void pci_unlock_rescan_remove(void);
1199
1200 /* Vital Product Data routines */
1201 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1202 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1203 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1204
1205 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1206 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1207 void pci_bus_assign_resources(const struct pci_bus *bus);
1208 void pci_bus_claim_resources(struct pci_bus *bus);
1209 void pci_bus_size_bridges(struct pci_bus *bus);
1210 int pci_claim_resource(struct pci_dev *, int);
1211 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1212 void pci_assign_unassigned_resources(void);
1213 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1214 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1215 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1216 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1217 void pdev_enable_device(struct pci_dev *);
1218 int pci_enable_resources(struct pci_dev *, int mask);
1219 void pci_assign_irq(struct pci_dev *dev);
1220 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1221 #define HAVE_PCI_REQ_REGIONS 2
1222 int __must_check pci_request_regions(struct pci_dev *, const char *);
1223 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1224 void pci_release_regions(struct pci_dev *);
1225 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1226 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1227 void pci_release_region(struct pci_dev *, int);
1228 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1229 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1230 void pci_release_selected_regions(struct pci_dev *, int);
1231
1232 /* drivers/pci/bus.c */
1233 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1234 void pci_bus_put(struct pci_bus *bus);
1235 void pci_add_resource(struct list_head *resources, struct resource *res);
1236 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1237 resource_size_t offset);
1238 void pci_free_resource_list(struct list_head *resources);
1239 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1240 unsigned int flags);
1241 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1242 void pci_bus_remove_resources(struct pci_bus *bus);
1243 int devm_request_pci_bus_resources(struct device *dev,
1244 struct list_head *resources);
1245
1246 /* Temporary until new and working PCI SBR API in place */
1247 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1248
1249 #define pci_bus_for_each_resource(bus, res, i) \
1250 for (i = 0; \
1251 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1252 i++)
1253
1254 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1255 struct resource *res, resource_size_t size,
1256 resource_size_t align, resource_size_t min,
1257 unsigned long type_mask,
1258 resource_size_t (*alignf)(void *,
1259 const struct resource *,
1260 resource_size_t,
1261 resource_size_t),
1262 void *alignf_data);
1263
1264
1265 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1266 resource_size_t size);
1267 unsigned long pci_address_to_pio(phys_addr_t addr);
1268 phys_addr_t pci_pio_to_address(unsigned long pio);
1269 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1270 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1271 phys_addr_t phys_addr);
1272 void pci_unmap_iospace(struct resource *res);
1273 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1274 resource_size_t offset,
1275 resource_size_t size);
1276 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1277 struct resource *res);
1278
pci_bus_address(struct pci_dev * pdev,int bar)1279 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1280 {
1281 struct pci_bus_region region;
1282
1283 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1284 return region.start;
1285 }
1286
1287 /* Proper probing supporting hot-pluggable devices */
1288 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1289 const char *mod_name);
1290
1291 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1292 #define pci_register_driver(driver) \
1293 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1294
1295 void pci_unregister_driver(struct pci_driver *dev);
1296
1297 /**
1298 * module_pci_driver() - Helper macro for registering a PCI driver
1299 * @__pci_driver: pci_driver struct
1300 *
1301 * Helper macro for PCI drivers which do not do anything special in module
1302 * init/exit. This eliminates a lot of boilerplate. Each module may only
1303 * use this macro once, and calling it replaces module_init() and module_exit()
1304 */
1305 #define module_pci_driver(__pci_driver) \
1306 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1307
1308 /**
1309 * builtin_pci_driver() - Helper macro for registering a PCI driver
1310 * @__pci_driver: pci_driver struct
1311 *
1312 * Helper macro for PCI drivers which do not do anything special in their
1313 * init code. This eliminates a lot of boilerplate. Each driver may only
1314 * use this macro once, and calling it replaces device_initcall(...)
1315 */
1316 #define builtin_pci_driver(__pci_driver) \
1317 builtin_driver(__pci_driver, pci_register_driver)
1318
1319 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1320 int pci_add_dynid(struct pci_driver *drv,
1321 unsigned int vendor, unsigned int device,
1322 unsigned int subvendor, unsigned int subdevice,
1323 unsigned int class, unsigned int class_mask,
1324 unsigned long driver_data);
1325 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1326 struct pci_dev *dev);
1327 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1328 int pass);
1329
1330 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1331 void *userdata);
1332 int pci_cfg_space_size(struct pci_dev *dev);
1333 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1334 void pci_setup_bridge(struct pci_bus *bus);
1335 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1336 unsigned long type);
1337
1338 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1339 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1340
1341 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1342 unsigned int command_bits, u32 flags);
1343
1344 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1345 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1346 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1347 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1348 #define PCI_IRQ_ALL_TYPES \
1349 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1350
1351 /* kmem_cache style wrapper around pci_alloc_consistent() */
1352
1353 #include <linux/pci-dma.h>
1354 #include <linux/dmapool.h>
1355
1356 #define pci_pool dma_pool
1357 #define pci_pool_create(name, pdev, size, align, allocation) \
1358 dma_pool_create(name, &pdev->dev, size, align, allocation)
1359 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1360 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1361 #define pci_pool_zalloc(pool, flags, handle) \
1362 dma_pool_zalloc(pool, flags, handle)
1363 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1364
1365 struct msix_entry {
1366 u32 vector; /* Kernel uses to write allocated vector */
1367 u16 entry; /* Driver uses to specify entry, OS writes */
1368 };
1369
1370 #ifdef CONFIG_PCI_MSI
1371 int pci_msi_vec_count(struct pci_dev *dev);
1372 void pci_disable_msi(struct pci_dev *dev);
1373 int pci_msix_vec_count(struct pci_dev *dev);
1374 void pci_disable_msix(struct pci_dev *dev);
1375 void pci_restore_msi_state(struct pci_dev *dev);
1376 int pci_msi_enabled(void);
1377 int pci_enable_msi(struct pci_dev *dev);
1378 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1379 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1380 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1381 struct msix_entry *entries, int nvec)
1382 {
1383 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1384 if (rc < 0)
1385 return rc;
1386 return 0;
1387 }
1388 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1389 unsigned int max_vecs, unsigned int flags,
1390 const struct irq_affinity *affd);
1391
1392 void pci_free_irq_vectors(struct pci_dev *dev);
1393 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1394 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1395 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1396
1397 #else
pci_msi_vec_count(struct pci_dev * dev)1398 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1399 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1400 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1401 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1402 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1403 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1404 static inline int pci_enable_msi(struct pci_dev *dev)
1405 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1406 static inline int pci_enable_msix_range(struct pci_dev *dev,
1407 struct msix_entry *entries, int minvec, int maxvec)
1408 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1409 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1410 struct msix_entry *entries, int nvec)
1411 { return -ENOSYS; }
1412
1413 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,const struct irq_affinity * aff_desc)1414 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1415 unsigned int max_vecs, unsigned int flags,
1416 const struct irq_affinity *aff_desc)
1417 {
1418 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1419 return 1;
1420 return -ENOSPC;
1421 }
1422
pci_free_irq_vectors(struct pci_dev * dev)1423 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1424 {
1425 }
1426
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1427 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1428 {
1429 if (WARN_ON_ONCE(nr > 0))
1430 return -EINVAL;
1431 return dev->irq;
1432 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1433 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1434 int vec)
1435 {
1436 return cpu_possible_mask;
1437 }
1438
pci_irq_get_node(struct pci_dev * pdev,int vec)1439 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1440 {
1441 return first_online_node;
1442 }
1443 #endif
1444
1445 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1446 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1447 unsigned int max_vecs, unsigned int flags)
1448 {
1449 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1450 NULL);
1451 }
1452
1453 /**
1454 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1455 * @d: the INTx IRQ domain
1456 * @node: the DT node for the device whose interrupt we're translating
1457 * @intspec: the interrupt specifier data from the DT
1458 * @intsize: the number of entries in @intspec
1459 * @out_hwirq: pointer at which to write the hwirq number
1460 * @out_type: pointer at which to write the interrupt type
1461 *
1462 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1463 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1464 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1465 * INTx value to obtain the hwirq number.
1466 *
1467 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1468 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1469 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1470 struct device_node *node,
1471 const u32 *intspec,
1472 unsigned int intsize,
1473 unsigned long *out_hwirq,
1474 unsigned int *out_type)
1475 {
1476 const u32 intx = intspec[0];
1477
1478 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1479 return -EINVAL;
1480
1481 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1482 return 0;
1483 }
1484
1485 #ifdef CONFIG_PCIEPORTBUS
1486 extern bool pcie_ports_disabled;
1487 extern bool pcie_ports_native;
1488 #else
1489 #define pcie_ports_disabled true
1490 #define pcie_ports_native false
1491 #endif
1492
1493 #ifdef CONFIG_PCIEASPM
1494 bool pcie_aspm_support_enabled(void);
1495 #else
pcie_aspm_support_enabled(void)1496 static inline bool pcie_aspm_support_enabled(void) { return false; }
1497 #endif
1498
1499 #ifdef CONFIG_PCIEAER
1500 bool pci_aer_available(void);
1501 #else
pci_aer_available(void)1502 static inline bool pci_aer_available(void) { return false; }
1503 #endif
1504
1505 #ifdef CONFIG_PCIE_ECRC
1506 void pcie_set_ecrc_checking(struct pci_dev *dev);
1507 void pcie_ecrc_get_policy(char *str);
1508 #else
pcie_set_ecrc_checking(struct pci_dev * dev)1509 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
pcie_ecrc_get_policy(char * str)1510 static inline void pcie_ecrc_get_policy(char *str) { }
1511 #endif
1512
1513 bool pci_ats_disabled(void);
1514
1515 #ifdef CONFIG_PCI_ATS
1516 /* Address Translation Service */
1517 void pci_ats_init(struct pci_dev *dev);
1518 int pci_enable_ats(struct pci_dev *dev, int ps);
1519 void pci_disable_ats(struct pci_dev *dev);
1520 int pci_ats_queue_depth(struct pci_dev *dev);
1521 #else
pci_ats_init(struct pci_dev * d)1522 static inline void pci_ats_init(struct pci_dev *d) { }
pci_enable_ats(struct pci_dev * d,int ps)1523 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
pci_disable_ats(struct pci_dev * d)1524 static inline void pci_disable_ats(struct pci_dev *d) { }
pci_ats_queue_depth(struct pci_dev * d)1525 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1526 #endif
1527
1528 #ifdef CONFIG_PCIE_PTM
1529 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1530 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1531 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1532 { return -EINVAL; }
1533 #endif
1534
1535 void pci_cfg_access_lock(struct pci_dev *dev);
1536 bool pci_cfg_access_trylock(struct pci_dev *dev);
1537 void pci_cfg_access_unlock(struct pci_dev *dev);
1538
1539 /*
1540 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1541 * a PCI domain is defined to be a set of PCI buses which share
1542 * configuration space.
1543 */
1544 #ifdef CONFIG_PCI_DOMAINS
1545 extern int pci_domains_supported;
1546 #else
1547 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1548 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1549 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1550 #endif /* CONFIG_PCI_DOMAINS */
1551
1552 /*
1553 * Generic implementation for PCI domain support. If your
1554 * architecture does not need custom management of PCI
1555 * domains then this implementation will be used
1556 */
1557 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1558 static inline int pci_domain_nr(struct pci_bus *bus)
1559 {
1560 return bus->domain_nr;
1561 }
1562 #ifdef CONFIG_ACPI
1563 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1564 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1565 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1566 { return 0; }
1567 #endif
1568 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1569 #endif
1570
1571 /* Some architectures require additional setup to direct VGA traffic */
1572 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1573 unsigned int command_bits, u32 flags);
1574 void pci_register_set_vga_state(arch_set_vga_state_t func);
1575
1576 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1577 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1578 {
1579 return pci_request_selected_regions(pdev,
1580 pci_select_bars(pdev, IORESOURCE_IO), name);
1581 }
1582
1583 static inline void
pci_release_io_regions(struct pci_dev * pdev)1584 pci_release_io_regions(struct pci_dev *pdev)
1585 {
1586 return pci_release_selected_regions(pdev,
1587 pci_select_bars(pdev, IORESOURCE_IO));
1588 }
1589
1590 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1591 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1592 {
1593 return pci_request_selected_regions(pdev,
1594 pci_select_bars(pdev, IORESOURCE_MEM), name);
1595 }
1596
1597 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1598 pci_release_mem_regions(struct pci_dev *pdev)
1599 {
1600 return pci_release_selected_regions(pdev,
1601 pci_select_bars(pdev, IORESOURCE_MEM));
1602 }
1603
1604 #else /* CONFIG_PCI is not enabled */
1605
pci_set_flags(int flags)1606 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1607 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1608 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1609 static inline int pci_has_flag(int flag) { return 0; }
1610
1611 /*
1612 * If the system does not have PCI, clearly these return errors. Define
1613 * these as simple inline functions to avoid hair in drivers.
1614 */
1615 #define _PCI_NOP(o, s, t) \
1616 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1617 int where, t val) \
1618 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1619
1620 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1621 _PCI_NOP(o, word, u16 x) \
1622 _PCI_NOP(o, dword, u32 x)
1623 _PCI_NOP_ALL(read, *)
1624 _PCI_NOP_ALL(write,)
1625
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1626 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1627 unsigned int device,
1628 struct pci_dev *from)
1629 { return NULL; }
1630
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1631 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1632 unsigned int device,
1633 unsigned int ss_vendor,
1634 unsigned int ss_device,
1635 struct pci_dev *from)
1636 { return NULL; }
1637
pci_get_class(unsigned int class,struct pci_dev * from)1638 static inline struct pci_dev *pci_get_class(unsigned int class,
1639 struct pci_dev *from)
1640 { return NULL; }
1641
1642 #define pci_dev_present(ids) (0)
1643 #define no_pci_devices() (1)
1644 #define pci_dev_put(dev) do { } while (0)
1645
pci_set_master(struct pci_dev * dev)1646 static inline void pci_set_master(struct pci_dev *dev) { }
pci_clear_master(struct pci_dev * dev)1647 static inline void pci_clear_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1648 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1649 static inline void pci_disable_device(struct pci_dev *dev) { }
pci_assign_resource(struct pci_dev * dev,int i)1650 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1651 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1652 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1653 struct module *owner,
1654 const char *mod_name)
1655 { return 0; }
pci_register_driver(struct pci_driver * drv)1656 static inline int pci_register_driver(struct pci_driver *drv)
1657 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1658 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1659 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1660 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1661 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1662 int cap)
1663 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1664 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1665 { return 0; }
1666
1667 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1668 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1669 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1670 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1671 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1672 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1673 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1674 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1675 pm_message_t state)
1676 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1677 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1678 int enable)
1679 { return 0; }
1680
pci_find_resource(struct pci_dev * dev,struct resource * res)1681 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1682 struct resource *res)
1683 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1684 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1685 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1686 static inline void pci_release_regions(struct pci_dev *dev) { }
1687
pci_address_to_pio(phys_addr_t addr)1688 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1689
pci_block_cfg_access(struct pci_dev * dev)1690 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
pci_block_cfg_access_in_atomic(struct pci_dev * dev)1691 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1692 { return 0; }
pci_unblock_cfg_access(struct pci_dev * dev)1693 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1694
pci_find_next_bus(const struct pci_bus * from)1695 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1696 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1697 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1698 unsigned int devfn)
1699 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1700 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1701 unsigned int bus, unsigned int devfn)
1702 { return NULL; }
1703
pci_domain_nr(struct pci_bus * bus)1704 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1705 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1706
1707 #define dev_is_pci(d) (false)
1708 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1709 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1710 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1711 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1712 struct device_node *node,
1713 const u32 *intspec,
1714 unsigned int intsize,
1715 unsigned long *out_hwirq,
1716 unsigned int *out_type)
1717 { return -EINVAL; }
1718 #endif /* CONFIG_PCI */
1719
1720 /* Include architecture-dependent settings and functions */
1721
1722 #include <asm/pci.h>
1723
1724 /* These two functions provide almost identical functionality. Depennding
1725 * on the architecture, one will be implemented as a wrapper around the
1726 * other (in drivers/pci/mmap.c).
1727 *
1728 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1729 * is expected to be an offset within that region.
1730 *
1731 * pci_mmap_page_range() is the legacy architecture-specific interface,
1732 * which accepts a "user visible" resource address converted by
1733 * pci_resource_to_user(), as used in the legacy mmap() interface in
1734 * /proc/bus/pci/.
1735 */
1736 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1737 struct vm_area_struct *vma,
1738 enum pci_mmap_state mmap_state, int write_combine);
1739 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1740 struct vm_area_struct *vma,
1741 enum pci_mmap_state mmap_state, int write_combine);
1742
1743 #ifndef arch_can_pci_mmap_wc
1744 #define arch_can_pci_mmap_wc() 0
1745 #endif
1746
1747 #ifndef arch_can_pci_mmap_io
1748 #define arch_can_pci_mmap_io() 0
1749 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1750 #else
1751 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1752 #endif
1753
1754 #ifndef pci_root_bus_fwnode
1755 #define pci_root_bus_fwnode(bus) NULL
1756 #endif
1757
1758 /*
1759 * These helpers provide future and backwards compatibility
1760 * for accessing popular PCI BAR info
1761 */
1762 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1763 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1764 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1765 #define pci_resource_len(dev,bar) \
1766 ((pci_resource_start((dev), (bar)) == 0 && \
1767 pci_resource_end((dev), (bar)) == \
1768 pci_resource_start((dev), (bar))) ? 0 : \
1769 \
1770 (pci_resource_end((dev), (bar)) - \
1771 pci_resource_start((dev), (bar)) + 1))
1772
1773 /*
1774 * Similar to the helpers above, these manipulate per-pci_dev
1775 * driver-specific data. They are really just a wrapper around
1776 * the generic device structure functions of these calls.
1777 */
pci_get_drvdata(struct pci_dev * pdev)1778 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1779 {
1780 return dev_get_drvdata(&pdev->dev);
1781 }
1782
pci_set_drvdata(struct pci_dev * pdev,void * data)1783 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1784 {
1785 dev_set_drvdata(&pdev->dev, data);
1786 }
1787
pci_name(const struct pci_dev * pdev)1788 static inline const char *pci_name(const struct pci_dev *pdev)
1789 {
1790 return dev_name(&pdev->dev);
1791 }
1792
1793
1794 /*
1795 * Some archs don't want to expose struct resource to userland as-is
1796 * in sysfs and /proc
1797 */
1798 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1799 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1800 const struct resource *rsrc,
1801 resource_size_t *start, resource_size_t *end);
1802 #else
pci_resource_to_user(const struct pci_dev * dev,int bar,const struct resource * rsrc,resource_size_t * start,resource_size_t * end)1803 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1804 const struct resource *rsrc, resource_size_t *start,
1805 resource_size_t *end)
1806 {
1807 *start = rsrc->start;
1808 *end = rsrc->end;
1809 }
1810 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1811
1812
1813 /*
1814 * The world is not perfect and supplies us with broken PCI devices.
1815 * For at least a part of these bugs we need a work-around, so both
1816 * generic (drivers/pci/quirks.c) and per-architecture code can define
1817 * fixup hooks to be called for particular buggy devices.
1818 */
1819
1820 struct pci_fixup {
1821 u16 vendor; /* Or PCI_ANY_ID */
1822 u16 device; /* Or PCI_ANY_ID */
1823 u32 class; /* Or PCI_ANY_ID */
1824 unsigned int class_shift; /* should be 0, 8, 16 */
1825 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1826 int hook_offset;
1827 #else
1828 void (*hook)(struct pci_dev *dev);
1829 #endif
1830 };
1831
1832 enum pci_fixup_pass {
1833 pci_fixup_early, /* Before probing BARs */
1834 pci_fixup_header, /* After reading configuration header */
1835 pci_fixup_final, /* Final phase of device fixups */
1836 pci_fixup_enable, /* pci_enable_device() time */
1837 pci_fixup_resume, /* pci_device_resume() */
1838 pci_fixup_suspend, /* pci_device_suspend() */
1839 pci_fixup_resume_early, /* pci_device_resume_early() */
1840 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1841 };
1842
1843 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1844 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1845 class_shift, hook) \
1846 __ADDRESSABLE(hook) \
1847 asm(".section " #sec ", \"a\" \n" \
1848 ".balign 16 \n" \
1849 ".short " #vendor ", " #device " \n" \
1850 ".long " #class ", " #class_shift " \n" \
1851 ".long " #hook " - . \n" \
1852 ".previous \n");
1853 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1854 class_shift, hook) \
1855 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1856 class_shift, hook)
1857 #else
1858 /* Anonymous variables would be nice... */
1859 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1860 class_shift, hook) \
1861 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1862 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1863 = { vendor, device, class, class_shift, hook };
1864 #endif
1865
1866 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1867 class_shift, hook) \
1868 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1869 hook, vendor, device, class, class_shift, hook)
1870 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1871 class_shift, hook) \
1872 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1873 hook, vendor, device, class, class_shift, hook)
1874 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1875 class_shift, hook) \
1876 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1877 hook, vendor, device, class, class_shift, hook)
1878 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1879 class_shift, hook) \
1880 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1881 hook, vendor, device, class, class_shift, hook)
1882 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1883 class_shift, hook) \
1884 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1885 resume##hook, vendor, device, class, class_shift, hook)
1886 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1887 class_shift, hook) \
1888 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1889 resume_early##hook, vendor, device, class, class_shift, hook)
1890 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1891 class_shift, hook) \
1892 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1893 suspend##hook, vendor, device, class, class_shift, hook)
1894 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1895 class_shift, hook) \
1896 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1897 suspend_late##hook, vendor, device, class, class_shift, hook)
1898
1899 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1900 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1901 hook, vendor, device, PCI_ANY_ID, 0, hook)
1902 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1903 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1904 hook, vendor, device, PCI_ANY_ID, 0, hook)
1905 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1906 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1907 hook, vendor, device, PCI_ANY_ID, 0, hook)
1908 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1909 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1910 hook, vendor, device, PCI_ANY_ID, 0, hook)
1911 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1912 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1913 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1914 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1915 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1916 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1917 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1918 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1919 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1920 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1921 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1922 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1923
1924 #ifdef CONFIG_PCI_QUIRKS
1925 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1926 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)1927 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1928 struct pci_dev *dev) { }
1929 #endif
1930
1931 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1932 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1933 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1934 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1935 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1936 const char *name);
1937 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1938
1939 extern int pci_pci_problems;
1940 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1941 #define PCIPCI_TRITON 2
1942 #define PCIPCI_NATOMA 4
1943 #define PCIPCI_VIAETBF 8
1944 #define PCIPCI_VSFX 16
1945 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1946 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1947
1948 extern unsigned long pci_cardbus_io_size;
1949 extern unsigned long pci_cardbus_mem_size;
1950 extern u8 pci_dfl_cache_line_size;
1951 extern u8 pci_cache_line_size;
1952
1953 extern unsigned long pci_hotplug_io_size;
1954 extern unsigned long pci_hotplug_mem_size;
1955 extern unsigned long pci_hotplug_bus_size;
1956
1957 /* Architecture-specific versions may override these (weak) */
1958 void pcibios_disable_device(struct pci_dev *dev);
1959 void pcibios_set_master(struct pci_dev *dev);
1960 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1961 enum pcie_reset_state state);
1962 int pcibios_add_device(struct pci_dev *dev);
1963 void pcibios_release_device(struct pci_dev *dev);
1964 void pcibios_penalize_isa_irq(int irq, int active);
1965 int pcibios_alloc_irq(struct pci_dev *dev);
1966 void pcibios_free_irq(struct pci_dev *dev);
1967 resource_size_t pcibios_default_alignment(void);
1968
1969 #ifdef CONFIG_HIBERNATE_CALLBACKS
1970 extern struct dev_pm_ops pcibios_pm_ops;
1971 #endif
1972
1973 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1974 void __init pci_mmcfg_early_init(void);
1975 void __init pci_mmcfg_late_init(void);
1976 #else
pci_mmcfg_early_init(void)1977 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)1978 static inline void pci_mmcfg_late_init(void) { }
1979 #endif
1980
1981 int pci_ext_cfg_avail(void);
1982
1983 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1984 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1985
1986 #ifdef CONFIG_PCI_IOV
1987 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1988 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1989
1990 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1991 void pci_disable_sriov(struct pci_dev *dev);
1992 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1993 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1994 int pci_num_vf(struct pci_dev *dev);
1995 int pci_vfs_assigned(struct pci_dev *dev);
1996 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1997 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1998 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
1999 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2000 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2001
2002 /* Arch may override these (weak) */
2003 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2004 int pcibios_sriov_disable(struct pci_dev *pdev);
2005 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2006 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2007 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2008 {
2009 return -ENOSYS;
2010 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2011 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2012 {
2013 return -ENOSYS;
2014 }
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2015 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2016 { return -ENODEV; }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2017 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2018 {
2019 return -ENOSYS;
2020 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2021 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2022 int id) { }
pci_disable_sriov(struct pci_dev * dev)2023 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2024 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2025 static inline int pci_vfs_assigned(struct pci_dev *dev)
2026 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2027 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2028 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2029 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2030 { return 0; }
2031 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2032 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2033 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2034 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2035 #endif
2036
2037 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2038 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2039 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2040 #endif
2041
2042 /**
2043 * pci_pcie_cap - get the saved PCIe capability offset
2044 * @dev: PCI device
2045 *
2046 * PCIe capability offset is calculated at PCI device initialization
2047 * time and saved in the data structure. This function returns saved
2048 * PCIe capability offset. Using this instead of pci_find_capability()
2049 * reduces unnecessary search in the PCI configuration space. If you
2050 * need to calculate PCIe capability offset from raw device for some
2051 * reasons, please use pci_find_capability() instead.
2052 */
pci_pcie_cap(struct pci_dev * dev)2053 static inline int pci_pcie_cap(struct pci_dev *dev)
2054 {
2055 return dev->pcie_cap;
2056 }
2057
2058 /**
2059 * pci_is_pcie - check if the PCI device is PCI Express capable
2060 * @dev: PCI device
2061 *
2062 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2063 */
pci_is_pcie(struct pci_dev * dev)2064 static inline bool pci_is_pcie(struct pci_dev *dev)
2065 {
2066 return pci_pcie_cap(dev);
2067 }
2068
2069 /**
2070 * pcie_caps_reg - get the PCIe Capabilities Register
2071 * @dev: PCI device
2072 */
pcie_caps_reg(const struct pci_dev * dev)2073 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2074 {
2075 return dev->pcie_flags_reg;
2076 }
2077
2078 /**
2079 * pci_pcie_type - get the PCIe device/port type
2080 * @dev: PCI device
2081 */
pci_pcie_type(const struct pci_dev * dev)2082 static inline int pci_pcie_type(const struct pci_dev *dev)
2083 {
2084 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2085 }
2086
pcie_find_root_port(struct pci_dev * dev)2087 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2088 {
2089 while (1) {
2090 if (!pci_is_pcie(dev))
2091 break;
2092 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2093 return dev;
2094 if (!dev->bus->self)
2095 break;
2096 dev = dev->bus->self;
2097 }
2098 return NULL;
2099 }
2100
2101 void pci_request_acs(void);
2102 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2103 bool pci_acs_path_enabled(struct pci_dev *start,
2104 struct pci_dev *end, u16 acs_flags);
2105 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2106
2107 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2108 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2109
2110 /* Large Resource Data Type Tag Item Names */
2111 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2112 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2113 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2114
2115 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2116 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2117 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2118
2119 /* Small Resource Data Type Tag Item Names */
2120 #define PCI_VPD_STIN_END 0x0f /* End */
2121
2122 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2123
2124 #define PCI_VPD_SRDT_TIN_MASK 0x78
2125 #define PCI_VPD_SRDT_LEN_MASK 0x07
2126 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2127
2128 #define PCI_VPD_LRDT_TAG_SIZE 3
2129 #define PCI_VPD_SRDT_TAG_SIZE 1
2130
2131 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2132
2133 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2134 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2135 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2136 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2137
2138 /**
2139 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2140 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2141 *
2142 * Returns the extracted Large Resource Data Type length.
2143 */
pci_vpd_lrdt_size(const u8 * lrdt)2144 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2145 {
2146 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2147 }
2148
2149 /**
2150 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2151 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2152 *
2153 * Returns the extracted Large Resource Data Type Tag item.
2154 */
pci_vpd_lrdt_tag(const u8 * lrdt)2155 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2156 {
2157 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2158 }
2159
2160 /**
2161 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2162 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2163 *
2164 * Returns the extracted Small Resource Data Type length.
2165 */
pci_vpd_srdt_size(const u8 * srdt)2166 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2167 {
2168 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2169 }
2170
2171 /**
2172 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2173 * @srdt: Pointer to the beginning of the Small Resource Data Type tag
2174 *
2175 * Returns the extracted Small Resource Data Type Tag Item.
2176 */
pci_vpd_srdt_tag(const u8 * srdt)2177 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2178 {
2179 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2180 }
2181
2182 /**
2183 * pci_vpd_info_field_size - Extracts the information field length
2184 * @lrdt: Pointer to the beginning of an information field header
2185 *
2186 * Returns the extracted information field length.
2187 */
pci_vpd_info_field_size(const u8 * info_field)2188 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2189 {
2190 return info_field[2];
2191 }
2192
2193 /**
2194 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2195 * @buf: Pointer to buffered vpd data
2196 * @off: The offset into the buffer at which to begin the search
2197 * @len: The length of the vpd buffer
2198 * @rdt: The Resource Data Type to search for
2199 *
2200 * Returns the index where the Resource Data Type was found or
2201 * -ENOENT otherwise.
2202 */
2203 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2204
2205 /**
2206 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2207 * @buf: Pointer to buffered vpd data
2208 * @off: The offset into the buffer at which to begin the search
2209 * @len: The length of the buffer area, relative to off, in which to search
2210 * @kw: The keyword to search for
2211 *
2212 * Returns the index where the information field keyword was found or
2213 * -ENOENT otherwise.
2214 */
2215 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2216 unsigned int len, const char *kw);
2217
2218 /* PCI <-> OF binding helpers */
2219 #ifdef CONFIG_OF
2220 struct device_node;
2221 struct irq_domain;
2222 void pci_set_of_node(struct pci_dev *dev);
2223 void pci_release_of_node(struct pci_dev *dev);
2224 void pci_set_bus_of_node(struct pci_bus *bus);
2225 void pci_release_bus_of_node(struct pci_bus *bus);
2226 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2227 int pci_parse_request_of_pci_ranges(struct device *dev,
2228 struct list_head *resources,
2229 struct resource **bus_range);
2230
2231 /* Arch may override this (weak) */
2232 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2233
2234 #else /* CONFIG_OF */
pci_set_of_node(struct pci_dev * dev)2235 static inline void pci_set_of_node(struct pci_dev *dev) { }
pci_release_of_node(struct pci_dev * dev)2236 static inline void pci_release_of_node(struct pci_dev *dev) { }
pci_set_bus_of_node(struct pci_bus * bus)2237 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
pci_release_bus_of_node(struct pci_bus * bus)2238 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2239 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2240 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_parse_request_of_pci_ranges(struct device * dev,struct list_head * resources,struct resource ** bus_range)2241 static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2242 struct list_head *resources,
2243 struct resource **bus_range)
2244 {
2245 return -EINVAL;
2246 }
2247 #endif /* CONFIG_OF */
2248
2249 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2250 pci_device_to_OF_node(const struct pci_dev *pdev)
2251 {
2252 return pdev ? pdev->dev.of_node : NULL;
2253 }
2254
pci_bus_to_OF_node(struct pci_bus * bus)2255 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2256 {
2257 return bus ? bus->dev.of_node : NULL;
2258 }
2259
2260 #ifdef CONFIG_ACPI
2261 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2262
2263 void
2264 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2265 #else
2266 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2267 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2268 #endif
2269
2270 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2271 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2272 {
2273 return pdev->dev.archdata.edev;
2274 }
2275 #endif
2276
2277 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2278 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2279 int pci_for_each_dma_alias(struct pci_dev *pdev,
2280 int (*fn)(struct pci_dev *pdev,
2281 u16 alias, void *data), void *data);
2282
2283 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2284 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2285 {
2286 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2287 }
pci_clear_dev_assigned(struct pci_dev * pdev)2288 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2289 {
2290 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2291 }
pci_is_dev_assigned(struct pci_dev * pdev)2292 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2293 {
2294 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2295 }
2296
2297 /**
2298 * pci_ari_enabled - query ARI forwarding status
2299 * @bus: the PCI bus
2300 *
2301 * Returns true if ARI forwarding is enabled.
2302 */
pci_ari_enabled(struct pci_bus * bus)2303 static inline bool pci_ari_enabled(struct pci_bus *bus)
2304 {
2305 return bus->self && bus->self->ari_enabled;
2306 }
2307
2308 /**
2309 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2310 * @pdev: PCI device to check
2311 *
2312 * Walk upwards from @pdev and check for each encountered bridge if it's part
2313 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2314 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2315 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2316 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2317 {
2318 struct pci_dev *parent = pdev;
2319
2320 if (pdev->is_thunderbolt)
2321 return true;
2322
2323 while ((parent = pci_upstream_bridge(parent)))
2324 if (parent->is_thunderbolt)
2325 return true;
2326
2327 return false;
2328 }
2329
2330 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2331 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2332 #endif
2333
2334 /* Provide the legacy pci_dma_* API */
2335 #include <linux/pci-dma-compat.h>
2336
2337 #define pci_printk(level, pdev, fmt, arg...) \
2338 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2339
2340 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2341 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2342 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2343 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2344 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2345 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2346 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2347 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2348
2349 #endif /* LINUX_PCI_H */
2350