1 /* 2 * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /** 21 * DOC: wlan_dfs_public_struct.h 22 * This file contains DFS data structures 23 */ 24 25 #ifndef __WLAN_DFS_PUBLIC_STRUCT_H_ 26 #define __WLAN_DFS_PUBLIC_STRUCT_H_ 27 #include <wlan_cmn.h> 28 /* TODO: This structure has many redundant variables, needs cleanup */ 29 /** 30 * struct radar_found_info - radar found info 31 * @pdev_id: pdev id. 32 * @detection_mode: 0 indicates RADAR detected, non-zero indicates debug mode. 33 * @freq_offset: frequency offset. 34 * @chan_width: channel width. 35 * @detector_id: detector id for full-offload. 36 * @segment_id: segment id (same as detector_id) for partial-offload. 37 * @timestamp: timestamp (Time when filter match is found in Firmware). 38 * @is_chirp: is chirp or not. 39 * @chan_freq: channel frequency (Primary channel frequency). 40 * @radar_freq: radar frequency (Is it same as '@chan_freq'?). 41 * @sidx: sidx value (same as freq_offset). 42 * @is_full_bw_nol: Is full bandwidth needed to put to NOL. 43 */ 44 struct radar_found_info { 45 uint32_t pdev_id; 46 uint32_t detection_mode; 47 int32_t freq_offset; 48 uint32_t chan_width; 49 uint32_t detector_id; 50 uint32_t segment_id; 51 uint32_t timestamp; 52 uint32_t is_chirp; 53 uint32_t chan_freq; 54 uint32_t radar_freq; 55 int32_t sidx; 56 uint8_t is_full_bw_nol; 57 }; 58 59 /** 60 * struct dfs_acs_info - acs info, ch range 61 * @acs_mode: to enable/disable acs 1/0. 62 * @chan_freq_list: channel frequency list 63 * @num_of_channel: number of channel in ACS channel list 64 */ 65 struct dfs_acs_info { 66 uint8_t acs_mode; 67 uint32_t *chan_freq_list; 68 uint8_t num_of_channel; 69 }; 70 71 /** 72 * struct radar_event_info - radar event info. 73 * @pulse_is_chirp: flag to indicate if this pulse is chirp. 74 * @pulse_center_freq: the center frequency of the radar pulse detected, KHz. 75 * @pulse_duration: the duaration of the pulse in us. 76 * @rssi: RSSI recorded in the ppdu. 77 * @pulse_detect_ts: timestamp indicates the time when DFS pulse is detected. 78 * @upload_fullts_low: low 32 tsf timestamp get from MAC tsf timer indicates 79 * the time that the radar event uploading to host. 80 * @upload_fullts_high: high 32 tsf timestamp get from MAC tsf timer indicates 81 * the time that the radar event uploading to host. 82 * @peak_sidx: index of peak magnitude bin (signed) 83 * @pdev_id: pdev_id for identifying the MAC. 84 * @delta_diff: Delta diff value. 85 * @delta_peak: Delta peak value. 86 * @psidx_diff: Psidx diff value. 87 * @is_psidx_diff_valid: Does fw send valid psidx diff. 88 */ 89 struct radar_event_info { 90 uint8_t pulse_is_chirp; 91 uint32_t pulse_center_freq; 92 uint32_t pulse_duration; 93 uint8_t rssi; 94 uint32_t pulse_detect_ts; 95 uint32_t upload_fullts_low; 96 uint32_t upload_fullts_high; 97 int32_t peak_sidx; 98 uint8_t pdev_id; 99 uint8_t delta_diff; 100 int8_t delta_peak; 101 int8_t psidx_diff; 102 int8_t is_psidx_diff_valid; 103 }; 104 105 /** 106 * struct dfs_user_config - user configuration required for for DFS. 107 * @dfs_is_phyerr_filter_offload: flag to indicate DFS phyerr filtering offload. 108 */ 109 struct dfs_user_config { 110 bool dfs_is_phyerr_filter_offload; 111 }; 112 113 /** 114 * struct dfs_radar_found_params - radar found parameters. 115 * @pri_min: Minimum PRI of detected radar pulse. 116 * @pri_max: Max PRI of detected radar pulse. 117 * @duration_min: Min duration of detected pulse in us. 118 * @duration_max: Max duration of detected pulse in us. 119 * @sidx_min: Min softare index of detected radar pulse. 120 * @sidx_max: Max software index of detected radar pulse. 121 */ 122 struct dfs_radar_found_params { 123 u_int32_t pri_min; 124 u_int32_t pri_max; 125 u_int32_t duration_min; 126 u_int32_t duration_max; 127 u_int32_t sidx_min; 128 u_int32_t sidx_max; 129 }; 130 131 /** 132 * enum adfs_ocac_mode - Various Off-Channel CAC modes. 133 * @QUICK_OCAC_MODE: Used for OCAC where the CAC timeout value is finite. 134 * This is also known as PreCAC. 135 * @EXTENSIVE_OCAC_MODE: Extensive OCAC. 136 * @QUICK_RCAC_MODE: Used for RollingCAC where the timeout value is assumed to 137 * be infinite by the Firmware code, that is, the FW has to 138 * be on the agile channel until host stop/aborts the agile 139 * CAC. 140 */ 141 enum adfs_ocac_mode { 142 QUICK_OCAC_MODE = 0, 143 EXTENSIVE_OCAC_MODE, 144 QUICK_RCAC_MODE, 145 }; 146 147 /** 148 * struct dfs_agile_cac_params - Agile DFS-CAC parameters. 149 * @precac_chan: Agile preCAC channel. 150 * @precac_center_freq_1: Agile preCAC channel frequency in MHz for 20/40/80/ 151 * 160 and left center frequency(5690MHz) for restricted 152 * 80p80. 153 * @precac_center_freq_2: Second segment Agile frequency if applicable. 0 for 154 * 20/40/80/160 and right center frequency(5775MHz) for 155 * restricted 80p80. 156 * @precac_chwidth: Agile preCAC channel width. 157 * @min_precac_timeout: Minimum agile preCAC timeout. 158 * @max_precac_timeout: Maximum agile preCAC timeout. 159 * @ocac_mode: Off-Channel CAC mode. 160 */ 161 struct dfs_agile_cac_params { 162 uint8_t precac_chan; 163 uint16_t precac_center_freq_1; 164 uint16_t precac_center_freq_2; 165 enum phy_ch_width precac_chwidth; 166 uint32_t min_precac_timeout; 167 uint32_t max_precac_timeout; 168 enum adfs_ocac_mode ocac_mode; 169 }; 170 171 /* The first DFS channel number is 52 and the last DFS channel number is 161(in 172 * case of ETSI EN302502). So, the array size is taken as (161 - 52) / 4 ~= 30. 173 */ 174 #define NUM_DFS_CHANS 30 175 176 /** 177 * enum channel_dfs_state - DFS channel states. 178 * @CH_DFS_S_INVALID: The DFS state for invalid channel numbers that are not 179 * part of the radio's channel list. 180 * @CH_DFS_S_CAC_REQ: Indicates that the CAC/Off-channel CAC has to performed 181 * before Tx on the DFS channel. 182 * @CH_DFS_S_CAC_STARTED: Indicates that the CAC has been started for the DFS 183 * channel. 184 * @CH_DFS_S_CAC_COMPLETED: Indicates that the CAC has been completed for the 185 * DFS channel. 186 * @CH_DFS_S_NOL: Indicates that the DFS channel is in NOL. 187 * @CH_DFS_S_PRECAC_STARTED: Indicates that the PreCAC has been started for the 188 * DFS channel. 189 * @CH_DFS_S_PRECAC_COMPLETED: Indicates that the PreCAC has been completed for 190 * the DFS channel. 191 * @CH_DFS_S_NON_DFS: Indicates that it is a non-DFS channel. 192 */ 193 enum channel_dfs_state { 194 CH_DFS_S_INVALID, 195 CH_DFS_S_CAC_REQ, 196 CH_DFS_S_CAC_STARTED, 197 CH_DFS_S_CAC_COMPLETED, 198 CH_DFS_S_NOL, 199 CH_DFS_S_PRECAC_STARTED, 200 CH_DFS_S_PRECAC_COMPLETED, 201 CH_DFS_S_NON_DFS, 202 }; 203 204 /** 205 * enum ocac_status_type - Enum for OCAC status for Agile DFS. 206 * @OCAC_SUCCESS: OCAC completed successfully. 207 * @OCAC_RESET: OCAC status was reset. 208 * @OCAC_CANCEL: OCAC canceled. 209 */ 210 enum ocac_status_type { 211 OCAC_SUCCESS = 0, 212 OCAC_RESET, 213 OCAC_CANCEL, 214 }; 215 #endif 216