1 /*
2  * Copyright (C) 2002 ARM Limited, All Rights Reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/irqchip/arm-gic.h>
21 
22 #include "irq-gic-common.h"
23 
24 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
25 
26 static const struct gic_kvm_info *gic_kvm_info;
27 
gic_get_kvm_info(void)28 const struct gic_kvm_info *gic_get_kvm_info(void)
29 {
30 	return gic_kvm_info;
31 }
32 
gic_set_kvm_info(const struct gic_kvm_info * info)33 void gic_set_kvm_info(const struct gic_kvm_info *info)
34 {
35 	BUG_ON(gic_kvm_info != NULL);
36 	gic_kvm_info = info;
37 }
38 
gic_enable_quirks(u32 iidr,const struct gic_quirk * quirks,void * data)39 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
40 		void *data)
41 {
42 	for (; quirks->desc; quirks++) {
43 		if (quirks->iidr != (quirks->mask & iidr))
44 			continue;
45 		if (quirks->init(data))
46 			pr_info("GIC: enabling workaround for %s\n",
47 				quirks->desc);
48 	}
49 }
50 
gic_configure_irq(unsigned int irq,unsigned int type,void __iomem * base,void (* sync_access)(void))51 int gic_configure_irq(unsigned int irq, unsigned int type,
52 		       void __iomem *base, void (*sync_access)(void))
53 {
54 	u32 confmask = 0x2 << ((irq % 16) * 2);
55 	u32 confoff = (irq / 16) * 4;
56 	u32 val, oldval;
57 	int ret = 0;
58 	unsigned long flags;
59 
60 	/*
61 	 * Read current configuration register, and insert the config
62 	 * for "irq", depending on "type".
63 	 */
64 	raw_spin_lock_irqsave(&irq_controller_lock, flags);
65 	val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
66 	if (type & IRQ_TYPE_LEVEL_MASK)
67 		val &= ~confmask;
68 	else if (type & IRQ_TYPE_EDGE_BOTH)
69 		val |= confmask;
70 
71 	/* If the current configuration is the same, then we are done */
72 	if (val == oldval) {
73 		raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
74 		return 0;
75 	}
76 
77 	/*
78 	 * Write back the new configuration, and possibly re-enable
79 	 * the interrupt. If we fail to write a new configuration for
80 	 * an SPI then WARN and return an error. If we fail to write the
81 	 * configuration for a PPI this is most likely because the GIC
82 	 * does not allow us to set the configuration or we are in a
83 	 * non-secure mode, and hence it may not be catastrophic.
84 	 */
85 	writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
86 	if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val) {
87 		if (WARN_ON(irq >= 32))
88 			ret = -EINVAL;
89 		else
90 			pr_warn("GIC: PPI%d is secure or misconfigured\n",
91 				irq - 16);
92 	}
93 	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
94 
95 	if (sync_access)
96 		sync_access();
97 
98 	return ret;
99 }
100 
gic_dist_config(void __iomem * base,int gic_irqs,void (* sync_access)(void))101 void gic_dist_config(void __iomem *base, int gic_irqs,
102 		     void (*sync_access)(void))
103 {
104 	unsigned int i;
105 
106 	/*
107 	 * Set all global interrupts to be level triggered, active low.
108 	 */
109 	for (i = 32; i < gic_irqs; i += 16)
110 		writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
111 					base + GIC_DIST_CONFIG + i / 4);
112 
113 	/*
114 	 * Set priority on all global interrupts.
115 	 */
116 	for (i = 32; i < gic_irqs; i += 4)
117 		writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
118 
119 	/*
120 	 * Deactivate and disable all SPIs. Leave the PPI and SGIs
121 	 * alone as they are in the redistributor registers on GICv3.
122 	 */
123 	for (i = 32; i < gic_irqs; i += 32) {
124 		writel_relaxed(GICD_INT_EN_CLR_X32,
125 			       base + GIC_DIST_ACTIVE_CLEAR + i / 8);
126 		writel_relaxed(GICD_INT_EN_CLR_X32,
127 			       base + GIC_DIST_ENABLE_CLEAR + i / 8);
128 	}
129 
130 	if (sync_access)
131 		sync_access();
132 }
133 
gic_cpu_config(void __iomem * base,void (* sync_access)(void))134 void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
135 {
136 	int i;
137 
138 	/*
139 	 * Deal with the banked PPI and SGI interrupts - disable all
140 	 * PPI interrupts, ensure all SGI interrupts are enabled.
141 	 * Make sure everything is deactivated.
142 	 */
143 	writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);
144 	writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
145 	writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
146 
147 	/*
148 	 * Set priority on PPI and SGI interrupts
149 	 */
150 	for (i = 0; i < 32; i += 4)
151 		writel_relaxed(GICD_INT_DEF_PRI_X4,
152 					base + GIC_DIST_PRI + i * 4 / 4);
153 
154 	if (sync_access)
155 		sync_access();
156 }
157