1 /*
2 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include "hal_li_hw_headers.h"
19 #include "hal_internal.h"
20 #include "hal_api.h"
21 #include "target_type.h"
22 #include "wcss_version.h"
23 #include "qdf_module.h"
24 #include "hal_qcn6122_rx.h"
25 #include "hal_api_mon.h"
26 #include "hal_flow.h"
27 #include "rx_flow_search_entry.h"
28 #include "hal_rx_flow_info.h"
29
30 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
31 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
32 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
33 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK
34 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
35 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB
36 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \
37 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET
38 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \
39 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK
40 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \
41 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB
42 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
43 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET
44 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
45 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
46 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
47 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
48 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
49 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
50 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
51 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
52 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
53 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
54 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
55 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
56 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
57 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
58 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
59 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
60 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
61 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
62 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
63 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
64 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
65 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
67 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
70 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
71 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
72 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
73 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
74 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
75 STATUS_HEADER_REO_STATUS_NUMBER
76 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
77 STATUS_HEADER_TIMESTAMP
78 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
79 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
80 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
81 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
82 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
83 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
84 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
85 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
86 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
87 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
88 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
89 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
90 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
91 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
92 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
93 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
94 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
95 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
96 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
97 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
98 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
99 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
100 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
101 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
102 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
103 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
104 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
105 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
106 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
107 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
108 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
109 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
110 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
111 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
112 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
113 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
114
115 #define CE_WINDOW_ADDRESS_6122 \
116 ((SOC_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
117
118 #define UMAC_WINDOW_ADDRESS_6122 \
119 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
120
121 #define WINDOW_CONFIGURATION_VALUE_6122 \
122 ((CE_WINDOW_ADDRESS_6122 << 6) |\
123 (UMAC_WINDOW_ADDRESS_6122 << 12) | \
124 WINDOW_ENABLE_BIT)
125
126 #include "hal_qcn6122_tx.h"
127 #include <hal_generic_api.h>
128 #include "hal_li_rx.h"
129 #include "hal_li_api.h"
130 #include "hal_li_generic_api.h"
131
132 /**
133 * hal_rx_sw_mon_desc_info_get_6122() - API to read the sw monitor ring
134 * descriptor
135 * @rxdma_dst_ring_desc: sw monitor ring descriptor
136 * @desc_info_buf: Descriptor info buffer to which sw monitor ring descriptor is
137 * populated to
138 *
139 * Return: void
140 */
141 static void
hal_rx_sw_mon_desc_info_get_6122(hal_ring_desc_t rxdma_dst_ring_desc,hal_rx_mon_desc_info_t desc_info_buf)142 hal_rx_sw_mon_desc_info_get_6122(hal_ring_desc_t rxdma_dst_ring_desc,
143 hal_rx_mon_desc_info_t desc_info_buf)
144 {
145 struct sw_monitor_ring *sw_mon_ring =
146 (struct sw_monitor_ring *)rxdma_dst_ring_desc;
147 struct buffer_addr_info *buf_addr_info;
148 uint32_t *mpdu_info;
149 uint32_t loop_cnt;
150 struct hal_rx_mon_desc_info *desc_info;
151
152 desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf;
153 mpdu_info = (uint32_t *)&sw_mon_ring->
154 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
155
156 loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT);
157 desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info);
158
159 /* Get msdu link descriptor buf_addr_info */
160 buf_addr_info = &sw_mon_ring->
161 reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
162 desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info)
163 | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(
164 buf_addr_info)) << 32);
165 desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
166 buf_addr_info = &sw_mon_ring->status_buff_addr_info;
167 desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info)
168 | ((uint64_t)
169 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32);
170 desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
171 desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring,
172 SW_MONITOR_RING_6,
173 END_OF_PPDU);
174 desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring,
175 SW_MONITOR_RING_6,
176 STATUS_BUF_COUNT);
177 desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring,
178 SW_MONITOR_RING_6,
179 RXDMA_PUSH_REASON);
180 desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring,
181 SW_MONITOR_RING_7,
182 PHY_PPDU_ID);
183 }
184
185 /**
186 * hal_rx_msdu_start_nss_get_6122() - API to get the NSS Interval from
187 * rx_msdu_start
188 * @buf: pointer to the start of RX PKT TLV header
189 *
190 * Return: uint32_t(nss)
191 */
hal_rx_msdu_start_nss_get_6122(uint8_t * buf)192 static uint32_t hal_rx_msdu_start_nss_get_6122(uint8_t *buf)
193 {
194 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
195 struct rx_msdu_start *msdu_start =
196 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
197 uint8_t mimo_ss_bitmap;
198
199 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
200
201 return qdf_get_hweight8(mimo_ss_bitmap);
202 }
203
204 /**
205 * hal_rx_msdu_start_get_len_6122() - API to get the MSDU length from
206 * rx_msdu_start TLV
207 * @buf: pointer to the start of RX PKT TLV headers
208 *
209 * Return: (uint32_t)msdu length
210 */
hal_rx_msdu_start_get_len_6122(uint8_t * buf)211 static uint32_t hal_rx_msdu_start_get_len_6122(uint8_t *buf)
212 {
213 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
214 struct rx_msdu_start *msdu_start =
215 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
216 uint32_t msdu_len;
217
218 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
219
220 return msdu_len;
221 }
222
223 /**
224 * hal_rx_mon_hw_desc_get_mpdu_status_6122() - Retrieve MPDU status
225 * @hw_desc_addr: Start address of Rx HW TLVs
226 * @rs: Status for monitor mode
227 *
228 * Return: void
229 */
hal_rx_mon_hw_desc_get_mpdu_status_6122(void * hw_desc_addr,struct mon_rx_status * rs)230 static void hal_rx_mon_hw_desc_get_mpdu_status_6122(void *hw_desc_addr,
231 struct mon_rx_status *rs)
232 {
233 struct rx_msdu_start *rx_msdu_start;
234 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
235 uint32_t reg_value;
236 const uint32_t sgi_hw_to_cdp[] = {
237 CDP_SGI_0_8_US,
238 CDP_SGI_0_4_US,
239 CDP_SGI_1_6_US,
240 CDP_SGI_3_2_US,
241 };
242
243 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
244
245 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
246
247 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
248 RX_MSDU_START_5, USER_RSSI);
249 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
250
251 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
252 rs->sgi = sgi_hw_to_cdp[reg_value];
253 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
254 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
255 /* TODO: rs->beamformed should be set for SU beamforming also */
256 }
257
258 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
259 /**
260 * hal_get_link_desc_size_6122() - API to get the link desc size
261 *
262 * Return: uint32_t
263 */
hal_get_link_desc_size_6122(void)264 static uint32_t hal_get_link_desc_size_6122(void)
265 {
266 return LINK_DESC_SIZE;
267 }
268
269 /**
270 * hal_rx_get_tlv_6122() - API to get the tlv
271 * @rx_tlv: TLV data extracted from the rx packet
272 *
273 * Return: uint8_t
274 */
hal_rx_get_tlv_6122(void * rx_tlv)275 static uint8_t hal_rx_get_tlv_6122(void *rx_tlv)
276 {
277 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
278 }
279
280 /**
281 * hal_rx_mpdu_start_tlv_tag_valid_6122() - API to check if RX_MPDU_START
282 * tlv tag is valid
283 * @rx_tlv_hdr: start address of rx_pkt_tlvs
284 *
285 * Return: true if RX_MPDU_START is valid, else false.
286 */
hal_rx_mpdu_start_tlv_tag_valid_6122(void * rx_tlv_hdr)287 uint8_t hal_rx_mpdu_start_tlv_tag_valid_6122(void *rx_tlv_hdr)
288 {
289 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
290 uint32_t tlv_tag;
291
292 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
293
294 return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
295 }
296
297 /**
298 * hal_rx_wbm_err_msdu_continuation_get_6122() - API to check if WBM msdu
299 * continuation bit is set
300 * @wbm_desc: wbm release ring descriptor
301 *
302 * Return: true if msdu continuation bit is set.
303 */
hal_rx_wbm_err_msdu_continuation_get_6122(void * wbm_desc)304 uint8_t hal_rx_wbm_err_msdu_continuation_get_6122(void *wbm_desc)
305 {
306 uint32_t comp_desc =
307 *(uint32_t *)(((uint8_t *)wbm_desc) +
308 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET);
309
310 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >>
311 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB;
312 }
313
314 /**
315 * hal_rx_proc_phyrx_other_receive_info_tlv_6122() - API to get tlv info
316 * @rx_tlv_hdr: RX TLV header
317 * @ppdu_info_hdl: handle to PPDU info to update
318 *
319 * Return: None
320 */
321 static inline
hal_rx_proc_phyrx_other_receive_info_tlv_6122(void * rx_tlv_hdr,void * ppdu_info_hdl)322 void hal_rx_proc_phyrx_other_receive_info_tlv_6122(void *rx_tlv_hdr,
323 void *ppdu_info_hdl)
324 {
325 }
326
327 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
328 static inline
hal_rx_get_bb_info_6122(void * rx_tlv,void * ppdu_info_hdl)329 void hal_rx_get_bb_info_6122(void *rx_tlv,
330 void *ppdu_info_hdl)
331 {
332 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
333
334 ppdu_info->cfr_info.bb_captured_channel =
335 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL);
336
337 ppdu_info->cfr_info.bb_captured_timeout =
338 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT);
339
340 ppdu_info->cfr_info.bb_captured_reason =
341 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON);
342 }
343
344 static inline
hal_rx_get_rtt_info_6122(void * rx_tlv,void * ppdu_info_hdl)345 void hal_rx_get_rtt_info_6122(void *rx_tlv,
346 void *ppdu_info_hdl)
347 {
348 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
349
350 ppdu_info->cfr_info.rx_location_info_valid =
351 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS,
352 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID);
353
354 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
355 HAL_RX_GET(rx_tlv,
356 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
357 RTT_CHE_BUFFER_POINTER_LOW32);
358
359 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
360 HAL_RX_GET(rx_tlv,
361 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
362 RTT_CHE_BUFFER_POINTER_HIGH8);
363
364 ppdu_info->cfr_info.chan_capture_status =
365 HAL_RX_GET(rx_tlv,
366 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
367 RESERVED_8);
368
369 ppdu_info->cfr_info.rx_start_ts =
370 HAL_RX_GET(rx_tlv,
371 PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
372 RX_START_TS);
373
374 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
375 HAL_RX_GET(rx_tlv,
376 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
377 RTT_CFO_MEASUREMENT);
378
379 ppdu_info->cfr_info.agc_gain_info0 =
380 HAL_RX_GET(rx_tlv,
381 PHYRX_PKT_END_1_RX_PKT_END_DETAILS,
382 PHY_TIMESTAMP_1_LOWER_32);
383
384 ppdu_info->cfr_info.agc_gain_info1 =
385 HAL_RX_GET(rx_tlv,
386 PHYRX_PKT_END_2_RX_PKT_END_DETAILS,
387 PHY_TIMESTAMP_1_UPPER_32);
388
389 ppdu_info->cfr_info.agc_gain_info2 =
390 HAL_RX_GET(rx_tlv,
391 PHYRX_PKT_END_3_RX_PKT_END_DETAILS,
392 PHY_TIMESTAMP_2_LOWER_32);
393
394 ppdu_info->cfr_info.agc_gain_info3 =
395 HAL_RX_GET(rx_tlv,
396 PHYRX_PKT_END_4_RX_PKT_END_DETAILS,
397 PHY_TIMESTAMP_2_UPPER_32);
398
399 ppdu_info->cfr_info.mcs_rate =
400 HAL_RX_GET(rx_tlv,
401 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
402 RTT_MCS_RATE);
403
404 ppdu_info->cfr_info.gi_type =
405 HAL_RX_GET(rx_tlv,
406 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
407 RTT_GI_TYPE);
408 }
409 #endif
410
411 /**
412 * hal_rx_dump_msdu_start_tlv_6122() - dump RX msdu_start TLV in structured
413 * human readable format.
414 * @pkttlvs: pointer to the pkttlvs.
415 * @dbg_level: log level.
416 *
417 * Return: void
418 */
hal_rx_dump_msdu_start_tlv_6122(void * pkttlvs,uint8_t dbg_level)419 static void hal_rx_dump_msdu_start_tlv_6122(void *pkttlvs,
420 uint8_t dbg_level)
421 {
422 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
423 struct rx_msdu_start *msdu_start =
424 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
425
426 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
427 "rx_msdu_start tlv - "
428 "rxpcu_mpdu_filter_in_category: %d "
429 "sw_frame_group_id: %d "
430 "phy_ppdu_id: %d "
431 "msdu_length: %d "
432 "ipsec_esp: %d "
433 "l3_offset: %d "
434 "ipsec_ah: %d "
435 "l4_offset: %d "
436 "msdu_number: %d "
437 "decap_format: %d "
438 "ipv4_proto: %d "
439 "ipv6_proto: %d "
440 "tcp_proto: %d "
441 "udp_proto: %d "
442 "ip_frag: %d "
443 "tcp_only_ack: %d "
444 "da_is_bcast_mcast: %d "
445 "ip4_protocol_ip6_next_header: %d "
446 "toeplitz_hash_2_or_4: %d "
447 "flow_id_toeplitz: %d "
448 "user_rssi: %d "
449 "pkt_type: %d "
450 "stbc: %d "
451 "sgi: %d "
452 "rate_mcs: %d "
453 "receive_bandwidth: %d "
454 "reception_type: %d "
455 "ppdu_start_timestamp: %d "
456 "sw_phy_meta_data: %d ",
457 msdu_start->rxpcu_mpdu_filter_in_category,
458 msdu_start->sw_frame_group_id,
459 msdu_start->phy_ppdu_id,
460 msdu_start->msdu_length,
461 msdu_start->ipsec_esp,
462 msdu_start->l3_offset,
463 msdu_start->ipsec_ah,
464 msdu_start->l4_offset,
465 msdu_start->msdu_number,
466 msdu_start->decap_format,
467 msdu_start->ipv4_proto,
468 msdu_start->ipv6_proto,
469 msdu_start->tcp_proto,
470 msdu_start->udp_proto,
471 msdu_start->ip_frag,
472 msdu_start->tcp_only_ack,
473 msdu_start->da_is_bcast_mcast,
474 msdu_start->ip4_protocol_ip6_next_header,
475 msdu_start->toeplitz_hash_2_or_4,
476 msdu_start->flow_id_toeplitz,
477 msdu_start->user_rssi,
478 msdu_start->pkt_type,
479 msdu_start->stbc,
480 msdu_start->sgi,
481 msdu_start->rate_mcs,
482 msdu_start->receive_bandwidth,
483 msdu_start->reception_type,
484 msdu_start->ppdu_start_timestamp,
485 msdu_start->sw_phy_meta_data);
486 }
487
488 /**
489 * hal_rx_dump_msdu_end_tlv_6122() - dump RX msdu_end TLV in structured
490 * human readable format.
491 * @pkttlvs: pointer to the pkttlvs.
492 * @dbg_level: log level.
493 *
494 * Return: void
495 */
hal_rx_dump_msdu_end_tlv_6122(void * pkttlvs,uint8_t dbg_level)496 static void hal_rx_dump_msdu_end_tlv_6122(void *pkttlvs,
497 uint8_t dbg_level)
498 {
499 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
500 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
501
502 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
503 "rx_msdu_end tlv - "
504 "rxpcu_mpdu_filter_in_category: %d "
505 "sw_frame_group_id: %d "
506 "phy_ppdu_id: %d "
507 "ip_hdr_chksum: %d "
508 "reported_mpdu_length: %d "
509 "key_id_octet: %d "
510 "cce_super_rule: %d "
511 "cce_classify_not_done_truncat: %d "
512 "cce_classify_not_done_cce_dis: %d "
513 "rule_indication_31_0: %d "
514 "rule_indication_63_32: %d "
515 "da_offset: %d "
516 "sa_offset: %d "
517 "da_offset_valid: %d "
518 "sa_offset_valid: %d "
519 "ipv6_options_crc: %d "
520 "tcp_seq_number: %d "
521 "tcp_ack_number: %d "
522 "tcp_flag: %d "
523 "lro_eligible: %d "
524 "window_size: %d "
525 "tcp_udp_chksum: %d "
526 "sa_idx_timeout: %d "
527 "da_idx_timeout: %d "
528 "msdu_limit_error: %d "
529 "flow_idx_timeout: %d "
530 "flow_idx_invalid: %d "
531 "wifi_parser_error: %d "
532 "amsdu_parser_error: %d "
533 "sa_is_valid: %d "
534 "da_is_valid: %d "
535 "da_is_mcbc: %d "
536 "l3_header_padding: %d "
537 "first_msdu: %d "
538 "last_msdu: %d "
539 "sa_idx: %d "
540 "msdu_drop: %d "
541 "reo_destination_indication: %d "
542 "flow_idx: %d "
543 "fse_metadata: %d "
544 "cce_metadata: %d "
545 "sa_sw_peer_id: %d ",
546 msdu_end->rxpcu_mpdu_filter_in_category,
547 msdu_end->sw_frame_group_id,
548 msdu_end->phy_ppdu_id,
549 msdu_end->ip_hdr_chksum,
550 msdu_end->reported_mpdu_length,
551 msdu_end->key_id_octet,
552 msdu_end->cce_super_rule,
553 msdu_end->cce_classify_not_done_truncate,
554 msdu_end->cce_classify_not_done_cce_dis,
555 msdu_end->rule_indication_31_0,
556 msdu_end->rule_indication_63_32,
557 msdu_end->da_offset,
558 msdu_end->sa_offset,
559 msdu_end->da_offset_valid,
560 msdu_end->sa_offset_valid,
561 msdu_end->ipv6_options_crc,
562 msdu_end->tcp_seq_number,
563 msdu_end->tcp_ack_number,
564 msdu_end->tcp_flag,
565 msdu_end->lro_eligible,
566 msdu_end->window_size,
567 msdu_end->tcp_udp_chksum,
568 msdu_end->sa_idx_timeout,
569 msdu_end->da_idx_timeout,
570 msdu_end->msdu_limit_error,
571 msdu_end->flow_idx_timeout,
572 msdu_end->flow_idx_invalid,
573 msdu_end->wifi_parser_error,
574 msdu_end->amsdu_parser_error,
575 msdu_end->sa_is_valid,
576 msdu_end->da_is_valid,
577 msdu_end->da_is_mcbc,
578 msdu_end->l3_header_padding,
579 msdu_end->first_msdu,
580 msdu_end->last_msdu,
581 msdu_end->sa_idx,
582 msdu_end->msdu_drop,
583 msdu_end->reo_destination_indication,
584 msdu_end->flow_idx,
585 msdu_end->fse_metadata,
586 msdu_end->cce_metadata,
587 msdu_end->sa_sw_peer_id);
588 }
589
590 /**
591 * hal_rx_mpdu_start_tid_get_6122() - API to get tid from rx_msdu_start
592 * @buf: pointer to the start of RX PKT TLV header
593 *
594 * Return: uint32_t(tid value)
595 */
hal_rx_mpdu_start_tid_get_6122(uint8_t * buf)596 static uint32_t hal_rx_mpdu_start_tid_get_6122(uint8_t *buf)
597 {
598 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
599 struct rx_mpdu_start *mpdu_start =
600 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
601 uint32_t tid;
602
603 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
604
605 return tid;
606 }
607
608 /**
609 * hal_rx_msdu_start_reception_type_get_6122() - API to get the reception type
610 * Interval from rx_msdu_start
611 * @buf: pointer to the start of RX PKT TLV header
612 *
613 * Return: uint32_t(reception_type)
614 */
hal_rx_msdu_start_reception_type_get_6122(uint8_t * buf)615 static uint32_t hal_rx_msdu_start_reception_type_get_6122(uint8_t *buf)
616 {
617 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
618 struct rx_msdu_start *msdu_start =
619 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
620 uint32_t reception_type;
621
622 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
623
624 return reception_type;
625 }
626
627 /**
628 * hal_rx_msdu_end_da_idx_get_6122() - API to get da_idx from rx_msdu_end TLV
629 * @buf: pointer to the start of RX PKT TLV headers
630 *
631 * Return: da index
632 */
hal_rx_msdu_end_da_idx_get_6122(uint8_t * buf)633 static uint16_t hal_rx_msdu_end_da_idx_get_6122(uint8_t *buf)
634 {
635 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
636 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
637 uint16_t da_idx;
638
639 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
640
641 return da_idx;
642 }
643
644 /**
645 * hal_rx_get_rx_fragment_number_6122() - Function to retrieve rx fragment
646 * number
647 * @buf: Network buffer
648 *
649 * Return: rx fragment number
650 */
651 static
hal_rx_get_rx_fragment_number_6122(uint8_t * buf)652 uint8_t hal_rx_get_rx_fragment_number_6122(uint8_t *buf)
653 {
654 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
655 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
656
657 /* Return first 4 bits as fragment number */
658 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
659 DOT11_SEQ_FRAG_MASK);
660 }
661
662 /**
663 * hal_rx_msdu_end_da_is_mcbc_get_6122() - API to check if pkt is MCBC from
664 * rx_msdu_end TLV
665 * @buf: pointer to the start of RX PKT TLV headers
666 *
667 * Return: da_is_mcbc
668 */
669 static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_6122(uint8_t * buf)670 hal_rx_msdu_end_da_is_mcbc_get_6122(uint8_t *buf)
671 {
672 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
673 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
674
675 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
676 }
677
678 /**
679 * hal_rx_msdu_end_sa_is_valid_get_6122() - API to get_6122 the sa_is_valid bit
680 * from rx_msdu_end TLV
681 * @buf: pointer to the start of RX PKT TLV headers
682 *
683 * Return: sa_is_valid bit
684 */
685 static uint8_t
hal_rx_msdu_end_sa_is_valid_get_6122(uint8_t * buf)686 hal_rx_msdu_end_sa_is_valid_get_6122(uint8_t *buf)
687 {
688 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
689 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
690 uint8_t sa_is_valid;
691
692 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
693
694 return sa_is_valid;
695 }
696
697 /**
698 * hal_rx_msdu_end_sa_idx_get_6122() - API to get_6122 the sa_idx from
699 * rx_msdu_end TLV
700 * @buf: pointer to the start of RX PKT TLV headers
701 *
702 * Return: sa_idx (SA AST index)
703 */
hal_rx_msdu_end_sa_idx_get_6122(uint8_t * buf)704 static uint16_t hal_rx_msdu_end_sa_idx_get_6122(uint8_t *buf)
705 {
706 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
707 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
708 uint16_t sa_idx;
709
710 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
711
712 return sa_idx;
713 }
714
715 /**
716 * hal_rx_desc_is_first_msdu_6122() - Check if first msdu
717 * @hw_desc_addr: hardware descriptor address
718 *
719 * Return: 0 - success/ non-zero failure
720 */
hal_rx_desc_is_first_msdu_6122(void * hw_desc_addr)721 static uint32_t hal_rx_desc_is_first_msdu_6122(void *hw_desc_addr)
722 {
723 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
724 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
725
726 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU);
727 }
728
729 /**
730 * hal_rx_msdu_end_l3_hdr_padding_get_6122() - API to get_6122 the l3_header
731 * padding from rx_msdu_end TLV
732 * @buf: pointer to the start of RX PKT TLV headers
733 *
734 * Return: number of l3 header padding bytes
735 */
hal_rx_msdu_end_l3_hdr_padding_get_6122(uint8_t * buf)736 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6122(uint8_t *buf)
737 {
738 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
739 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
740 uint32_t l3_header_padding;
741
742 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
743
744 return l3_header_padding;
745 }
746
747 /**
748 * hal_rx_encryption_info_valid_6122() - Returns encryption type.
749 * @buf: rx_tlv_hdr of the received packet
750 *
751 * Return: encryption type
752 */
hal_rx_encryption_info_valid_6122(uint8_t * buf)753 inline uint32_t hal_rx_encryption_info_valid_6122(uint8_t *buf)
754 {
755 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
756 struct rx_mpdu_start *mpdu_start =
757 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
758 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
759 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
760
761 return encryption_info;
762 }
763
764 /**
765 * hal_rx_print_pn_6122() - Prints the PN of rx packet.
766 * @buf: rx_tlv_hdr of the received packet
767 *
768 * Return: void
769 */
hal_rx_print_pn_6122(uint8_t * buf)770 static void hal_rx_print_pn_6122(uint8_t *buf)
771 {
772 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
773 struct rx_mpdu_start *mpdu_start =
774 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
775 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
776
777 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
778 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
779 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
780 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
781
782 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x",
783 pn_127_96, pn_95_64, pn_63_32, pn_31_0);
784 }
785
786 /**
787 * hal_rx_msdu_end_first_msdu_get_6122() - API to get first msdu status from
788 * rx_msdu_end TLV
789 * @buf: pointer to the start of RX PKT TLV headers
790 *
791 * Return: first_msdu
792 */
hal_rx_msdu_end_first_msdu_get_6122(uint8_t * buf)793 static uint8_t hal_rx_msdu_end_first_msdu_get_6122(uint8_t *buf)
794 {
795 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
796 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
797 uint8_t first_msdu;
798
799 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
800
801 return first_msdu;
802 }
803
804 /**
805 * hal_rx_msdu_end_da_is_valid_get_6122() - API to check if da is valid from
806 * rx_msdu_end TLV
807 * @buf: pointer to the start of RX PKT TLV headers
808 *
809 * Return: da_is_valid
810 */
hal_rx_msdu_end_da_is_valid_get_6122(uint8_t * buf)811 static uint8_t hal_rx_msdu_end_da_is_valid_get_6122(uint8_t *buf)
812 {
813 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
814 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
815 uint8_t da_is_valid;
816
817 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
818
819 return da_is_valid;
820 }
821
822 /**
823 * hal_rx_msdu_end_last_msdu_get_6122() - API to get last msdu status from
824 * rx_msdu_end TLV
825 * @buf: pointer to the start of RX PKT TLV headers
826 *
827 * Return: last_msdu
828 */
hal_rx_msdu_end_last_msdu_get_6122(uint8_t * buf)829 static uint8_t hal_rx_msdu_end_last_msdu_get_6122(uint8_t *buf)
830 {
831 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
832 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
833 uint8_t last_msdu;
834
835 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
836
837 return last_msdu;
838 }
839
840 /**
841 * hal_rx_get_mpdu_mac_ad4_valid_6122() - Retrieves if mpdu 4th addr is valid
842 * @buf: Network buffer
843 *
844 * Return: value of mpdu 4th address valid field
845 */
hal_rx_get_mpdu_mac_ad4_valid_6122(uint8_t * buf)846 inline bool hal_rx_get_mpdu_mac_ad4_valid_6122(uint8_t *buf)
847 {
848 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
849 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
850 bool ad4_valid = 0;
851
852 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info);
853
854 return ad4_valid;
855 }
856
857 /**
858 * hal_rx_mpdu_start_sw_peer_id_get_6122() - Retrieve sw peer_id
859 * @buf: network buffer
860 *
861 * Return: sw peer_id
862 */
hal_rx_mpdu_start_sw_peer_id_get_6122(uint8_t * buf)863 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6122(uint8_t *buf)
864 {
865 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
866 struct rx_mpdu_start *mpdu_start =
867 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
868
869 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
870 &mpdu_start->rx_mpdu_info_details);
871 }
872
873 /**
874 * hal_rx_mpdu_get_to_ds_6122() - API to get the tods info from rx_mpdu_start
875 * @buf: pointer to the start of RX PKT TLV header
876 *
877 * Return: uint32_t(to_ds)
878 */
hal_rx_mpdu_get_to_ds_6122(uint8_t * buf)879 static uint32_t hal_rx_mpdu_get_to_ds_6122(uint8_t *buf)
880 {
881 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
882 struct rx_mpdu_start *mpdu_start =
883 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
884
885 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
886
887 return HAL_RX_MPDU_GET_TODS(mpdu_info);
888 }
889
890 /**
891 * hal_rx_mpdu_get_fr_ds_6122() - API to get the from ds info from rx_mpdu_start
892 * @buf: pointer to the start of RX PKT TLV header
893 *
894 * Return: uint32_t(fr_ds)
895 */
hal_rx_mpdu_get_fr_ds_6122(uint8_t * buf)896 static uint32_t hal_rx_mpdu_get_fr_ds_6122(uint8_t *buf)
897 {
898 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
899 struct rx_mpdu_start *mpdu_start =
900 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
901
902 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
903
904 return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
905 }
906
907 /**
908 * hal_rx_get_mpdu_frame_control_valid_6122() - Retrieves mpdu frame control
909 * valid
910 * @buf: Network buffer
911 *
912 * Return: value of frame control valid field
913 */
hal_rx_get_mpdu_frame_control_valid_6122(uint8_t * buf)914 static uint8_t hal_rx_get_mpdu_frame_control_valid_6122(uint8_t *buf)
915 {
916 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
917 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
918
919 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
920 }
921
922 /**
923 * hal_rx_get_mpdu_frame_control_field_6122() - Function to retrieve frame
924 * control field
925 * @buf: Network buffer
926 *
927 * Return: value of frame control field
928 *
929 */
hal_rx_get_mpdu_frame_control_field_6122(uint8_t * buf)930 static uint16_t hal_rx_get_mpdu_frame_control_field_6122(uint8_t *buf)
931 {
932 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
933 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
934 uint16_t frame_ctrl = 0;
935
936 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
937
938 return frame_ctrl;
939 }
940
941 /**
942 * hal_rx_mpdu_get_addr1_6122() - API to check get address1 of the mpdu
943 * @buf: pointer to the start of RX PKT TLV headera
944 * @mac_addr: pointer to mac address
945 *
946 * Return: success/failure
947 */
hal_rx_mpdu_get_addr1_6122(uint8_t * buf,uint8_t * mac_addr)948 static QDF_STATUS hal_rx_mpdu_get_addr1_6122(uint8_t *buf,
949 uint8_t *mac_addr)
950 {
951 struct __attribute__((__packed__)) hal_addr1 {
952 uint32_t ad1_31_0;
953 uint16_t ad1_47_32;
954 };
955
956 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
957 struct rx_mpdu_start *mpdu_start =
958 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
959
960 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
961 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
962 uint32_t mac_addr_ad1_valid;
963
964 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
965
966 if (mac_addr_ad1_valid) {
967 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
968 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
969 return QDF_STATUS_SUCCESS;
970 }
971
972 return QDF_STATUS_E_FAILURE;
973 }
974
975 /**
976 * hal_rx_mpdu_get_addr2_6122() - API to check get address2 of the mpdu in the
977 * packet
978 * @buf: pointer to the start of RX PKT TLV header
979 * @mac_addr: pointer to mac address
980 *
981 * Return: success/failure
982 */
hal_rx_mpdu_get_addr2_6122(uint8_t * buf,uint8_t * mac_addr)983 static QDF_STATUS hal_rx_mpdu_get_addr2_6122(uint8_t *buf, uint8_t *mac_addr)
984 {
985 struct __attribute__((__packed__)) hal_addr2 {
986 uint16_t ad2_15_0;
987 uint32_t ad2_47_16;
988 };
989
990 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
991 struct rx_mpdu_start *mpdu_start =
992 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
993
994 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
995 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
996 uint32_t mac_addr_ad2_valid;
997
998 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
999
1000 if (mac_addr_ad2_valid) {
1001 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
1002 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
1003 return QDF_STATUS_SUCCESS;
1004 }
1005
1006 return QDF_STATUS_E_FAILURE;
1007 }
1008
1009 /**
1010 * hal_rx_mpdu_get_addr3_6122() - API to get address3 of the mpdu in the packet
1011 * @buf: pointer to the start of RX PKT TLV header
1012 * @mac_addr: pointer to mac address
1013 *
1014 * Return: success/failure
1015 */
hal_rx_mpdu_get_addr3_6122(uint8_t * buf,uint8_t * mac_addr)1016 static QDF_STATUS hal_rx_mpdu_get_addr3_6122(uint8_t *buf, uint8_t *mac_addr)
1017 {
1018 struct __attribute__((__packed__)) hal_addr3 {
1019 uint32_t ad3_31_0;
1020 uint16_t ad3_47_32;
1021 };
1022
1023 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1024 struct rx_mpdu_start *mpdu_start =
1025 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1026
1027 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1028 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
1029 uint32_t mac_addr_ad3_valid;
1030
1031 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
1032
1033 if (mac_addr_ad3_valid) {
1034 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
1035 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
1036 return QDF_STATUS_SUCCESS;
1037 }
1038
1039 return QDF_STATUS_E_FAILURE;
1040 }
1041
1042 /**
1043 * hal_rx_mpdu_get_addr4_6122() - API to get address4 of the mpdu in the packet
1044 * @buf: pointer to the start of RX PKT TLV header
1045 * @mac_addr: pointer to mac address
1046 *
1047 * Return: success/failure
1048 */
hal_rx_mpdu_get_addr4_6122(uint8_t * buf,uint8_t * mac_addr)1049 static QDF_STATUS hal_rx_mpdu_get_addr4_6122(uint8_t *buf, uint8_t *mac_addr)
1050 {
1051 struct __attribute__((__packed__)) hal_addr4 {
1052 uint32_t ad4_31_0;
1053 uint16_t ad4_47_32;
1054 };
1055
1056 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1057 struct rx_mpdu_start *mpdu_start =
1058 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1059
1060 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1061 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
1062 uint32_t mac_addr_ad4_valid;
1063
1064 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
1065
1066 if (mac_addr_ad4_valid) {
1067 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
1068 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
1069 return QDF_STATUS_SUCCESS;
1070 }
1071
1072 return QDF_STATUS_E_FAILURE;
1073 }
1074
1075 /**
1076 * hal_rx_get_mpdu_sequence_control_valid_6122() - Get mpdu sequence control
1077 * valid
1078 * @buf: Network buffer
1079 *
1080 * Return: value of sequence control valid field
1081 */
hal_rx_get_mpdu_sequence_control_valid_6122(uint8_t * buf)1082 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6122(uint8_t *buf)
1083 {
1084 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1085 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1086
1087 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
1088 }
1089
1090 /**
1091 * hal_rx_is_unicast_6122() - check packet is unicast frame or not.
1092 * @buf: pointer to rx pkt TLV.
1093 *
1094 * Return: true on unicast.
1095 */
hal_rx_is_unicast_6122(uint8_t * buf)1096 static bool hal_rx_is_unicast_6122(uint8_t *buf)
1097 {
1098 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1099 struct rx_mpdu_start *mpdu_start =
1100 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1101 uint32_t grp_id;
1102 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
1103
1104 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
1105 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)),
1106 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK,
1107 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB));
1108
1109 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
1110 }
1111
1112 /**
1113 * hal_rx_tid_get_6122() - get tid based on qos control valid.
1114 * @hal_soc_hdl: hal soc handle
1115 * @buf: pointer to rx pkt TLV.
1116 *
1117 * Return: tid
1118 */
hal_rx_tid_get_6122(hal_soc_handle_t hal_soc_hdl,uint8_t * buf)1119 static uint32_t hal_rx_tid_get_6122(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
1120 {
1121 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1122 struct rx_mpdu_start *mpdu_start =
1123 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1124 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
1125 uint8_t qos_control_valid =
1126 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
1127 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),
1128 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK,
1129 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB));
1130
1131 if (qos_control_valid)
1132 return hal_rx_mpdu_start_tid_get_6122(buf);
1133
1134 return HAL_RX_NON_QOS_TID;
1135 }
1136
1137 /**
1138 * hal_rx_hw_desc_get_ppduid_get_6122() - retrieve ppdu id
1139 * @rx_tlv_hdr: rx tlv header
1140 * @rxdma_dst_ring_desc: rxdma HW descriptor
1141 *
1142 * Return: ppdu id
1143 */
hal_rx_hw_desc_get_ppduid_get_6122(void * rx_tlv_hdr,void * rxdma_dst_ring_desc)1144 static uint32_t hal_rx_hw_desc_get_ppduid_get_6122(void *rx_tlv_hdr,
1145 void *rxdma_dst_ring_desc)
1146 {
1147 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc;
1148
1149 return reo_ent->phy_ppdu_id;
1150 }
1151
1152 /**
1153 * hal_reo_status_get_header_6122() - Process reo desc info
1154 * @ring_desc: REO status ring descriptor
1155 * @b: tlv type info
1156 * @h1: Pointer to hal_reo_status_header where info to be stored
1157 *
1158 * Return: none.
1159 *
1160 */
hal_reo_status_get_header_6122(hal_ring_desc_t ring_desc,int b,void * h1)1161 static void hal_reo_status_get_header_6122(hal_ring_desc_t ring_desc, int b,
1162 void *h1)
1163 {
1164 uint32_t *d = (uint32_t *)ring_desc;
1165 uint32_t val1 = 0;
1166 struct hal_reo_status_header *h =
1167 (struct hal_reo_status_header *)h1;
1168
1169 /* Offsets of descriptor fields defined in HW headers start
1170 * from the field after TLV header
1171 */
1172 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
1173
1174 switch (b) {
1175 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1176 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
1177 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1178 break;
1179 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1180 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
1181 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1182 break;
1183 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1184 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
1185 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1186 break;
1187 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1188 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
1189 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1190 break;
1191 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1192 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
1193 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1194 break;
1195 case HAL_REO_DESC_THRES_STATUS_TLV:
1196 val1 =
1197 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
1198 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1199 break;
1200 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1201 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
1202 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1203 break;
1204 default:
1205 qdf_nofl_err("ERROR: Unknown tlv\n");
1206 break;
1207 }
1208 h->cmd_num =
1209 HAL_GET_FIELD(
1210 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
1211 val1);
1212 h->exec_time =
1213 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
1214 CMD_EXECUTION_TIME, val1);
1215 h->status =
1216 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
1217 REO_CMD_EXECUTION_STATUS, val1);
1218 switch (b) {
1219 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1220 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
1221 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1222 break;
1223 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1224 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
1225 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1226 break;
1227 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1228 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
1229 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1230 break;
1231 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1232 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
1233 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1234 break;
1235 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1236 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
1237 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1238 break;
1239 case HAL_REO_DESC_THRES_STATUS_TLV:
1240 val1 =
1241 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
1242 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1243 break;
1244 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1245 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
1246 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1247 break;
1248 default:
1249 qdf_nofl_err("ERROR: Unknown tlv\n");
1250 break;
1251 }
1252 h->tstamp =
1253 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
1254 }
1255
1256 /**
1257 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122() - Retrieve qos control
1258 * valid bit from the tlv.
1259 * @buf: pointer to rx pkt TLV.
1260 *
1261 * Return: qos control value.
1262 */
1263 static inline uint32_t
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122(uint8_t * buf)1264 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122(uint8_t *buf)
1265 {
1266 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1267 struct rx_mpdu_start *mpdu_start =
1268 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1269
1270 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
1271 &mpdu_start->rx_mpdu_info_details);
1272 }
1273
1274 /**
1275 * hal_rx_msdu_end_sa_sw_peer_id_get_6122() - API to get the sa_sw_peer_id from
1276 * rx_msdu_end TLV
1277 * @buf: pointer to the start of RX PKT TLV headers
1278 *
1279 * Return: sa_sw_peer_id index
1280 */
1281 static inline uint32_t
hal_rx_msdu_end_sa_sw_peer_id_get_6122(uint8_t * buf)1282 hal_rx_msdu_end_sa_sw_peer_id_get_6122(uint8_t *buf)
1283 {
1284 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1285 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1286
1287 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
1288 }
1289
1290 /**
1291 * hal_tx_desc_set_mesh_en_6122() - Set mesh_enable flag in Tx descriptor
1292 * @desc: Handle to Tx Descriptor
1293 * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
1294 * enabling the interpretation of the 'Mesh Control Present' bit
1295 * (bit 8) of QoS Control (otherwise this bit is ignored),
1296 * For native WiFi frames, this indicates that a 'Mesh Control' field
1297 * is present between the header and the LLC.
1298 *
1299 * Return: void
1300 */
1301 static inline
hal_tx_desc_set_mesh_en_6122(void * desc,uint8_t en)1302 void hal_tx_desc_set_mesh_en_6122(void *desc, uint8_t en)
1303 {
1304 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |=
1305 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
1306 }
1307
1308 static
hal_rx_msdu0_buffer_addr_lsb_6122(void * link_desc_va)1309 void *hal_rx_msdu0_buffer_addr_lsb_6122(void *link_desc_va)
1310 {
1311 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
1312 }
1313
1314 static
hal_rx_msdu_desc_info_ptr_get_6122(void * msdu0)1315 void *hal_rx_msdu_desc_info_ptr_get_6122(void *msdu0)
1316 {
1317 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
1318 }
1319
1320 static
hal_ent_mpdu_desc_info_6122(void * ent_ring_desc)1321 void *hal_ent_mpdu_desc_info_6122(void *ent_ring_desc)
1322 {
1323 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
1324 }
1325
1326 static
hal_dst_mpdu_desc_info_6122(void * dst_ring_desc)1327 void *hal_dst_mpdu_desc_info_6122(void *dst_ring_desc)
1328 {
1329 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
1330 }
1331
1332 static
hal_rx_get_fc_valid_6122(uint8_t * buf)1333 uint8_t hal_rx_get_fc_valid_6122(uint8_t *buf)
1334 {
1335 return HAL_RX_GET_FC_VALID(buf);
1336 }
1337
hal_rx_get_to_ds_flag_6122(uint8_t * buf)1338 static uint8_t hal_rx_get_to_ds_flag_6122(uint8_t *buf)
1339 {
1340 return HAL_RX_GET_TO_DS_FLAG(buf);
1341 }
1342
hal_rx_get_mac_addr2_valid_6122(uint8_t * buf)1343 static uint8_t hal_rx_get_mac_addr2_valid_6122(uint8_t *buf)
1344 {
1345 return HAL_RX_GET_MAC_ADDR2_VALID(buf);
1346 }
1347
hal_rx_get_filter_category_6122(uint8_t * buf)1348 static uint8_t hal_rx_get_filter_category_6122(uint8_t *buf)
1349 {
1350 return HAL_RX_GET_FILTER_CATEGORY(buf);
1351 }
1352
1353 static uint32_t
hal_rx_get_ppdu_id_6122(uint8_t * buf)1354 hal_rx_get_ppdu_id_6122(uint8_t *buf)
1355 {
1356 struct rx_mpdu_info *rx_mpdu_info;
1357 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf;
1358
1359 rx_mpdu_info =
1360 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
1361
1362 return HAL_RX_GET_PPDU_ID(rx_mpdu_info);
1363 }
1364
1365 /**
1366 * hal_reo_config_6122() - Set reo config parameters
1367 * @soc: hal soc handle
1368 * @reg_val: value to be set
1369 * @reo_params: reo parameters
1370 *
1371 * Return: void
1372 */
1373 static void
hal_reo_config_6122(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)1374 hal_reo_config_6122(struct hal_soc *soc,
1375 uint32_t reg_val,
1376 struct hal_reo_params *reo_params)
1377 {
1378 HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
1379 }
1380
1381 /**
1382 * hal_rx_msdu_desc_info_get_ptr_6122() - Get msdu desc info ptr
1383 * @msdu_details_ptr: Pointer to msdu_details_ptr
1384 *
1385 * Return: Pointer to rx_msdu_desc_info structure.
1386 *
1387 */
hal_rx_msdu_desc_info_get_ptr_6122(void * msdu_details_ptr)1388 static void *hal_rx_msdu_desc_info_get_ptr_6122(void *msdu_details_ptr)
1389 {
1390 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
1391 }
1392
1393 /**
1394 * hal_rx_link_desc_msdu0_ptr_6122 - Get pointer to rx_msdu details
1395 * @link_desc: Pointer to link desc
1396 *
1397 * Return: Pointer to rx_msdu_details structure
1398 *
1399 */
hal_rx_link_desc_msdu0_ptr_6122(void * link_desc)1400 static void *hal_rx_link_desc_msdu0_ptr_6122(void *link_desc)
1401 {
1402 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
1403 }
1404
1405 /**
1406 * hal_rx_msdu_flow_idx_get_6122() - API to get flow index from rx_msdu_end TLV
1407 * @buf: pointer to the start of RX PKT TLV headers
1408 *
1409 * Return: flow index value from MSDU END TLV
1410 */
hal_rx_msdu_flow_idx_get_6122(uint8_t * buf)1411 static inline uint32_t hal_rx_msdu_flow_idx_get_6122(uint8_t *buf)
1412 {
1413 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1414 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1415
1416 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
1417 }
1418
1419 /**
1420 * hal_rx_msdu_flow_idx_invalid_6122() - API to get flow index invalid from
1421 * rx_msdu_end TLV
1422 * @buf: pointer to the start of RX PKT TLV headers
1423 *
1424 * Return: flow index invalid value from MSDU END TLV
1425 */
hal_rx_msdu_flow_idx_invalid_6122(uint8_t * buf)1426 static bool hal_rx_msdu_flow_idx_invalid_6122(uint8_t *buf)
1427 {
1428 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1429 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1430
1431 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
1432 }
1433
1434 /**
1435 * hal_rx_msdu_flow_idx_timeout_6122() - API to get flow index timeout from
1436 * rx_msdu_end TLV
1437 * @buf: pointer to the start of RX PKT TLV headers
1438 *
1439 * Return: flow index timeout value from MSDU END TLV
1440 */
hal_rx_msdu_flow_idx_timeout_6122(uint8_t * buf)1441 static bool hal_rx_msdu_flow_idx_timeout_6122(uint8_t *buf)
1442 {
1443 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1444 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1445
1446 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
1447 }
1448
1449 /**
1450 * hal_rx_msdu_fse_metadata_get_6122() - API to get FSE metadata from
1451 * rx_msdu_end TLV
1452 * @buf: pointer to the start of RX PKT TLV headers
1453 *
1454 * Return: fse metadata value from MSDU END TLV
1455 */
hal_rx_msdu_fse_metadata_get_6122(uint8_t * buf)1456 static uint32_t hal_rx_msdu_fse_metadata_get_6122(uint8_t *buf)
1457 {
1458 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1459 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1460
1461 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
1462 }
1463
1464 /**
1465 * hal_rx_msdu_cce_metadata_get_6122() - API to get CCE metadata from
1466 * rx_msdu_end TLV
1467 * @buf: pointer to the start of RX PKT TLV headers
1468 *
1469 * Return: cce_metadata
1470 */
1471 static uint16_t
hal_rx_msdu_cce_metadata_get_6122(uint8_t * buf)1472 hal_rx_msdu_cce_metadata_get_6122(uint8_t *buf)
1473 {
1474 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1475 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1476
1477 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
1478 }
1479
1480 /**
1481 * hal_rx_msdu_get_flow_params_6122() - API to get flow index, flow index
1482 * invalid and flow index timeout from
1483 * rx_msdu_end TLV
1484 * @buf: pointer to the start of RX PKT TLV headers
1485 * @flow_invalid: pointer to return value of flow_idx_valid
1486 * @flow_timeout: pointer to return value of flow_idx_timeout
1487 * @flow_index: pointer to return value of flow_idx
1488 *
1489 * Return: none
1490 */
1491 static inline void
hal_rx_msdu_get_flow_params_6122(uint8_t * buf,bool * flow_invalid,bool * flow_timeout,uint32_t * flow_index)1492 hal_rx_msdu_get_flow_params_6122(uint8_t *buf,
1493 bool *flow_invalid,
1494 bool *flow_timeout,
1495 uint32_t *flow_index)
1496 {
1497 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1498 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1499
1500 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
1501 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
1502 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
1503 }
1504
1505 /**
1506 * hal_rx_tlv_get_tcp_chksum_6122() - API to get tcp checksum
1507 * @buf: rx_tlv_hdr
1508 *
1509 * Return: tcp checksum
1510 */
1511 static uint16_t
hal_rx_tlv_get_tcp_chksum_6122(uint8_t * buf)1512 hal_rx_tlv_get_tcp_chksum_6122(uint8_t *buf)
1513 {
1514 return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
1515 }
1516
1517 /**
1518 * hal_rx_get_rx_sequence_6122() - Function to retrieve rx sequence number
1519 * @buf: Network buffer
1520 *
1521 * Return: rx sequence number
1522 */
1523 static
hal_rx_get_rx_sequence_6122(uint8_t * buf)1524 uint16_t hal_rx_get_rx_sequence_6122(uint8_t *buf)
1525 {
1526 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1527 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1528
1529 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
1530 }
1531
1532 #define SPRUCE_SEQ_WCSS_UMAC_OFFSET 0x00a00000
1533 #define SPRUCE_CE_WFSS_CE_REG_BASE 0x3B80000
1534
1535 /**
1536 * hal_get_window_address_6122() - Function to get hp/tp address
1537 * @hal_soc: Pointer to hal_soc
1538 * @addr: address offset of register
1539 *
1540 * Return: modified address offset of register
1541 */
hal_get_window_address_6122(struct hal_soc * hal_soc,qdf_iomem_t addr)1542 static inline qdf_iomem_t hal_get_window_address_6122(struct hal_soc *hal_soc,
1543 qdf_iomem_t addr)
1544 {
1545 uint32_t offset = addr - hal_soc->dev_base_addr;
1546 qdf_iomem_t new_offset;
1547
1548 /*
1549 * If offset lies within DP register range, use 3rd window to write
1550 * into DP region.
1551 */
1552 if ((offset ^ SPRUCE_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) {
1553 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) +
1554 (offset & WINDOW_RANGE_MASK));
1555 /*
1556 * If offset lies within CE register range, use 2nd window to write
1557 * into CE region.
1558 */
1559 } else if ((offset ^ SPRUCE_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) {
1560 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) +
1561 (offset & WINDOW_RANGE_MASK));
1562 } else {
1563 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
1564 "%s: ERROR: Accessing Wrong register\n", __func__);
1565 qdf_assert_always(0);
1566 return 0;
1567 }
1568 return new_offset;
1569 }
1570
hal_write_window_register(struct hal_soc * hal_soc)1571 static inline void hal_write_window_register(struct hal_soc *hal_soc)
1572 {
1573 /* Write value into window configuration register */
1574 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
1575 WINDOW_CONFIGURATION_VALUE_6122);
1576 }
1577
1578 /**
1579 * hal_rx_msdu_packet_metadata_get_6122() - API to get the msdu information from
1580 * rx_msdu_end TLV
1581 * @buf: pointer to the start of RX PKT TLV headers
1582 * @msdu_pkt_metadata: pointer to the msdu info structure
1583 */
1584 static void
hal_rx_msdu_packet_metadata_get_6122(uint8_t * buf,void * msdu_pkt_metadata)1585 hal_rx_msdu_packet_metadata_get_6122(uint8_t *buf,
1586 void *msdu_pkt_metadata)
1587 {
1588 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1589 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1590 struct hal_rx_msdu_metadata *msdu_metadata =
1591 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata;
1592
1593 msdu_metadata->l3_hdr_pad =
1594 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
1595 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
1596 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
1597 msdu_metadata->sa_sw_peer_id =
1598 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
1599 }
1600
1601 /**
1602 * hal_rx_flow_setup_fse_6122() - Setup a flow search entry in HW FST
1603 * @rx_fst: Pointer to the Rx Flow Search Table
1604 * @table_offset: offset into the table where the flow is to be setup
1605 * @rx_flow: Flow Parameters
1606 *
1607 * Return: Success/Failure
1608 */
1609 static void *
hal_rx_flow_setup_fse_6122(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)1610 hal_rx_flow_setup_fse_6122(uint8_t *rx_fst, uint32_t table_offset,
1611 uint8_t *rx_flow)
1612 {
1613 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
1614 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1615 uint8_t *fse;
1616 bool fse_valid;
1617
1618 if (table_offset >= fst->max_entries) {
1619 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1620 "HAL FSE table offset %u exceeds max entries %u",
1621 table_offset, fst->max_entries);
1622 return NULL;
1623 }
1624
1625 fse = (uint8_t *)fst->base_vaddr +
1626 (table_offset * HAL_RX_FST_ENTRY_SIZE);
1627
1628 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1629
1630 if (fse_valid) {
1631 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1632 "HAL FSE %pK already valid", fse);
1633 return NULL;
1634 }
1635
1636 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) =
1637 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
1638 qdf_htonl(flow->tuple_info.src_ip_127_96));
1639
1640 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) =
1641 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
1642 qdf_htonl(flow->tuple_info.src_ip_95_64));
1643
1644 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) =
1645 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
1646 qdf_htonl(flow->tuple_info.src_ip_63_32));
1647
1648 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) =
1649 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
1650 qdf_htonl(flow->tuple_info.src_ip_31_0));
1651
1652 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) =
1653 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
1654 qdf_htonl(flow->tuple_info.dest_ip_127_96));
1655
1656 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) =
1657 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
1658 qdf_htonl(flow->tuple_info.dest_ip_95_64));
1659
1660 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) =
1661 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
1662 qdf_htonl(flow->tuple_info.dest_ip_63_32));
1663
1664 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) =
1665 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
1666 qdf_htonl(flow->tuple_info.dest_ip_31_0));
1667
1668 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT);
1669 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |=
1670 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
1671 (flow->tuple_info.dest_port));
1672
1673 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT);
1674 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |=
1675 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
1676 (flow->tuple_info.src_port));
1677
1678 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL);
1679 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |=
1680 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
1681 flow->tuple_info.l4_protocol);
1682
1683 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER);
1684 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |=
1685 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
1686 flow->reo_destination_handler);
1687
1688 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1689 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |=
1690 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
1691
1692 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA);
1693 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) =
1694 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
1695 flow->fse_metadata);
1696
1697 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION);
1698 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |=
1699 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9,
1700 REO_DESTINATION_INDICATION,
1701 flow->reo_destination_indication);
1702
1703 /* Reset all the other fields in FSE */
1704 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9);
1705 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP);
1706 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT);
1707 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT);
1708 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP);
1709
1710 return fse;
1711 }
1712
hal_compute_reo_remap_ix2_ix3_6122(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)1713 void hal_compute_reo_remap_ix2_ix3_6122(uint32_t *ring, uint32_t num_rings,
1714 uint32_t *remap1, uint32_t *remap2)
1715 {
1716 switch (num_rings) {
1717 case 1:
1718 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1719 HAL_REO_REMAP_IX2(ring[0], 17) |
1720 HAL_REO_REMAP_IX2(ring[0], 18) |
1721 HAL_REO_REMAP_IX2(ring[0], 19) |
1722 HAL_REO_REMAP_IX2(ring[0], 20) |
1723 HAL_REO_REMAP_IX2(ring[0], 21) |
1724 HAL_REO_REMAP_IX2(ring[0], 22) |
1725 HAL_REO_REMAP_IX2(ring[0], 23);
1726
1727 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1728 HAL_REO_REMAP_IX3(ring[0], 25) |
1729 HAL_REO_REMAP_IX3(ring[0], 26) |
1730 HAL_REO_REMAP_IX3(ring[0], 27) |
1731 HAL_REO_REMAP_IX3(ring[0], 28) |
1732 HAL_REO_REMAP_IX3(ring[0], 29) |
1733 HAL_REO_REMAP_IX3(ring[0], 30) |
1734 HAL_REO_REMAP_IX3(ring[0], 31);
1735 break;
1736 case 2:
1737 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1738 HAL_REO_REMAP_IX2(ring[0], 17) |
1739 HAL_REO_REMAP_IX2(ring[1], 18) |
1740 HAL_REO_REMAP_IX2(ring[1], 19) |
1741 HAL_REO_REMAP_IX2(ring[0], 20) |
1742 HAL_REO_REMAP_IX2(ring[0], 21) |
1743 HAL_REO_REMAP_IX2(ring[1], 22) |
1744 HAL_REO_REMAP_IX2(ring[1], 23);
1745
1746 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1747 HAL_REO_REMAP_IX3(ring[0], 25) |
1748 HAL_REO_REMAP_IX3(ring[1], 26) |
1749 HAL_REO_REMAP_IX3(ring[1], 27) |
1750 HAL_REO_REMAP_IX3(ring[0], 28) |
1751 HAL_REO_REMAP_IX3(ring[0], 29) |
1752 HAL_REO_REMAP_IX3(ring[1], 30) |
1753 HAL_REO_REMAP_IX3(ring[1], 31);
1754 break;
1755 case 3:
1756 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1757 HAL_REO_REMAP_IX2(ring[1], 17) |
1758 HAL_REO_REMAP_IX2(ring[2], 18) |
1759 HAL_REO_REMAP_IX2(ring[0], 19) |
1760 HAL_REO_REMAP_IX2(ring[1], 20) |
1761 HAL_REO_REMAP_IX2(ring[2], 21) |
1762 HAL_REO_REMAP_IX2(ring[0], 22) |
1763 HAL_REO_REMAP_IX2(ring[1], 23);
1764
1765 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
1766 HAL_REO_REMAP_IX3(ring[0], 25) |
1767 HAL_REO_REMAP_IX3(ring[1], 26) |
1768 HAL_REO_REMAP_IX3(ring[2], 27) |
1769 HAL_REO_REMAP_IX3(ring[0], 28) |
1770 HAL_REO_REMAP_IX3(ring[1], 29) |
1771 HAL_REO_REMAP_IX3(ring[2], 30) |
1772 HAL_REO_REMAP_IX3(ring[0], 31);
1773 break;
1774 case 4:
1775 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1776 HAL_REO_REMAP_IX2(ring[1], 17) |
1777 HAL_REO_REMAP_IX2(ring[2], 18) |
1778 HAL_REO_REMAP_IX2(ring[3], 19) |
1779 HAL_REO_REMAP_IX2(ring[0], 20) |
1780 HAL_REO_REMAP_IX2(ring[1], 21) |
1781 HAL_REO_REMAP_IX2(ring[2], 22) |
1782 HAL_REO_REMAP_IX2(ring[3], 23);
1783
1784 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1785 HAL_REO_REMAP_IX3(ring[1], 25) |
1786 HAL_REO_REMAP_IX3(ring[2], 26) |
1787 HAL_REO_REMAP_IX3(ring[3], 27) |
1788 HAL_REO_REMAP_IX3(ring[0], 28) |
1789 HAL_REO_REMAP_IX3(ring[1], 29) |
1790 HAL_REO_REMAP_IX3(ring[2], 30) |
1791 HAL_REO_REMAP_IX3(ring[3], 31);
1792 break;
1793 }
1794 }
1795
hal_hw_txrx_ops_attach_qcn6122(struct hal_soc * hal_soc)1796 static void hal_hw_txrx_ops_attach_qcn6122(struct hal_soc *hal_soc)
1797 {
1798
1799 /* init and setup */
1800 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1801 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1802 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1803 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
1804 hal_soc->ops->hal_get_window_address = hal_get_window_address_6122;
1805
1806 /* tx */
1807 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
1808 hal_tx_desc_set_dscp_tid_table_id_6122;
1809 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6122;
1810 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6122;
1811 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6122;
1812 hal_soc->ops->hal_tx_desc_set_buf_addr =
1813 hal_tx_desc_set_buf_addr_generic_li;
1814 hal_soc->ops->hal_tx_desc_set_search_type =
1815 hal_tx_desc_set_search_type_generic_li;
1816 hal_soc->ops->hal_tx_desc_set_search_index =
1817 hal_tx_desc_set_search_index_generic_li;
1818 hal_soc->ops->hal_tx_desc_set_cache_set_num =
1819 hal_tx_desc_set_cache_set_num_generic_li;
1820 hal_soc->ops->hal_tx_comp_get_status =
1821 hal_tx_comp_get_status_generic_li;
1822 hal_soc->ops->hal_tx_comp_get_release_reason =
1823 hal_tx_comp_get_release_reason_generic_li;
1824 hal_soc->ops->hal_get_wbm_internal_error =
1825 hal_get_wbm_internal_error_generic_li;
1826 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6122;
1827 hal_soc->ops->hal_tx_init_cmd_credit_ring =
1828 hal_tx_init_cmd_credit_ring_6122;
1829
1830 /* rx */
1831 hal_soc->ops->hal_rx_msdu_start_nss_get =
1832 hal_rx_msdu_start_nss_get_6122;
1833 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1834 hal_rx_mon_hw_desc_get_mpdu_status_6122;
1835 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6122;
1836 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1837 hal_rx_proc_phyrx_other_receive_info_tlv_6122;
1838
1839 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6122;
1840 hal_soc->ops->hal_rx_dump_rx_attention_tlv =
1841 hal_rx_dump_rx_attention_tlv_generic_li;
1842 hal_soc->ops->hal_rx_dump_msdu_start_tlv =
1843 hal_rx_dump_msdu_start_tlv_6122;
1844 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1845 hal_rx_dump_mpdu_start_tlv_generic_li;
1846 hal_soc->ops->hal_rx_dump_mpdu_end_tlv =
1847 hal_rx_dump_mpdu_end_tlv_generic_li;
1848 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv =
1849 hal_rx_dump_pkt_hdr_tlv_generic_li;
1850
1851 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6122;
1852 hal_soc->ops->hal_rx_mpdu_start_tid_get =
1853 hal_rx_mpdu_start_tid_get_6122;
1854 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1855 hal_rx_msdu_start_reception_type_get_6122;
1856 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1857 hal_rx_msdu_end_da_idx_get_6122;
1858 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1859 hal_rx_msdu_desc_info_get_ptr_6122;
1860 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1861 hal_rx_link_desc_msdu0_ptr_6122;
1862 hal_soc->ops->hal_reo_status_get_header =
1863 hal_reo_status_get_header_6122;
1864 hal_soc->ops->hal_rx_status_get_tlv_info =
1865 hal_rx_status_get_tlv_info_generic_li;
1866 hal_soc->ops->hal_rx_wbm_err_info_get =
1867 hal_rx_wbm_err_info_get_generic_li;
1868
1869 hal_soc->ops->hal_tx_set_pcp_tid_map =
1870 hal_tx_set_pcp_tid_map_generic_li;
1871 hal_soc->ops->hal_tx_update_pcp_tid_map =
1872 hal_tx_update_pcp_tid_generic_li;
1873 hal_soc->ops->hal_tx_set_tidmap_prty =
1874 hal_tx_update_tidmap_prty_generic_li;
1875 hal_soc->ops->hal_rx_get_rx_fragment_number =
1876 hal_rx_get_rx_fragment_number_6122;
1877 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1878 hal_rx_msdu_end_da_is_mcbc_get_6122;
1879 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1880 hal_rx_msdu_end_sa_is_valid_get_6122;
1881 hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
1882 hal_rx_msdu_end_sa_idx_get_6122;
1883 hal_soc->ops->hal_rx_desc_is_first_msdu =
1884 hal_rx_desc_is_first_msdu_6122;
1885 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1886 hal_rx_msdu_end_l3_hdr_padding_get_6122;
1887 hal_soc->ops->hal_rx_encryption_info_valid =
1888 hal_rx_encryption_info_valid_6122;
1889 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6122;
1890 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1891 hal_rx_msdu_end_first_msdu_get_6122;
1892 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1893 hal_rx_msdu_end_da_is_valid_get_6122;
1894 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1895 hal_rx_msdu_end_last_msdu_get_6122;
1896 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1897 hal_rx_get_mpdu_mac_ad4_valid_6122;
1898 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1899 hal_rx_mpdu_start_sw_peer_id_get_6122;
1900 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1901 hal_rx_mpdu_peer_meta_data_get_li;
1902 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6122;
1903 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6122;
1904 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1905 hal_rx_get_mpdu_frame_control_valid_6122;
1906 hal_soc->ops->hal_rx_get_frame_ctrl_field =
1907 hal_rx_get_mpdu_frame_control_field_6122;
1908 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6122;
1909 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6122;
1910 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6122;
1911 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6122;
1912 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1913 hal_rx_get_mpdu_sequence_control_valid_6122;
1914 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6122;
1915 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6122;
1916 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1917 hal_rx_hw_desc_get_ppduid_get_6122;
1918 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1919 hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122;
1920 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1921 hal_rx_msdu_end_sa_sw_peer_id_get_6122;
1922 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1923 hal_rx_msdu0_buffer_addr_lsb_6122;
1924 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1925 hal_rx_msdu_desc_info_ptr_get_6122;
1926 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6122;
1927 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6122;
1928 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6122;
1929 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6122;
1930 hal_soc->ops->hal_rx_get_mac_addr2_valid =
1931 hal_rx_get_mac_addr2_valid_6122;
1932 hal_soc->ops->hal_rx_get_filter_category =
1933 hal_rx_get_filter_category_6122;
1934 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6122;
1935 hal_soc->ops->hal_reo_config = hal_reo_config_6122;
1936 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6122;
1937 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1938 hal_rx_msdu_flow_idx_invalid_6122;
1939 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1940 hal_rx_msdu_flow_idx_timeout_6122;
1941 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1942 hal_rx_msdu_fse_metadata_get_6122;
1943 hal_soc->ops->hal_rx_msdu_cce_match_get =
1944 hal_rx_msdu_cce_match_get_li;
1945 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1946 hal_rx_msdu_cce_metadata_get_6122;
1947 hal_soc->ops->hal_rx_msdu_get_flow_params =
1948 hal_rx_msdu_get_flow_params_6122;
1949 hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
1950 hal_rx_tlv_get_tcp_chksum_6122;
1951 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6122;
1952 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
1953 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6122;
1954 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6122;
1955 #endif
1956 /* rx - msdu fast path info fields */
1957 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1958 hal_rx_msdu_packet_metadata_get_6122;
1959 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1960 hal_rx_mpdu_start_tlv_tag_valid_6122;
1961 hal_soc->ops->hal_rx_sw_mon_desc_info_get =
1962 hal_rx_sw_mon_desc_info_get_6122;
1963 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
1964 hal_rx_wbm_err_msdu_continuation_get_6122;
1965
1966 /* rx - TLV struct offsets */
1967 hal_soc->ops->hal_rx_msdu_end_offset_get =
1968 hal_rx_msdu_end_offset_get_generic;
1969 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
1970 hal_soc->ops->hal_rx_msdu_start_offset_get =
1971 hal_rx_msdu_start_offset_get_generic;
1972 hal_soc->ops->hal_rx_mpdu_start_offset_get =
1973 hal_rx_mpdu_start_offset_get_generic;
1974 hal_soc->ops->hal_rx_mpdu_end_offset_get =
1975 hal_rx_mpdu_end_offset_get_generic;
1976 #ifndef NO_RX_PKT_HDR_TLV
1977 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1978 hal_rx_pkt_tlv_offset_get_generic;
1979 #endif
1980 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6122;
1981 hal_soc->ops->hal_rx_flow_get_tuple_info =
1982 hal_rx_flow_get_tuple_info_li;
1983 hal_soc->ops->hal_rx_flow_delete_entry =
1984 hal_rx_flow_delete_entry_li;
1985 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li;
1986 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1987 hal_compute_reo_remap_ix2_ix3_6122;
1988 hal_soc->ops->hal_setup_link_idle_list =
1989 hal_setup_link_idle_list_generic_li;
1990 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li;
1991 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li;
1992 hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1993 hal_rx_tlv_decrypt_err_get_li;
1994 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
1995 hal_rx_tlv_get_pkt_capture_flags_li;
1996 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1997 hal_rx_mpdu_info_ampdu_flag_get_li;
1998 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
1999 hal_soc->ops->hal_rx_tlv_msdu_len_get =
2000 hal_rx_msdu_start_get_len_6122;
2001 };
2002
2003 struct hal_hw_srng_config hw_srng_table_6122[] = {
2004 /* TODO: max_rings can populated by querying HW capabilities */
2005 { /* REO_DST */
2006 .start_ring_id = HAL_SRNG_REO2SW1,
2007 .max_rings = 4,
2008 .entry_size = sizeof(struct reo_destination_ring) >> 2,
2009 .lmac_ring = FALSE,
2010 .ring_dir = HAL_SRNG_DST_RING,
2011 .reg_start = {
2012 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
2013 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2014 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
2015 SEQ_WCSS_UMAC_REO_REG_OFFSET)
2016 },
2017 .reg_size = {
2018 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
2019 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
2020 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
2021 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
2022 },
2023 .max_size =
2024 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
2025 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
2026 },
2027 { /* REO_EXCEPTION */
2028 /* Designating REO2TCL ring as exception ring. This ring is
2029 * similar to other REO2SW rings though it is named as REO2TCL.
2030 * Any of theREO2SW rings can be used as exception ring.
2031 */
2032 .start_ring_id = HAL_SRNG_REO2TCL,
2033 .max_rings = 1,
2034 .entry_size = sizeof(struct reo_destination_ring) >> 2,
2035 .lmac_ring = FALSE,
2036 .ring_dir = HAL_SRNG_DST_RING,
2037 .reg_start = {
2038 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
2039 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2040 HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
2041 SEQ_WCSS_UMAC_REO_REG_OFFSET)
2042 },
2043 /* Single ring - provide ring size if multiple rings of this
2044 * type are supported
2045 */
2046 .reg_size = {},
2047 .max_size =
2048 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
2049 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
2050 },
2051 { /* REO_REINJECT */
2052 .start_ring_id = HAL_SRNG_SW2REO,
2053 .max_rings = 1,
2054 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2055 .lmac_ring = FALSE,
2056 .ring_dir = HAL_SRNG_SRC_RING,
2057 .reg_start = {
2058 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
2059 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2060 HWIO_REO_R2_SW2REO_RING_HP_ADDR(
2061 SEQ_WCSS_UMAC_REO_REG_OFFSET)
2062 },
2063 /* Single ring - provide ring size if multiple rings of this
2064 * type are supported
2065 */
2066 .reg_size = {},
2067 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
2068 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
2069 },
2070 { /* REO_CMD */
2071 .start_ring_id = HAL_SRNG_REO_CMD,
2072 .max_rings = 1,
2073 .entry_size = (sizeof(struct tlv_32_hdr) +
2074 sizeof(struct reo_get_queue_stats)) >> 2,
2075 .lmac_ring = FALSE,
2076 .ring_dir = HAL_SRNG_SRC_RING,
2077 .reg_start = {
2078 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
2079 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2080 HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
2081 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2082 },
2083 /* Single ring - provide ring size if multiple rings of this
2084 * type are supported
2085 */
2086 .reg_size = {},
2087 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
2088 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
2089 },
2090 { /* REO_STATUS */
2091 .start_ring_id = HAL_SRNG_REO_STATUS,
2092 .max_rings = 1,
2093 .entry_size = (sizeof(struct tlv_32_hdr) +
2094 sizeof(struct reo_get_queue_stats_status)) >> 2,
2095 .lmac_ring = FALSE,
2096 .ring_dir = HAL_SRNG_DST_RING,
2097 .reg_start = {
2098 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
2099 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2100 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
2101 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2102 },
2103 /* Single ring - provide ring size if multiple rings of this
2104 * type are supported
2105 */
2106 .reg_size = {},
2107 .max_size =
2108 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
2109 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
2110 },
2111 { /* TCL_DATA */
2112 .start_ring_id = HAL_SRNG_SW2TCL1,
2113 .max_rings = 3,
2114 .entry_size = (sizeof(struct tlv_32_hdr) +
2115 sizeof(struct tcl_data_cmd)) >> 2,
2116 .lmac_ring = FALSE,
2117 .ring_dir = HAL_SRNG_SRC_RING,
2118 .reg_start = {
2119 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
2120 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2121 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
2122 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2123 },
2124 .reg_size = {
2125 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
2126 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
2127 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
2128 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
2129 },
2130 .max_size =
2131 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
2132 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
2133 },
2134 { /* TCL_CMD/CREDIT */
2135 /* qca8074v2 and qcn6122 uses this ring for data commands */
2136 .start_ring_id = HAL_SRNG_SW2TCL_CMD,
2137 .max_rings = 1,
2138 .entry_size = (sizeof(struct tlv_32_hdr) +
2139 sizeof(struct tcl_data_cmd)) >> 2,
2140 .lmac_ring = FALSE,
2141 .ring_dir = HAL_SRNG_SRC_RING,
2142 .reg_start = {
2143 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
2144 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2145 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
2146 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2147 },
2148 /* Single ring - provide ring size if multiple rings of this
2149 * type are supported
2150 */
2151 .reg_size = {},
2152 .max_size =
2153 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
2154 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
2155 },
2156 { /* TCL_STATUS */
2157 .start_ring_id = HAL_SRNG_TCL_STATUS,
2158 .max_rings = 1,
2159 .entry_size = (sizeof(struct tlv_32_hdr) +
2160 sizeof(struct tcl_status_ring)) >> 2,
2161 .lmac_ring = FALSE,
2162 .ring_dir = HAL_SRNG_DST_RING,
2163 .reg_start = {
2164 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
2165 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2166 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
2167 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2168 },
2169 /* Single ring - provide ring size if multiple rings of this
2170 * type are supported
2171 */
2172 .reg_size = {},
2173 .max_size =
2174 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
2175 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
2176 },
2177 { /* CE_SRC */
2178 .start_ring_id = HAL_SRNG_CE_0_SRC,
2179 .max_rings = 12,
2180 .entry_size = sizeof(struct ce_src_desc) >> 2,
2181 .lmac_ring = FALSE,
2182 .ring_dir = HAL_SRNG_SRC_RING,
2183 .reg_start = {
2184 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
2185 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
2186 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
2187 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
2188 },
2189 .reg_size = {
2190 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
2191 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
2192 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
2193 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
2194 },
2195 .max_size =
2196 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
2197 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
2198 },
2199 { /* CE_DST */
2200 .start_ring_id = HAL_SRNG_CE_0_DST,
2201 .max_rings = 12,
2202 .entry_size = 8 >> 2,
2203 /*TODO: entry_size above should actually be
2204 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
2205 * of struct ce_dst_desc in HW header files
2206 */
2207 .lmac_ring = FALSE,
2208 .ring_dir = HAL_SRNG_SRC_RING,
2209 .reg_start = {
2210 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
2211 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
2212 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
2213 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
2214 },
2215 .reg_size = {
2216 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
2217 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
2218 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
2219 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
2220 },
2221 .max_size =
2222 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
2223 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
2224 },
2225 { /* CE_DST_STATUS */
2226 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
2227 .max_rings = 12,
2228 .entry_size = sizeof(struct ce_stat_desc) >> 2,
2229 .lmac_ring = FALSE,
2230 .ring_dir = HAL_SRNG_DST_RING,
2231 .reg_start = {
2232 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
2233 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
2234 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
2235 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
2236 },
2237 /* TODO: check destination status ring registers */
2238 .reg_size = {
2239 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
2240 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
2241 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
2242 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
2243 },
2244 .max_size =
2245 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
2246 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
2247 },
2248 { /* WBM_IDLE_LINK */
2249 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
2250 .max_rings = 1,
2251 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
2252 .lmac_ring = FALSE,
2253 .ring_dir = HAL_SRNG_SRC_RING,
2254 .reg_start = {
2255 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2256 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2257 },
2258 /* Single ring - provide ring size if multiple rings of this
2259 * type are supported
2260 */
2261 .reg_size = {},
2262 .max_size =
2263 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
2264 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
2265 },
2266 { /* SW2WBM_RELEASE */
2267 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
2268 .max_rings = 1,
2269 .entry_size = sizeof(struct wbm_release_ring) >> 2,
2270 .lmac_ring = FALSE,
2271 .ring_dir = HAL_SRNG_SRC_RING,
2272 .reg_start = {
2273 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2274 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2275 },
2276 /* Single ring - provide ring size if multiple rings of this
2277 * type are supported
2278 */
2279 .reg_size = {},
2280 .max_size =
2281 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2282 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2283 },
2284 { /* WBM2SW_RELEASE */
2285 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
2286 .max_rings = 5,
2287 .entry_size = sizeof(struct wbm_release_ring) >> 2,
2288 .lmac_ring = FALSE,
2289 .ring_dir = HAL_SRNG_DST_RING,
2290 .reg_start = {
2291 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2292 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2293 },
2294 .reg_size = {
2295 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
2296 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2297 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
2298 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2299 },
2300 .max_size =
2301 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2302 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2303 },
2304 { /* RXDMA_BUF */
2305 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
2306 #ifdef IPA_OFFLOAD
2307 .max_rings = 3,
2308 #else
2309 .max_rings = 2,
2310 #endif
2311 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2312 .lmac_ring = TRUE,
2313 .ring_dir = HAL_SRNG_SRC_RING,
2314 /* reg_start is not set because LMAC rings are not accessed
2315 * from host
2316 */
2317 .reg_start = {},
2318 .reg_size = {},
2319 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2320 },
2321 { /* RXDMA_DST */
2322 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
2323 .max_rings = 1,
2324 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2325 .lmac_ring = TRUE,
2326 .ring_dir = HAL_SRNG_DST_RING,
2327 /* reg_start is not set because LMAC rings are not accessed
2328 * from host
2329 */
2330 .reg_start = {},
2331 .reg_size = {},
2332 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2333 },
2334 { /* RXDMA_MONITOR_BUF */
2335 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
2336 .max_rings = 1,
2337 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2338 .lmac_ring = TRUE,
2339 .ring_dir = HAL_SRNG_SRC_RING,
2340 /* reg_start is not set because LMAC rings are not accessed
2341 * from host
2342 */
2343 .reg_start = {},
2344 .reg_size = {},
2345 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2346 },
2347 { /* RXDMA_MONITOR_STATUS */
2348 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
2349 .max_rings = 1,
2350 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2351 .lmac_ring = TRUE,
2352 .ring_dir = HAL_SRNG_SRC_RING,
2353 /* reg_start is not set because LMAC rings are not accessed
2354 * from host
2355 */
2356 .reg_start = {},
2357 .reg_size = {},
2358 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2359 },
2360 { /* RXDMA_MONITOR_DST */
2361 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
2362 .max_rings = 1,
2363 .entry_size = sizeof(struct sw_monitor_ring) >> 2,
2364 .lmac_ring = TRUE,
2365 .ring_dir = HAL_SRNG_DST_RING,
2366 /* reg_start is not set because LMAC rings are not accessed
2367 * from host
2368 */
2369 .reg_start = {},
2370 .reg_size = {},
2371 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2372 },
2373 { /* RXDMA_MONITOR_DESC */
2374 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
2375 .max_rings = 1,
2376 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2377 .lmac_ring = TRUE,
2378 .ring_dir = HAL_SRNG_SRC_RING,
2379 /* reg_start is not set because LMAC rings are not accessed
2380 * from host
2381 */
2382 .reg_start = {},
2383 .reg_size = {},
2384 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2385 },
2386 { /* DIR_BUF_RX_DMA_SRC */
2387 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
2388 /* one ring for spectral and one ring for cfr */
2389 .max_rings = 2,
2390 .entry_size = 2,
2391 .lmac_ring = TRUE,
2392 .ring_dir = HAL_SRNG_SRC_RING,
2393 /* reg_start is not set because LMAC rings are not accessed
2394 * from host
2395 */
2396 .reg_start = {},
2397 .reg_size = {},
2398 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2399 },
2400 #ifdef WLAN_FEATURE_CIF_CFR
2401 { /* WIFI_POS_SRC */
2402 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
2403 .max_rings = 1,
2404 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
2405 .lmac_ring = TRUE,
2406 .ring_dir = HAL_SRNG_SRC_RING,
2407 /* reg_start is not set because LMAC rings are not accessed
2408 * from host
2409 */
2410 .reg_start = {},
2411 .reg_size = {},
2412 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2413 },
2414 #endif
2415 { /* REO2PPE */ 0},
2416 { /* PPE2TCL */ 0},
2417 { /* PPE_RELEASE */ 0},
2418 { /* TX_MONITOR_BUF */ 0},
2419 { /* TX_MONITOR_DST */ 0},
2420 { /* SW2RXDMA_NEW */ 0},
2421 { /* SW2RXDMA_LINK_RELEASE */ 0},
2422 };
2423
2424 /**
2425 * hal_qcn6122_attach() - Attach 6122 target specific hal_soc ops,
2426 * offset and srng table
2427 * @hal_soc: HAL SoC Context
2428 *
2429 * Return: void
2430 */
hal_qcn6122_attach(struct hal_soc * hal_soc)2431 void hal_qcn6122_attach(struct hal_soc *hal_soc)
2432 {
2433 hal_soc->hw_srng_table = hw_srng_table_6122;
2434 hal_srng_hw_reg_offset_init_generic(hal_soc);
2435
2436 hal_hw_txrx_default_ops_attach_li(hal_soc);
2437 hal_hw_txrx_ops_attach_qcn6122(hal_soc);
2438 if (hal_soc->static_window_map)
2439 hal_write_window_register(hal_soc);
2440 }
2441