1 /*
2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "hal_li_hw_headers.h"
20 #include "hal_internal.h"
21 #include "hal_api.h"
22 #include "target_type.h"
23 #include "wcss_version.h"
24 #include "qdf_module.h"
25 #include "hal_9000_rx.h"
26 #include "hal_api_mon.h"
27 #include "hal_flow.h"
28 #include "rx_flow_search_entry.h"
29 #include "hal_rx_flow_info.h"
30
31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
32 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
34 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK
35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
36 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB
37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \
38 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET
39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \
40 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK
41 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \
42 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB
43 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
44 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET
45 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
46 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
47 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
48 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
49 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
50 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
51 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
52 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
53 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
54 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
55 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
56 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
57 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
58 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
59 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
60 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
61 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
62 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
63 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
64 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
65 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
66 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
67 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
68 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
69 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
70 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
71 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
72 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
73 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
74 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
76 STATUS_HEADER_REO_STATUS_NUMBER
77 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
78 STATUS_HEADER_TIMESTAMP
79 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
80 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
81 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
82 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
83 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
84 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
85 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
86 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
87 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
88 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
91 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
92 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
95 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
96 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
99 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
100 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
103 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
104 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
107 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
108 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
113 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
114 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
115
116 #define CE_WINDOW_ADDRESS_9000 \
117 ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
118
119 #define UMAC_WINDOW_ADDRESS_9000 \
120 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK)
121
122 #define WINDOW_CONFIGURATION_VALUE_9000 \
123 ((CE_WINDOW_ADDRESS_9000 << 6) |\
124 (UMAC_WINDOW_ADDRESS_9000 << 12) | \
125 WINDOW_ENABLE_BIT)
126
127 #include "hal_9000_tx.h"
128 #include <hal_generic_api.h>
129 #include "hal_li_rx.h"
130 #include "hal_li_api.h"
131 #include "hal_li_generic_api.h"
132
133 /**
134 * hal_rx_sw_mon_desc_info_get_9000() - API to read the sw monitor ring
135 * descriptor
136 * @rxdma_dst_ring_desc: sw monitor ring descriptor
137 * @desc_info_buf: Descriptor info buffer to which sw monitor ring descriptor is
138 * populated to
139 *
140 * Return: void
141 */
142 static void
hal_rx_sw_mon_desc_info_get_9000(hal_ring_desc_t rxdma_dst_ring_desc,hal_rx_mon_desc_info_t desc_info_buf)143 hal_rx_sw_mon_desc_info_get_9000(hal_ring_desc_t rxdma_dst_ring_desc,
144 hal_rx_mon_desc_info_t desc_info_buf)
145 {
146 struct sw_monitor_ring *sw_mon_ring =
147 (struct sw_monitor_ring *)rxdma_dst_ring_desc;
148 struct buffer_addr_info *buf_addr_info;
149 uint32_t *mpdu_info;
150 uint32_t loop_cnt;
151 struct hal_rx_mon_desc_info *desc_info;
152
153 desc_info = (struct hal_rx_mon_desc_info *)desc_info_buf;
154 mpdu_info = (uint32_t *)&sw_mon_ring->
155 reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
156
157 loop_cnt = HAL_RX_GET(sw_mon_ring, SW_MONITOR_RING_7, LOOPING_COUNT);
158 desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info);
159
160 /* Get msdu link descriptor buf_addr_info */
161 buf_addr_info = &sw_mon_ring->
162 reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
163 desc_info->link_desc.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info)
164 | ((uint64_t)(HAL_RX_BUFFER_ADDR_39_32_GET(
165 buf_addr_info)) << 32);
166 desc_info->link_desc.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
167 buf_addr_info = &sw_mon_ring->status_buff_addr_info;
168 desc_info->status_buf.paddr = HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info)
169 | ((uint64_t)
170 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32);
171 desc_info->status_buf.sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
172 desc_info->end_of_ppdu = HAL_RX_GET(sw_mon_ring,
173 SW_MONITOR_RING_6,
174 END_OF_PPDU);
175 desc_info->status_buf_count = HAL_RX_GET(sw_mon_ring,
176 SW_MONITOR_RING_6,
177 STATUS_BUF_COUNT);
178 desc_info->rxdma_push_reason = HAL_RX_GET(sw_mon_ring,
179 SW_MONITOR_RING_6,
180 RXDMA_PUSH_REASON);
181 desc_info->rxdma_error_code = HAL_RX_GET(sw_mon_ring,
182 SW_MONITOR_RING_6,
183 RXDMA_ERROR_CODE);
184 desc_info->ppdu_id = HAL_RX_GET(sw_mon_ring,
185 SW_MONITOR_RING_7,
186 PHY_PPDU_ID);
187 }
188
189 /**
190 * hal_rx_msdu_start_nss_get_9000() - API to get the NSS from rx_msdu_start
191 * @buf: pointer to the start of RX PKT TLV header
192 *
193 * Return: uint32_t(nss)
194 */
hal_rx_msdu_start_nss_get_9000(uint8_t * buf)195 static uint32_t hal_rx_msdu_start_nss_get_9000(uint8_t *buf)
196 {
197 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
198 struct rx_msdu_start *msdu_start =
199 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
200 uint8_t mimo_ss_bitmap;
201
202 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
203
204 return qdf_get_hweight8(mimo_ss_bitmap);
205 }
206
207 /**
208 * hal_rx_msdu_start_get_len_9000() - API to get the MSDU length from
209 * rx_msdu_start TLV
210 * @buf: pointer to the start of RX PKT TLV headers
211 *
212 * Return: (uint32_t)msdu length
213 */
hal_rx_msdu_start_get_len_9000(uint8_t * buf)214 static uint32_t hal_rx_msdu_start_get_len_9000(uint8_t *buf)
215 {
216 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
217 struct rx_msdu_start *msdu_start =
218 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
219 uint32_t msdu_len;
220
221 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
222
223 return msdu_len;
224 }
225
226 /**
227 * hal_rx_mon_hw_desc_get_mpdu_status_9000() - Retrieve MPDU status
228 * @hw_desc_addr: Start address of Rx HW TLVs
229 * @rs: Status for monitor mode
230 *
231 * Return: void
232 */
hal_rx_mon_hw_desc_get_mpdu_status_9000(void * hw_desc_addr,struct mon_rx_status * rs)233 static void hal_rx_mon_hw_desc_get_mpdu_status_9000(void *hw_desc_addr,
234 struct mon_rx_status *rs)
235 {
236 struct rx_msdu_start *rx_msdu_start;
237 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
238 uint32_t reg_value;
239 const uint32_t sgi_hw_to_cdp[] = {
240 CDP_SGI_0_8_US,
241 CDP_SGI_0_4_US,
242 CDP_SGI_1_6_US,
243 CDP_SGI_3_2_US,
244 };
245
246 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
247
248 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
249
250 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
251 RX_MSDU_START_5, USER_RSSI);
252 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
253
254 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
255 rs->sgi = sgi_hw_to_cdp[reg_value];
256 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
257 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
258 /* TODO: rs->beamformed should be set for SU beamforming also */
259 }
260
261 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
262 /**
263 * hal_get_link_desc_size_9000() - API to get the link desc size
264 *
265 * Return: uint32_t
266 */
hal_get_link_desc_size_9000(void)267 static uint32_t hal_get_link_desc_size_9000(void)
268 {
269 return LINK_DESC_SIZE;
270 }
271
272 /**
273 * hal_rx_get_tlv_9000() - API to get the tlv
274 * @rx_tlv: TLV data extracted from the rx packet
275 *
276 * Return: uint8_t
277 */
hal_rx_get_tlv_9000(void * rx_tlv)278 static uint8_t hal_rx_get_tlv_9000(void *rx_tlv)
279 {
280 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
281 }
282
283 /**
284 * hal_rx_mpdu_start_tlv_tag_valid_9000() - API to check if RX_MPDU_START tlv
285 * tag is valid
286 * @rx_tlv_hdr: start address of rx_pkt_tlvs
287 *
288 * Return: true if RX_MPDU_START is valid, else false.
289 */
hal_rx_mpdu_start_tlv_tag_valid_9000(void * rx_tlv_hdr)290 uint8_t hal_rx_mpdu_start_tlv_tag_valid_9000(void *rx_tlv_hdr)
291 {
292 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
293 uint32_t tlv_tag;
294
295 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
296
297 return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
298 }
299
300 /**
301 * hal_rx_wbm_err_msdu_continuation_get_9000() - API to check if WBM msdu
302 * continuation bit is set
303 * @wbm_desc: wbm release ring descriptor
304 *
305 * Return: true if msdu continuation bit is set.
306 */
hal_rx_wbm_err_msdu_continuation_get_9000(void * wbm_desc)307 uint8_t hal_rx_wbm_err_msdu_continuation_get_9000(void *wbm_desc)
308 {
309 uint32_t comp_desc =
310 *(uint32_t *)(((uint8_t *)wbm_desc) +
311 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET);
312
313 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >>
314 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB;
315 }
316
317 /**
318 * hal_rx_proc_phyrx_other_receive_info_tlv_9000() - API to get tlv info
319 * @rx_tlv_hdr: RX TLV header
320 * @ppdu_info_hdl: handle to PPDU info rto fill
321 *
322 * Return: None
323 */
324 static inline
hal_rx_proc_phyrx_other_receive_info_tlv_9000(void * rx_tlv_hdr,void * ppdu_info_hdl)325 void hal_rx_proc_phyrx_other_receive_info_tlv_9000(void *rx_tlv_hdr,
326 void *ppdu_info_hdl)
327 {
328 }
329
330 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
331 static inline
hal_rx_get_bb_info_9000(void * rx_tlv,void * ppdu_info_hdl)332 void hal_rx_get_bb_info_9000(void *rx_tlv, void *ppdu_info_hdl)
333 {
334 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
335
336 ppdu_info->cfr_info.bb_captured_channel =
337 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL);
338
339 ppdu_info->cfr_info.bb_captured_timeout =
340 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT);
341
342 ppdu_info->cfr_info.bb_captured_reason =
343 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON);
344 }
345
346 static inline
hal_rx_get_rtt_info_9000(void * rx_tlv,void * ppdu_info_hdl)347 void hal_rx_get_rtt_info_9000(void *rx_tlv, void *ppdu_info_hdl)
348 {
349 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
350
351 ppdu_info->cfr_info.rx_location_info_valid =
352 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS,
353 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID);
354
355 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
356 HAL_RX_GET(rx_tlv,
357 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
358 RTT_CHE_BUFFER_POINTER_LOW32);
359
360 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
361 HAL_RX_GET(rx_tlv,
362 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
363 RTT_CHE_BUFFER_POINTER_HIGH8);
364
365 ppdu_info->cfr_info.chan_capture_status =
366 GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
367
368 ppdu_info->cfr_info.rx_start_ts =
369 HAL_RX_GET(rx_tlv,
370 PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
371 RX_START_TS);
372
373 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
374 HAL_RX_GET(rx_tlv,
375 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
376 RTT_CFO_MEASUREMENT);
377
378 ppdu_info->cfr_info.agc_gain_info0 =
379 HAL_RX_GET(rx_tlv,
380 PHYRX_PKT_END_1_RX_PKT_END_DETAILS,
381 PHY_TIMESTAMP_1_LOWER_32);
382
383 ppdu_info->cfr_info.agc_gain_info1 =
384 HAL_RX_GET(rx_tlv,
385 PHYRX_PKT_END_2_RX_PKT_END_DETAILS,
386 PHY_TIMESTAMP_1_UPPER_32);
387
388 ppdu_info->cfr_info.agc_gain_info2 =
389 HAL_RX_GET(rx_tlv,
390 PHYRX_PKT_END_3_RX_PKT_END_DETAILS,
391 PHY_TIMESTAMP_2_LOWER_32);
392
393 ppdu_info->cfr_info.agc_gain_info3 =
394 HAL_RX_GET(rx_tlv,
395 PHYRX_PKT_END_4_RX_PKT_END_DETAILS,
396 PHY_TIMESTAMP_2_UPPER_32);
397
398 ppdu_info->cfr_info.mcs_rate =
399 HAL_RX_GET(rx_tlv,
400 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
401 RTT_MCS_RATE);
402
403 ppdu_info->cfr_info.gi_type =
404 HAL_RX_GET(rx_tlv,
405 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
406 RTT_GI_TYPE);
407 }
408 #endif
409
410 /**
411 * hal_rx_dump_msdu_start_tlv_9000() - dump RX msdu_start TLV in structured
412 * human readable format.
413 * @pkttlvs: pointer to the pkttlvs.
414 * @dbg_level: log level.
415 *
416 * Return: void
417 */
hal_rx_dump_msdu_start_tlv_9000(void * pkttlvs,uint8_t dbg_level)418 static void hal_rx_dump_msdu_start_tlv_9000(void *pkttlvs,
419 uint8_t dbg_level)
420 {
421 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
422 struct rx_msdu_start *msdu_start =
423 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
424
425 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
426 "rx_msdu_start tlv - "
427 "rxpcu_mpdu_filter_in_category: %d "
428 "sw_frame_group_id: %d "
429 "phy_ppdu_id: %d "
430 "msdu_length: %d "
431 "ipsec_esp: %d "
432 "l3_offset: %d "
433 "ipsec_ah: %d "
434 "l4_offset: %d "
435 "msdu_number: %d "
436 "decap_format: %d "
437 "ipv4_proto: %d "
438 "ipv6_proto: %d "
439 "tcp_proto: %d "
440 "udp_proto: %d "
441 "ip_frag: %d "
442 "tcp_only_ack: %d "
443 "da_is_bcast_mcast: %d "
444 "ip4_protocol_ip6_next_header: %d "
445 "toeplitz_hash_2_or_4: %d "
446 "flow_id_toeplitz: %d "
447 "user_rssi: %d "
448 "pkt_type: %d "
449 "stbc: %d "
450 "sgi: %d "
451 "rate_mcs: %d "
452 "receive_bandwidth: %d "
453 "reception_type: %d "
454 "ppdu_start_timestamp: %d "
455 "sw_phy_meta_data: %d ",
456 msdu_start->rxpcu_mpdu_filter_in_category,
457 msdu_start->sw_frame_group_id,
458 msdu_start->phy_ppdu_id,
459 msdu_start->msdu_length,
460 msdu_start->ipsec_esp,
461 msdu_start->l3_offset,
462 msdu_start->ipsec_ah,
463 msdu_start->l4_offset,
464 msdu_start->msdu_number,
465 msdu_start->decap_format,
466 msdu_start->ipv4_proto,
467 msdu_start->ipv6_proto,
468 msdu_start->tcp_proto,
469 msdu_start->udp_proto,
470 msdu_start->ip_frag,
471 msdu_start->tcp_only_ack,
472 msdu_start->da_is_bcast_mcast,
473 msdu_start->ip4_protocol_ip6_next_header,
474 msdu_start->toeplitz_hash_2_or_4,
475 msdu_start->flow_id_toeplitz,
476 msdu_start->user_rssi,
477 msdu_start->pkt_type,
478 msdu_start->stbc,
479 msdu_start->sgi,
480 msdu_start->rate_mcs,
481 msdu_start->receive_bandwidth,
482 msdu_start->reception_type,
483 msdu_start->ppdu_start_timestamp,
484 msdu_start->sw_phy_meta_data);
485 }
486
487 /**
488 * hal_rx_dump_msdu_end_tlv_9000() - dump RX msdu_end TLV in structured
489 * human readable format.
490 * @pkttlvs: pointer to the pkttlvs.
491 * @dbg_level: log level.
492 *
493 * Return: void
494 */
hal_rx_dump_msdu_end_tlv_9000(void * pkttlvs,uint8_t dbg_level)495 static void hal_rx_dump_msdu_end_tlv_9000(void *pkttlvs,
496 uint8_t dbg_level)
497 {
498 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
499 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
500
501 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
502 "rx_msdu_end tlv - "
503 "rxpcu_mpdu_filter_in_category: %d "
504 "sw_frame_group_id: %d "
505 "phy_ppdu_id: %d "
506 "ip_hdr_chksum: %d "
507 "reported_mpdu_length: %d "
508 "key_id_octet: %d "
509 "cce_super_rule: %d "
510 "cce_classify_not_done_truncat: %d "
511 "cce_classify_not_done_cce_dis: %d "
512 "rule_indication_31_0: %d "
513 "rule_indication_63_32: %d "
514 "da_offset: %d "
515 "sa_offset: %d "
516 "da_offset_valid: %d "
517 "sa_offset_valid: %d "
518 "ipv6_options_crc: %d "
519 "tcp_seq_number: %d "
520 "tcp_ack_number: %d "
521 "tcp_flag: %d "
522 "lro_eligible: %d "
523 "window_size: %d "
524 "tcp_udp_chksum: %d "
525 "sa_idx_timeout: %d "
526 "da_idx_timeout: %d "
527 "msdu_limit_error: %d "
528 "flow_idx_timeout: %d "
529 "flow_idx_invalid: %d "
530 "wifi_parser_error: %d "
531 "amsdu_parser_error: %d "
532 "sa_is_valid: %d "
533 "da_is_valid: %d "
534 "da_is_mcbc: %d "
535 "l3_header_padding: %d "
536 "first_msdu: %d "
537 "last_msdu: %d "
538 "sa_idx: %d "
539 "msdu_drop: %d "
540 "reo_destination_indication: %d "
541 "flow_idx: %d "
542 "fse_metadata: %d "
543 "cce_metadata: %d "
544 "sa_sw_peer_id: %d ",
545 msdu_end->rxpcu_mpdu_filter_in_category,
546 msdu_end->sw_frame_group_id,
547 msdu_end->phy_ppdu_id,
548 msdu_end->ip_hdr_chksum,
549 msdu_end->reported_mpdu_length,
550 msdu_end->key_id_octet,
551 msdu_end->cce_super_rule,
552 msdu_end->cce_classify_not_done_truncate,
553 msdu_end->cce_classify_not_done_cce_dis,
554 msdu_end->rule_indication_31_0,
555 msdu_end->rule_indication_63_32,
556 msdu_end->da_offset,
557 msdu_end->sa_offset,
558 msdu_end->da_offset_valid,
559 msdu_end->sa_offset_valid,
560 msdu_end->ipv6_options_crc,
561 msdu_end->tcp_seq_number,
562 msdu_end->tcp_ack_number,
563 msdu_end->tcp_flag,
564 msdu_end->lro_eligible,
565 msdu_end->window_size,
566 msdu_end->tcp_udp_chksum,
567 msdu_end->sa_idx_timeout,
568 msdu_end->da_idx_timeout,
569 msdu_end->msdu_limit_error,
570 msdu_end->flow_idx_timeout,
571 msdu_end->flow_idx_invalid,
572 msdu_end->wifi_parser_error,
573 msdu_end->amsdu_parser_error,
574 msdu_end->sa_is_valid,
575 msdu_end->da_is_valid,
576 msdu_end->da_is_mcbc,
577 msdu_end->l3_header_padding,
578 msdu_end->first_msdu,
579 msdu_end->last_msdu,
580 msdu_end->sa_idx,
581 msdu_end->msdu_drop,
582 msdu_end->reo_destination_indication,
583 msdu_end->flow_idx,
584 msdu_end->fse_metadata,
585 msdu_end->cce_metadata,
586 msdu_end->sa_sw_peer_id);
587 }
588
589 /**
590 * hal_rx_mpdu_start_tid_get_9000() - API to get tid from rx_msdu_start
591 * @buf: pointer to the start of RX PKT TLV header
592 *
593 * Return: uint32_t(tid value)
594 */
hal_rx_mpdu_start_tid_get_9000(uint8_t * buf)595 static uint32_t hal_rx_mpdu_start_tid_get_9000(uint8_t *buf)
596 {
597 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
598 struct rx_mpdu_start *mpdu_start =
599 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
600 uint32_t tid;
601
602 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
603
604 return tid;
605 }
606
607 /**
608 * hal_rx_msdu_start_reception_type_get_9000() - API to get the reception type
609 * from rx_msdu_start
610 * @buf: pointer to the start of RX PKT TLV header
611 *
612 * Return: uint32_t(reception_type)
613 */
hal_rx_msdu_start_reception_type_get_9000(uint8_t * buf)614 static uint32_t hal_rx_msdu_start_reception_type_get_9000(uint8_t *buf)
615 {
616 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
617 struct rx_msdu_start *msdu_start =
618 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
619 uint32_t reception_type;
620
621 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
622
623 return reception_type;
624 }
625
626 /**
627 * hal_rx_msdu_end_da_idx_get_9000() - API to get da_idx from rx_msdu_end TLV
628 * @buf: pointer to the start of RX PKT TLV headers
629 *
630 * Return: da index
631 */
hal_rx_msdu_end_da_idx_get_9000(uint8_t * buf)632 static uint16_t hal_rx_msdu_end_da_idx_get_9000(uint8_t *buf)
633 {
634 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
635 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
636 uint16_t da_idx;
637
638 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
639
640 return da_idx;
641 }
642
643 /**
644 * hal_rx_get_rx_fragment_number_9000() - Function to retrieve rx fragment
645 * number
646 * @buf: Network buffer
647 *
648 * Return: rx fragment number
649 */
650 static
hal_rx_get_rx_fragment_number_9000(uint8_t * buf)651 uint8_t hal_rx_get_rx_fragment_number_9000(uint8_t *buf)
652 {
653 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
654 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
655
656 /* Return first 4 bits as fragment number */
657 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
658 DOT11_SEQ_FRAG_MASK);
659 }
660
661 /**
662 * hal_rx_msdu_end_da_is_mcbc_get_9000() - API to check if pkt is MCBC from
663 * rx_msdu_end TLV
664 * @buf: pointer to the start of RX PKT TLV headers
665 *
666 * Return: da_is_mcbc
667 */
668 static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t * buf)669 hal_rx_msdu_end_da_is_mcbc_get_9000(uint8_t *buf)
670 {
671 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
672 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
673
674 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
675 }
676
677 /**
678 * hal_rx_msdu_end_sa_is_valid_get_9000() - API to get the sa_is_valid bit
679 * from rx_msdu_end TLV
680 * @buf: pointer to the start of RX PKT TLV headers
681 *
682 * Return: sa_is_valid bit
683 */
684 static uint8_t
hal_rx_msdu_end_sa_is_valid_get_9000(uint8_t * buf)685 hal_rx_msdu_end_sa_is_valid_get_9000(uint8_t *buf)
686 {
687 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
688 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
689 uint8_t sa_is_valid;
690
691 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
692
693 return sa_is_valid;
694 }
695
696 /**
697 * hal_rx_msdu_end_sa_idx_get_9000() - API to get the sa_idx from rx_msdu_end
698 * TLV
699 * @buf: pointer to the start of RX PKT TLV headers
700 *
701 * Return: sa_idx (SA AST index)
702 */
hal_rx_msdu_end_sa_idx_get_9000(uint8_t * buf)703 static uint16_t hal_rx_msdu_end_sa_idx_get_9000(uint8_t *buf)
704 {
705 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
706 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
707 uint16_t sa_idx;
708
709 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
710
711 return sa_idx;
712 }
713
714 /**
715 * hal_rx_desc_is_first_msdu_9000() - Check if first msdu
716 * @hw_desc_addr: hardware descriptor address
717 *
718 * Return: 0 - success/ non-zero failure
719 */
hal_rx_desc_is_first_msdu_9000(void * hw_desc_addr)720 static uint32_t hal_rx_desc_is_first_msdu_9000(void *hw_desc_addr)
721 {
722 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
723 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
724
725 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU);
726 }
727
728 /**
729 * hal_rx_msdu_end_l3_hdr_padding_get_9000() - API to get the l3_header padding
730 * from rx_msdu_end TLV
731 * @buf: pointer to the start of RX PKT TLV headers
732 *
733 * Return: number of l3 header padding bytes
734 */
hal_rx_msdu_end_l3_hdr_padding_get_9000(uint8_t * buf)735 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_9000(uint8_t *buf)
736 {
737 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
738 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
739 uint32_t l3_header_padding;
740
741 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
742
743 return l3_header_padding;
744 }
745
746 /**
747 * hal_rx_encryption_info_valid_9000() - Returns encryption type.
748 * @buf: rx_tlv_hdr of the received packet
749 *
750 * Return: encryption type
751 */
hal_rx_encryption_info_valid_9000(uint8_t * buf)752 inline uint32_t hal_rx_encryption_info_valid_9000(uint8_t *buf)
753 {
754 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
755 struct rx_mpdu_start *mpdu_start =
756 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
757 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
758 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
759
760 return encryption_info;
761 }
762
763 /**
764 * hal_rx_print_pn_9000() - Prints the PN of rx packet.
765 * @buf: rx_tlv_hdr of the received packet
766 *
767 * Return: void
768 */
hal_rx_print_pn_9000(uint8_t * buf)769 static void hal_rx_print_pn_9000(uint8_t *buf)
770 {
771 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
772 struct rx_mpdu_start *mpdu_start =
773 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
774 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
775
776 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
777 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
778 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
779 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
780
781 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x",
782 pn_127_96, pn_95_64, pn_63_32, pn_31_0);
783 }
784
785 /**
786 * hal_rx_msdu_end_first_msdu_get_9000() - API to get first msdu status from
787 * rx_msdu_end TLV
788 * @buf: pointer to the start of RX PKT TLV headers
789 *
790 * Return: first_msdu
791 */
hal_rx_msdu_end_first_msdu_get_9000(uint8_t * buf)792 static uint8_t hal_rx_msdu_end_first_msdu_get_9000(uint8_t *buf)
793 {
794 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
795 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
796 uint8_t first_msdu;
797
798 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
799
800 return first_msdu;
801 }
802
803 /**
804 * hal_rx_msdu_end_da_is_valid_get_9000() - API to check if da is valid from
805 * rx_msdu_end TLV
806 * @buf: pointer to the start of RX PKT TLV headers
807 *
808 * Return: da_is_valid
809 */
hal_rx_msdu_end_da_is_valid_get_9000(uint8_t * buf)810 static uint8_t hal_rx_msdu_end_da_is_valid_get_9000(uint8_t *buf)
811 {
812 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
813 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
814 uint8_t da_is_valid;
815
816 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
817
818 return da_is_valid;
819 }
820
821 /**
822 * hal_rx_msdu_end_last_msdu_get_9000() - API to get last msdu status from
823 * rx_msdu_end TLV
824 * @buf: pointer to the start of RX PKT TLV headers
825 *
826 * Return: last_msdu
827 */
hal_rx_msdu_end_last_msdu_get_9000(uint8_t * buf)828 static uint8_t hal_rx_msdu_end_last_msdu_get_9000(uint8_t *buf)
829 {
830 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
831 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
832 uint8_t last_msdu;
833
834 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
835
836 return last_msdu;
837 }
838
839 /**
840 * hal_rx_get_mpdu_mac_ad4_valid_9000() - Retrieves if mpdu 4th addr is valid
841 * @buf: Network buffer
842 *
843 * Return: value of mpdu 4th address valid field
844 */
hal_rx_get_mpdu_mac_ad4_valid_9000(uint8_t * buf)845 inline bool hal_rx_get_mpdu_mac_ad4_valid_9000(uint8_t *buf)
846 {
847 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
848 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
849 bool ad4_valid = 0;
850
851 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info);
852
853 return ad4_valid;
854 }
855
856 /**
857 * hal_rx_mpdu_start_sw_peer_id_get_9000() - Retrieve sw peer_id
858 * @buf: network buffer
859 *
860 * Return: sw peer_id
861 */
hal_rx_mpdu_start_sw_peer_id_get_9000(uint8_t * buf)862 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_9000(uint8_t *buf)
863 {
864 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
865 struct rx_mpdu_start *mpdu_start =
866 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
867
868 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
869 &mpdu_start->rx_mpdu_info_details);
870 }
871
872 /**
873 * hal_rx_mpdu_get_to_ds_9000() - API to get the tods info from rx_mpdu_start
874 * @buf: pointer to the start of RX PKT TLV header
875 *
876 * Return: uint32_t(to_ds)
877 */
hal_rx_mpdu_get_to_ds_9000(uint8_t * buf)878 static uint32_t hal_rx_mpdu_get_to_ds_9000(uint8_t *buf)
879 {
880 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
881 struct rx_mpdu_start *mpdu_start =
882 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
883
884 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
885
886 return HAL_RX_MPDU_GET_TODS(mpdu_info);
887 }
888
889 /**
890 * hal_rx_mpdu_get_fr_ds_9000() - API to get the from ds info from rx_mpdu_start
891 * @buf: pointer to the start of RX PKT TLV header
892 *
893 * Return: uint32_t(fr_ds)
894 */
hal_rx_mpdu_get_fr_ds_9000(uint8_t * buf)895 static uint32_t hal_rx_mpdu_get_fr_ds_9000(uint8_t *buf)
896 {
897 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
898 struct rx_mpdu_start *mpdu_start =
899 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
900
901 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
902
903 return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
904 }
905
906 /**
907 * hal_rx_get_mpdu_frame_control_valid_9000() - Retrieves mpdu frame control
908 * valid
909 * @buf: Network buffer
910 *
911 * Return: value of frame control valid field
912 */
hal_rx_get_mpdu_frame_control_valid_9000(uint8_t * buf)913 static uint8_t hal_rx_get_mpdu_frame_control_valid_9000(uint8_t *buf)
914 {
915 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
916 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
917
918 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
919 }
920
921 /**
922 * hal_rx_get_mpdu_frame_control_field_9000() - Function to retrieve frame
923 * control field
924 * @buf: Network buffer
925 *
926 * Return: value of frame control field
927 *
928 */
hal_rx_get_mpdu_frame_control_field_9000(uint8_t * buf)929 static uint16_t hal_rx_get_mpdu_frame_control_field_9000(uint8_t *buf)
930 {
931 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
932 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
933 uint16_t frame_ctrl = 0;
934
935 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
936
937 return frame_ctrl;
938 }
939
940 /**
941 * hal_rx_mpdu_get_addr1_9000() - API to check get address1 of the mpdu
942 * @buf: pointer to the start of RX PKT TLV headera
943 * @mac_addr: pointer to mac address
944 *
945 * Return: success/failure
946 */
hal_rx_mpdu_get_addr1_9000(uint8_t * buf,uint8_t * mac_addr)947 static QDF_STATUS hal_rx_mpdu_get_addr1_9000(uint8_t *buf,
948 uint8_t *mac_addr)
949 {
950 struct __attribute__((__packed__)) hal_addr1 {
951 uint32_t ad1_31_0;
952 uint16_t ad1_47_32;
953 };
954
955 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
956 struct rx_mpdu_start *mpdu_start =
957 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
958
959 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
960 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
961 uint32_t mac_addr_ad1_valid;
962
963 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
964
965 if (mac_addr_ad1_valid) {
966 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
967 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
968 return QDF_STATUS_SUCCESS;
969 }
970
971 return QDF_STATUS_E_FAILURE;
972 }
973
974 /**
975 * hal_rx_mpdu_get_addr2_9000() - API to check get address2 of the mpdu in the
976 * packet
977 * @buf: pointer to the start of RX PKT TLV header
978 * @mac_addr: pointer to mac address
979 *
980 * Return: success/failure
981 */
hal_rx_mpdu_get_addr2_9000(uint8_t * buf,uint8_t * mac_addr)982 static QDF_STATUS hal_rx_mpdu_get_addr2_9000(uint8_t *buf, uint8_t *mac_addr)
983 {
984 struct __attribute__((__packed__)) hal_addr2 {
985 uint16_t ad2_15_0;
986 uint32_t ad2_47_16;
987 };
988
989 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
990 struct rx_mpdu_start *mpdu_start =
991 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
992
993 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
994 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
995 uint32_t mac_addr_ad2_valid;
996
997 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
998
999 if (mac_addr_ad2_valid) {
1000 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
1001 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
1002 return QDF_STATUS_SUCCESS;
1003 }
1004
1005 return QDF_STATUS_E_FAILURE;
1006 }
1007
1008 /**
1009 * hal_rx_mpdu_get_addr3_9000() - API to get address3 of the mpdu in the packet
1010 * @buf: pointer to the start of RX PKT TLV header
1011 * @mac_addr: pointer to mac address
1012 *
1013 * Return: success/failure
1014 */
hal_rx_mpdu_get_addr3_9000(uint8_t * buf,uint8_t * mac_addr)1015 static QDF_STATUS hal_rx_mpdu_get_addr3_9000(uint8_t *buf, uint8_t *mac_addr)
1016 {
1017 struct __attribute__((__packed__)) hal_addr3 {
1018 uint32_t ad3_31_0;
1019 uint16_t ad3_47_32;
1020 };
1021
1022 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1023 struct rx_mpdu_start *mpdu_start =
1024 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1025
1026 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1027 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
1028 uint32_t mac_addr_ad3_valid;
1029
1030 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
1031
1032 if (mac_addr_ad3_valid) {
1033 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
1034 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
1035 return QDF_STATUS_SUCCESS;
1036 }
1037
1038 return QDF_STATUS_E_FAILURE;
1039 }
1040
1041 /**
1042 * hal_rx_mpdu_get_addr4_9000() - API to get address4 of the mpdu in the packet
1043 * @buf: pointer to the start of RX PKT TLV header
1044 * @mac_addr: pointer to mac address
1045 *
1046 * Return: success/failure
1047 */
hal_rx_mpdu_get_addr4_9000(uint8_t * buf,uint8_t * mac_addr)1048 static QDF_STATUS hal_rx_mpdu_get_addr4_9000(uint8_t *buf, uint8_t *mac_addr)
1049 {
1050 struct __attribute__((__packed__)) hal_addr4 {
1051 uint32_t ad4_31_0;
1052 uint16_t ad4_47_32;
1053 };
1054
1055 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1056 struct rx_mpdu_start *mpdu_start =
1057 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1058
1059 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1060 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
1061 uint32_t mac_addr_ad4_valid;
1062
1063 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
1064
1065 if (mac_addr_ad4_valid) {
1066 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
1067 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
1068 return QDF_STATUS_SUCCESS;
1069 }
1070
1071 return QDF_STATUS_E_FAILURE;
1072 }
1073
1074 /**
1075 * hal_rx_get_mpdu_sequence_control_valid_9000() - Get mpdu sequence control
1076 * valid
1077 * @buf: Network buffer
1078 *
1079 * Return: value of sequence control valid field
1080 */
hal_rx_get_mpdu_sequence_control_valid_9000(uint8_t * buf)1081 static uint8_t hal_rx_get_mpdu_sequence_control_valid_9000(uint8_t *buf)
1082 {
1083 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1084 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1085
1086 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
1087 }
1088
1089 /**
1090 * hal_rx_is_unicast_9000() - check packet is unicast frame or not.
1091 * @buf: pointer to rx pkt TLV.
1092 *
1093 * Return: true on unicast.
1094 */
hal_rx_is_unicast_9000(uint8_t * buf)1095 static bool hal_rx_is_unicast_9000(uint8_t *buf)
1096 {
1097 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1098 struct rx_mpdu_start *mpdu_start =
1099 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1100 uint32_t grp_id;
1101 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
1102
1103 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
1104 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)),
1105 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK,
1106 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB));
1107
1108 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
1109 }
1110
1111 /**
1112 * hal_rx_tid_get_9000() - get tid based on qos control valid.
1113 * @hal_soc_hdl: hal soc handle
1114 * @buf: pointer to rx pkt TLV.
1115 *
1116 * Return: tid
1117 */
hal_rx_tid_get_9000(hal_soc_handle_t hal_soc_hdl,uint8_t * buf)1118 static uint32_t hal_rx_tid_get_9000(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
1119 {
1120 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1121 struct rx_mpdu_start *mpdu_start =
1122 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1123 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
1124 uint8_t qos_control_valid =
1125 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
1126 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),
1127 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK,
1128 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB));
1129
1130 if (qos_control_valid)
1131 return hal_rx_mpdu_start_tid_get_9000(buf);
1132
1133 return HAL_RX_NON_QOS_TID;
1134 }
1135
1136 /**
1137 * hal_rx_hw_desc_get_ppduid_get_9000() - retrieve ppdu id
1138 * @rx_tlv_hdr: rx tlv header
1139 * @rxdma_dst_ring_desc: rxdma HW descriptor
1140 *
1141 * Return: ppdu id
1142 */
hal_rx_hw_desc_get_ppduid_get_9000(void * rx_tlv_hdr,void * rxdma_dst_ring_desc)1143 static uint32_t hal_rx_hw_desc_get_ppduid_get_9000(void *rx_tlv_hdr,
1144 void *rxdma_dst_ring_desc)
1145 {
1146 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc;
1147
1148 return reo_ent->phy_ppdu_id;
1149 }
1150
1151 /**
1152 * hal_reo_status_get_header_9000() - Process reo desc info
1153 * @ring_desc: REO status ring descriptor
1154 * @b: tlv type info
1155 * @h1: Pointer to hal_reo_status_header where info to be stored
1156 *
1157 * Return: none.
1158 *
1159 */
hal_reo_status_get_header_9000(hal_ring_desc_t ring_desc,int b,void * h1)1160 static void hal_reo_status_get_header_9000(hal_ring_desc_t ring_desc, int b,
1161 void *h1)
1162 {
1163 uint32_t *d = (uint32_t *)ring_desc;
1164 uint32_t val1 = 0;
1165 struct hal_reo_status_header *h =
1166 (struct hal_reo_status_header *)h1;
1167
1168 /* Offsets of descriptor fields defined in HW headers start
1169 * from the field after TLV header
1170 */
1171 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
1172
1173 switch (b) {
1174 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1175 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
1176 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1177 break;
1178 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1179 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
1180 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1181 break;
1182 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1183 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
1184 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1185 break;
1186 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1187 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
1188 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1189 break;
1190 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1191 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
1192 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1193 break;
1194 case HAL_REO_DESC_THRES_STATUS_TLV:
1195 val1 =
1196 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
1197 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1198 break;
1199 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1200 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
1201 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
1202 break;
1203 default:
1204 qdf_nofl_err("ERROR: Unknown tlv\n");
1205 break;
1206 }
1207 h->cmd_num =
1208 HAL_GET_FIELD(
1209 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
1210 val1);
1211 h->exec_time =
1212 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
1213 CMD_EXECUTION_TIME, val1);
1214 h->status =
1215 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
1216 REO_CMD_EXECUTION_STATUS, val1);
1217 switch (b) {
1218 case HAL_REO_QUEUE_STATS_STATUS_TLV:
1219 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
1220 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1221 break;
1222 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
1223 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
1224 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1225 break;
1226 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
1227 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
1228 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1229 break;
1230 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
1231 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
1232 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1233 break;
1234 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
1235 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
1236 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1237 break;
1238 case HAL_REO_DESC_THRES_STATUS_TLV:
1239 val1 =
1240 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
1241 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1242 break;
1243 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
1244 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
1245 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
1246 break;
1247 default:
1248 qdf_nofl_err("ERROR: Unknown tlv\n");
1249 break;
1250 }
1251 h->tstamp =
1252 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
1253 }
1254
1255 /**
1256 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000() - Retrieve qos control
1257 * valid bit from the tlv.
1258 * @buf: pointer to rx pkt TLV.
1259 *
1260 * Return: qos control value.
1261 */
1262 static inline uint32_t
hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(uint8_t * buf)1263 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000(uint8_t *buf)
1264 {
1265 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1266 struct rx_mpdu_start *mpdu_start =
1267 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1268
1269 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
1270 &mpdu_start->rx_mpdu_info_details);
1271 }
1272
1273 /**
1274 * hal_rx_msdu_end_sa_sw_peer_id_get_9000() - API to get the sa_sw_peer_id from
1275 * rx_msdu_end TLV
1276 * @buf: pointer to the start of RX PKT TLV headers
1277 *
1278 * Return: sa_sw_peer_id index
1279 */
1280 static inline uint32_t
hal_rx_msdu_end_sa_sw_peer_id_get_9000(uint8_t * buf)1281 hal_rx_msdu_end_sa_sw_peer_id_get_9000(uint8_t *buf)
1282 {
1283 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1284 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1285
1286 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
1287 }
1288
1289 /**
1290 * hal_tx_desc_set_mesh_en_9000() - Set mesh_enable flag in Tx descriptor
1291 * @desc: Handle to Tx Descriptor
1292 * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
1293 * enabling the interpretation of the 'Mesh Control Present' bit
1294 * (bit 8) of QoS Control (otherwise this bit is ignored),
1295 * For native WiFi frames, this indicates that a 'Mesh Control' field
1296 * is present between the header and the LLC.
1297 *
1298 * Return: void
1299 */
1300 static inline
hal_tx_desc_set_mesh_en_9000(void * desc,uint8_t en)1301 void hal_tx_desc_set_mesh_en_9000(void *desc, uint8_t en)
1302 {
1303 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |=
1304 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
1305 }
1306
1307 static
hal_rx_msdu0_buffer_addr_lsb_9000(void * link_desc_va)1308 void *hal_rx_msdu0_buffer_addr_lsb_9000(void *link_desc_va)
1309 {
1310 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
1311 }
1312
1313 static
hal_rx_msdu_desc_info_ptr_get_9000(void * msdu0)1314 void *hal_rx_msdu_desc_info_ptr_get_9000(void *msdu0)
1315 {
1316 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
1317 }
1318
1319 static
hal_ent_mpdu_desc_info_9000(void * ent_ring_desc)1320 void *hal_ent_mpdu_desc_info_9000(void *ent_ring_desc)
1321 {
1322 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
1323 }
1324
1325 static
hal_dst_mpdu_desc_info_9000(void * dst_ring_desc)1326 void *hal_dst_mpdu_desc_info_9000(void *dst_ring_desc)
1327 {
1328 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
1329 }
1330
1331 static
hal_rx_get_fc_valid_9000(uint8_t * buf)1332 uint8_t hal_rx_get_fc_valid_9000(uint8_t *buf)
1333 {
1334 return HAL_RX_GET_FC_VALID(buf);
1335 }
1336
hal_rx_get_to_ds_flag_9000(uint8_t * buf)1337 static uint8_t hal_rx_get_to_ds_flag_9000(uint8_t *buf)
1338 {
1339 return HAL_RX_GET_TO_DS_FLAG(buf);
1340 }
1341
hal_rx_get_mac_addr2_valid_9000(uint8_t * buf)1342 static uint8_t hal_rx_get_mac_addr2_valid_9000(uint8_t *buf)
1343 {
1344 return HAL_RX_GET_MAC_ADDR2_VALID(buf);
1345 }
1346
hal_rx_get_filter_category_9000(uint8_t * buf)1347 static uint8_t hal_rx_get_filter_category_9000(uint8_t *buf)
1348 {
1349 return HAL_RX_GET_FILTER_CATEGORY(buf);
1350 }
1351
1352 static uint32_t
hal_rx_get_ppdu_id_9000(uint8_t * buf)1353 hal_rx_get_ppdu_id_9000(uint8_t *buf)
1354 {
1355 struct rx_mpdu_info *rx_mpdu_info;
1356 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf;
1357
1358 rx_mpdu_info =
1359 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
1360
1361 return HAL_RX_GET_PPDU_ID(rx_mpdu_info);
1362 }
1363
1364 /**
1365 * hal_reo_config_9000() - Set reo config parameters
1366 * @soc: hal soc handle
1367 * @reg_val: value to be set
1368 * @reo_params: reo parameters
1369 *
1370 * Return: void
1371 */
1372 static void
hal_reo_config_9000(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)1373 hal_reo_config_9000(struct hal_soc *soc,
1374 uint32_t reg_val,
1375 struct hal_reo_params *reo_params)
1376 {
1377 HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
1378 }
1379
1380 /**
1381 * hal_rx_msdu_desc_info_get_ptr_9000() - Get msdu desc info ptr
1382 * @msdu_details_ptr: Pointer to msdu_details_ptr
1383 *
1384 * Return: Pointer to rx_msdu_desc_info structure.
1385 *
1386 */
hal_rx_msdu_desc_info_get_ptr_9000(void * msdu_details_ptr)1387 static void *hal_rx_msdu_desc_info_get_ptr_9000(void *msdu_details_ptr)
1388 {
1389 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
1390 }
1391
1392 /**
1393 * hal_rx_link_desc_msdu0_ptr_9000() - Get pointer to rx_msdu details
1394 * @link_desc: Pointer to link desc
1395 *
1396 * Return: Pointer to rx_msdu_details structure
1397 *
1398 */
hal_rx_link_desc_msdu0_ptr_9000(void * link_desc)1399 static void *hal_rx_link_desc_msdu0_ptr_9000(void *link_desc)
1400 {
1401 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
1402 }
1403
1404 /**
1405 * hal_rx_msdu_flow_idx_get_9000() - API to get flow index from rx_msdu_end TLV
1406 * @buf: pointer to the start of RX PKT TLV headers
1407 *
1408 * Return: flow index value from MSDU END TLV
1409 */
hal_rx_msdu_flow_idx_get_9000(uint8_t * buf)1410 static inline uint32_t hal_rx_msdu_flow_idx_get_9000(uint8_t *buf)
1411 {
1412 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1413 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1414
1415 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
1416 }
1417
1418 /**
1419 * hal_rx_msdu_flow_idx_invalid_9000() - API to get flow index invalid from
1420 * rx_msdu_end TLV
1421 * @buf: pointer to the start of RX PKT TLV headers
1422 *
1423 * Return: flow index invalid value from MSDU END TLV
1424 */
hal_rx_msdu_flow_idx_invalid_9000(uint8_t * buf)1425 static bool hal_rx_msdu_flow_idx_invalid_9000(uint8_t *buf)
1426 {
1427 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1428 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1429
1430 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
1431 }
1432
1433 /**
1434 * hal_rx_msdu_flow_idx_timeout_9000() - API to get flow index timeout from
1435 * rx_msdu_end TLV
1436 * @buf: pointer to the start of RX PKT TLV headers
1437 *
1438 * Return: flow index timeout value from MSDU END TLV
1439 */
hal_rx_msdu_flow_idx_timeout_9000(uint8_t * buf)1440 static bool hal_rx_msdu_flow_idx_timeout_9000(uint8_t *buf)
1441 {
1442 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1443 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1444
1445 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
1446 }
1447
1448 /**
1449 * hal_rx_msdu_fse_metadata_get_9000() - API to get FSE metadata from
1450 * rx_msdu_end TLV
1451 * @buf: pointer to the start of RX PKT TLV headers
1452 *
1453 * Return: fse metadata value from MSDU END TLV
1454 */
hal_rx_msdu_fse_metadata_get_9000(uint8_t * buf)1455 static uint32_t hal_rx_msdu_fse_metadata_get_9000(uint8_t *buf)
1456 {
1457 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1458 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1459
1460 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
1461 }
1462
1463 /**
1464 * hal_rx_msdu_cce_metadata_get_9000() - API to get CCE metadata from
1465 * rx_msdu_end TLV
1466 * @buf: pointer to the start of RX PKT TLV headers
1467 *
1468 * Return: cce_metadata
1469 */
1470 static uint16_t
hal_rx_msdu_cce_metadata_get_9000(uint8_t * buf)1471 hal_rx_msdu_cce_metadata_get_9000(uint8_t *buf)
1472 {
1473 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1474 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1475
1476 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
1477 }
1478
1479 /**
1480 * hal_rx_msdu_get_flow_params_9000() - API to get flow index, flow index
1481 * invalid and flow index timeout from
1482 * rx_msdu_end TLV
1483 * @buf: pointer to the start of RX PKT TLV headers
1484 * @flow_invalid: pointer to return value of flow_idx_valid
1485 * @flow_timeout: pointer to return value of flow_idx_timeout
1486 * @flow_index: pointer to return value of flow_idx
1487 *
1488 * Return: none
1489 */
1490 static inline void
hal_rx_msdu_get_flow_params_9000(uint8_t * buf,bool * flow_invalid,bool * flow_timeout,uint32_t * flow_index)1491 hal_rx_msdu_get_flow_params_9000(uint8_t *buf,
1492 bool *flow_invalid,
1493 bool *flow_timeout,
1494 uint32_t *flow_index)
1495 {
1496 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1497 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1498
1499 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
1500 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
1501 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
1502 }
1503
1504 /**
1505 * hal_rx_tlv_get_tcp_chksum_9000() - API to get tcp checksum
1506 * @buf: rx_tlv_hdr
1507 *
1508 * Return: tcp checksum
1509 */
1510 static uint16_t
hal_rx_tlv_get_tcp_chksum_9000(uint8_t * buf)1511 hal_rx_tlv_get_tcp_chksum_9000(uint8_t *buf)
1512 {
1513 return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
1514 }
1515
1516 /**
1517 * hal_rx_get_rx_sequence_9000() - Function to retrieve rx sequence number
1518 * @buf: Network buffer
1519 *
1520 * Return: rx sequence number
1521 */
1522 static
hal_rx_get_rx_sequence_9000(uint8_t * buf)1523 uint16_t hal_rx_get_rx_sequence_9000(uint8_t *buf)
1524 {
1525 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1526 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1527
1528 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
1529 }
1530
1531 /**
1532 * hal_get_window_address_9000() - Function to get hp/tp address
1533 * @hal_soc: Pointer to hal_soc
1534 * @addr: address offset of register
1535 *
1536 * Return: modified address offset of register
1537 */
hal_get_window_address_9000(struct hal_soc * hal_soc,qdf_iomem_t addr)1538 static inline qdf_iomem_t hal_get_window_address_9000(struct hal_soc *hal_soc,
1539 qdf_iomem_t addr)
1540 {
1541 uint32_t offset = addr - hal_soc->dev_base_addr;
1542 qdf_iomem_t new_offset;
1543
1544 /*
1545 * If offset lies within DP register range, use 3rd window to write
1546 * into DP region.
1547 */
1548 if ((offset ^ SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) {
1549 new_offset = (hal_soc->dev_base_addr + (3 * WINDOW_START) +
1550 (offset & WINDOW_RANGE_MASK));
1551 /*
1552 * If offset lies within CE register range, use 2nd window to write
1553 * into CE region.
1554 */
1555 } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) {
1556 new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) +
1557 (offset & WINDOW_RANGE_MASK));
1558 } else {
1559 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
1560 "%s: ERROR: Accessing Wrong register\n", __func__);
1561 qdf_assert_always(0);
1562 return 0;
1563 }
1564 return new_offset;
1565 }
1566
hal_write_window_register(struct hal_soc * hal_soc)1567 static inline void hal_write_window_register(struct hal_soc *hal_soc)
1568 {
1569 /* Write value into window configuration register */
1570 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS,
1571 WINDOW_CONFIGURATION_VALUE_9000);
1572 }
1573
1574 /**
1575 * hal_rx_msdu_packet_metadata_get_9000() - API to get the msdu information from
1576 * rx_msdu_end TLV
1577 * @buf: pointer to the start of RX PKT TLV headers
1578 * @msdu_pkt_metadata: pointer to the msdu info structure
1579 */
1580 static void
hal_rx_msdu_packet_metadata_get_9000(uint8_t * buf,void * msdu_pkt_metadata)1581 hal_rx_msdu_packet_metadata_get_9000(uint8_t *buf,
1582 void *msdu_pkt_metadata)
1583 {
1584 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1585 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1586 struct hal_rx_msdu_metadata *msdu_metadata =
1587 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata;
1588
1589 msdu_metadata->l3_hdr_pad =
1590 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
1591 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
1592 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
1593 msdu_metadata->sa_sw_peer_id =
1594 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
1595 }
1596
1597 /**
1598 * hal_rx_flow_setup_fse_9000() - Setup a flow search entry in HW FST
1599 * @rx_fst: Pointer to the Rx Flow Search Table
1600 * @table_offset: offset into the table where the flow is to be setup
1601 * @rx_flow: Flow Parameters
1602 *
1603 * Return: Success/Failure
1604 */
1605 static void *
hal_rx_flow_setup_fse_9000(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)1606 hal_rx_flow_setup_fse_9000(uint8_t *rx_fst, uint32_t table_offset,
1607 uint8_t *rx_flow)
1608 {
1609 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
1610 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1611 uint8_t *fse;
1612 bool fse_valid;
1613
1614 if (table_offset >= fst->max_entries) {
1615 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1616 "HAL FSE table offset %u exceeds max entries %u",
1617 table_offset, fst->max_entries);
1618 return NULL;
1619 }
1620
1621 fse = (uint8_t *)fst->base_vaddr +
1622 (table_offset * HAL_RX_FST_ENTRY_SIZE);
1623
1624 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1625
1626 if (fse_valid) {
1627 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1628 "HAL FSE %pK already valid", fse);
1629 return NULL;
1630 }
1631
1632 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) =
1633 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
1634 qdf_htonl(flow->tuple_info.src_ip_127_96));
1635
1636 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) =
1637 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
1638 qdf_htonl(flow->tuple_info.src_ip_95_64));
1639
1640 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) =
1641 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
1642 qdf_htonl(flow->tuple_info.src_ip_63_32));
1643
1644 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) =
1645 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
1646 qdf_htonl(flow->tuple_info.src_ip_31_0));
1647
1648 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) =
1649 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
1650 qdf_htonl(flow->tuple_info.dest_ip_127_96));
1651
1652 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) =
1653 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
1654 qdf_htonl(flow->tuple_info.dest_ip_95_64));
1655
1656 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) =
1657 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
1658 qdf_htonl(flow->tuple_info.dest_ip_63_32));
1659
1660 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) =
1661 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
1662 qdf_htonl(flow->tuple_info.dest_ip_31_0));
1663
1664 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT);
1665 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |=
1666 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
1667 (flow->tuple_info.dest_port));
1668
1669 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT);
1670 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |=
1671 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
1672 (flow->tuple_info.src_port));
1673
1674 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL);
1675 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |=
1676 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
1677 flow->tuple_info.l4_protocol);
1678
1679 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER);
1680 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |=
1681 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
1682 flow->reo_destination_handler);
1683
1684 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1685 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |=
1686 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
1687
1688 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA);
1689 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) =
1690 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
1691 flow->fse_metadata);
1692
1693 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION);
1694 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |=
1695 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9,
1696 REO_DESTINATION_INDICATION,
1697 flow->reo_destination_indication);
1698
1699 /* Reset all the other fields in FSE */
1700 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9);
1701 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP);
1702 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT);
1703 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT);
1704 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP);
1705
1706 return fse;
1707 }
1708
1709 static
hal_compute_reo_remap_ix2_ix3_9000(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)1710 void hal_compute_reo_remap_ix2_ix3_9000(uint32_t *ring, uint32_t num_rings,
1711 uint32_t *remap1, uint32_t *remap2)
1712 {
1713 switch (num_rings) {
1714 case 1:
1715 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1716 HAL_REO_REMAP_IX2(ring[0], 17) |
1717 HAL_REO_REMAP_IX2(ring[0], 18) |
1718 HAL_REO_REMAP_IX2(ring[0], 19) |
1719 HAL_REO_REMAP_IX2(ring[0], 20) |
1720 HAL_REO_REMAP_IX2(ring[0], 21) |
1721 HAL_REO_REMAP_IX2(ring[0], 22) |
1722 HAL_REO_REMAP_IX2(ring[0], 23);
1723
1724 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1725 HAL_REO_REMAP_IX3(ring[0], 25) |
1726 HAL_REO_REMAP_IX3(ring[0], 26) |
1727 HAL_REO_REMAP_IX3(ring[0], 27) |
1728 HAL_REO_REMAP_IX3(ring[0], 28) |
1729 HAL_REO_REMAP_IX3(ring[0], 29) |
1730 HAL_REO_REMAP_IX3(ring[0], 30) |
1731 HAL_REO_REMAP_IX3(ring[0], 31);
1732 break;
1733 case 2:
1734 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1735 HAL_REO_REMAP_IX2(ring[0], 17) |
1736 HAL_REO_REMAP_IX2(ring[1], 18) |
1737 HAL_REO_REMAP_IX2(ring[1], 19) |
1738 HAL_REO_REMAP_IX2(ring[0], 20) |
1739 HAL_REO_REMAP_IX2(ring[0], 21) |
1740 HAL_REO_REMAP_IX2(ring[1], 22) |
1741 HAL_REO_REMAP_IX2(ring[1], 23);
1742
1743 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1744 HAL_REO_REMAP_IX3(ring[0], 25) |
1745 HAL_REO_REMAP_IX3(ring[1], 26) |
1746 HAL_REO_REMAP_IX3(ring[1], 27) |
1747 HAL_REO_REMAP_IX3(ring[0], 28) |
1748 HAL_REO_REMAP_IX3(ring[0], 29) |
1749 HAL_REO_REMAP_IX3(ring[1], 30) |
1750 HAL_REO_REMAP_IX3(ring[1], 31);
1751 break;
1752 case 3:
1753 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1754 HAL_REO_REMAP_IX2(ring[1], 17) |
1755 HAL_REO_REMAP_IX2(ring[2], 18) |
1756 HAL_REO_REMAP_IX2(ring[0], 19) |
1757 HAL_REO_REMAP_IX2(ring[1], 20) |
1758 HAL_REO_REMAP_IX2(ring[2], 21) |
1759 HAL_REO_REMAP_IX2(ring[0], 22) |
1760 HAL_REO_REMAP_IX2(ring[1], 23);
1761
1762 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
1763 HAL_REO_REMAP_IX3(ring[0], 25) |
1764 HAL_REO_REMAP_IX3(ring[1], 26) |
1765 HAL_REO_REMAP_IX3(ring[2], 27) |
1766 HAL_REO_REMAP_IX3(ring[0], 28) |
1767 HAL_REO_REMAP_IX3(ring[1], 29) |
1768 HAL_REO_REMAP_IX3(ring[2], 30) |
1769 HAL_REO_REMAP_IX3(ring[0], 31);
1770 break;
1771 case 4:
1772 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1773 HAL_REO_REMAP_IX2(ring[1], 17) |
1774 HAL_REO_REMAP_IX2(ring[2], 18) |
1775 HAL_REO_REMAP_IX2(ring[3], 19) |
1776 HAL_REO_REMAP_IX2(ring[0], 20) |
1777 HAL_REO_REMAP_IX2(ring[1], 21) |
1778 HAL_REO_REMAP_IX2(ring[2], 22) |
1779 HAL_REO_REMAP_IX2(ring[3], 23);
1780
1781 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1782 HAL_REO_REMAP_IX3(ring[1], 25) |
1783 HAL_REO_REMAP_IX3(ring[2], 26) |
1784 HAL_REO_REMAP_IX3(ring[3], 27) |
1785 HAL_REO_REMAP_IX3(ring[0], 28) |
1786 HAL_REO_REMAP_IX3(ring[1], 29) |
1787 HAL_REO_REMAP_IX3(ring[2], 30) |
1788 HAL_REO_REMAP_IX3(ring[3], 31);
1789 break;
1790 }
1791 }
1792
hal_hw_txrx_ops_attach_qcn9000(struct hal_soc * hal_soc)1793 static void hal_hw_txrx_ops_attach_qcn9000(struct hal_soc *hal_soc)
1794 {
1795
1796 /* init and setup */
1797 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1798 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1799 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1800 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
1801 hal_soc->ops->hal_get_window_address = hal_get_window_address_9000;
1802
1803 /* tx */
1804 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
1805 hal_tx_desc_set_dscp_tid_table_id_9000;
1806 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9000;
1807 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9000;
1808 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_9000;
1809 hal_soc->ops->hal_tx_desc_set_buf_addr =
1810 hal_tx_desc_set_buf_addr_generic_li;
1811 hal_soc->ops->hal_tx_desc_set_search_type =
1812 hal_tx_desc_set_search_type_generic_li;
1813 hal_soc->ops->hal_tx_desc_set_search_index =
1814 hal_tx_desc_set_search_index_generic_li;
1815 hal_soc->ops->hal_tx_desc_set_cache_set_num =
1816 hal_tx_desc_set_cache_set_num_generic_li;
1817 hal_soc->ops->hal_tx_comp_get_status =
1818 hal_tx_comp_get_status_generic_li;
1819 hal_soc->ops->hal_tx_comp_get_release_reason =
1820 hal_tx_comp_get_release_reason_generic_li;
1821 hal_soc->ops->hal_get_wbm_internal_error =
1822 hal_get_wbm_internal_error_generic_li;
1823 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_9000;
1824 hal_soc->ops->hal_tx_init_cmd_credit_ring =
1825 hal_tx_init_cmd_credit_ring_9000;
1826
1827 /* rx */
1828 hal_soc->ops->hal_rx_msdu_start_nss_get =
1829 hal_rx_msdu_start_nss_get_9000;
1830 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1831 hal_rx_mon_hw_desc_get_mpdu_status_9000;
1832 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9000;
1833 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1834 hal_rx_proc_phyrx_other_receive_info_tlv_9000;
1835
1836 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9000;
1837 hal_soc->ops->hal_rx_dump_rx_attention_tlv =
1838 hal_rx_dump_rx_attention_tlv_generic_li;
1839 hal_soc->ops->hal_rx_dump_msdu_start_tlv =
1840 hal_rx_dump_msdu_start_tlv_9000;
1841 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1842 hal_rx_dump_mpdu_start_tlv_generic_li;
1843 hal_soc->ops->hal_rx_dump_mpdu_end_tlv =
1844 hal_rx_dump_mpdu_end_tlv_generic_li;
1845 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv =
1846 hal_rx_dump_pkt_hdr_tlv_generic_li;
1847
1848 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9000;
1849 hal_soc->ops->hal_rx_mpdu_start_tid_get =
1850 hal_rx_mpdu_start_tid_get_9000;
1851 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1852 hal_rx_msdu_start_reception_type_get_9000;
1853 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1854 hal_rx_msdu_end_da_idx_get_9000;
1855 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1856 hal_rx_msdu_desc_info_get_ptr_9000;
1857 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1858 hal_rx_link_desc_msdu0_ptr_9000;
1859 hal_soc->ops->hal_reo_status_get_header =
1860 hal_reo_status_get_header_9000;
1861 hal_soc->ops->hal_rx_status_get_tlv_info =
1862 hal_rx_status_get_tlv_info_generic_li;
1863 hal_soc->ops->hal_rx_wbm_err_info_get =
1864 hal_rx_wbm_err_info_get_generic_li;
1865
1866 hal_soc->ops->hal_tx_set_pcp_tid_map =
1867 hal_tx_set_pcp_tid_map_generic_li;
1868 hal_soc->ops->hal_tx_update_pcp_tid_map =
1869 hal_tx_update_pcp_tid_generic_li;
1870 hal_soc->ops->hal_tx_set_tidmap_prty =
1871 hal_tx_update_tidmap_prty_generic_li;
1872 hal_soc->ops->hal_rx_get_rx_fragment_number =
1873 hal_rx_get_rx_fragment_number_9000;
1874 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1875 hal_rx_msdu_end_da_is_mcbc_get_9000;
1876 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1877 hal_rx_msdu_end_sa_is_valid_get_9000;
1878 hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
1879 hal_rx_msdu_end_sa_idx_get_9000;
1880 hal_soc->ops->hal_rx_desc_is_first_msdu =
1881 hal_rx_desc_is_first_msdu_9000;
1882 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1883 hal_rx_msdu_end_l3_hdr_padding_get_9000;
1884 hal_soc->ops->hal_rx_encryption_info_valid =
1885 hal_rx_encryption_info_valid_9000;
1886 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_9000;
1887 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1888 hal_rx_msdu_end_first_msdu_get_9000;
1889 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1890 hal_rx_msdu_end_da_is_valid_get_9000;
1891 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1892 hal_rx_msdu_end_last_msdu_get_9000;
1893 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1894 hal_rx_get_mpdu_mac_ad4_valid_9000;
1895 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1896 hal_rx_mpdu_start_sw_peer_id_get_9000;
1897 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1898 hal_rx_mpdu_peer_meta_data_get_li;
1899 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_9000;
1900 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_9000;
1901 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1902 hal_rx_get_mpdu_frame_control_valid_9000;
1903 hal_soc->ops->hal_rx_get_frame_ctrl_field =
1904 hal_rx_get_mpdu_frame_control_field_9000;
1905 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_9000;
1906 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_9000;
1907 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_9000;
1908 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_9000;
1909 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1910 hal_rx_get_mpdu_sequence_control_valid_9000;
1911 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_9000;
1912 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_9000;
1913 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1914 hal_rx_hw_desc_get_ppduid_get_9000;
1915 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1916 hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000;
1917 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1918 hal_rx_msdu_end_sa_sw_peer_id_get_9000;
1919 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1920 hal_rx_msdu0_buffer_addr_lsb_9000;
1921 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1922 hal_rx_msdu_desc_info_ptr_get_9000;
1923 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9000;
1924 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9000;
1925 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_9000;
1926 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_9000;
1927 hal_soc->ops->hal_rx_get_mac_addr2_valid =
1928 hal_rx_get_mac_addr2_valid_9000;
1929 hal_soc->ops->hal_rx_get_filter_category =
1930 hal_rx_get_filter_category_9000;
1931 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_9000;
1932 hal_soc->ops->hal_reo_config = hal_reo_config_9000;
1933 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_9000;
1934 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1935 hal_rx_msdu_flow_idx_invalid_9000;
1936 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1937 hal_rx_msdu_flow_idx_timeout_9000;
1938 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1939 hal_rx_msdu_fse_metadata_get_9000;
1940 hal_soc->ops->hal_rx_msdu_cce_match_get =
1941 hal_rx_msdu_cce_match_get_li;
1942 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1943 hal_rx_msdu_cce_metadata_get_9000;
1944 hal_soc->ops->hal_rx_msdu_get_flow_params =
1945 hal_rx_msdu_get_flow_params_9000;
1946 hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
1947 hal_rx_tlv_get_tcp_chksum_9000;
1948 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_9000;
1949 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
1950 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9000;
1951 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9000;
1952 #endif
1953 /* rx - msdu fast path info fields */
1954 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1955 hal_rx_msdu_packet_metadata_get_9000;
1956 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1957 hal_rx_mpdu_start_tlv_tag_valid_9000;
1958 hal_soc->ops->hal_rx_sw_mon_desc_info_get =
1959 hal_rx_sw_mon_desc_info_get_9000;
1960 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
1961 hal_rx_wbm_err_msdu_continuation_get_9000;
1962
1963 /* rx - TLV struct offsets */
1964 hal_soc->ops->hal_rx_msdu_end_offset_get =
1965 hal_rx_msdu_end_offset_get_generic;
1966 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
1967 hal_soc->ops->hal_rx_msdu_start_offset_get =
1968 hal_rx_msdu_start_offset_get_generic;
1969 hal_soc->ops->hal_rx_mpdu_start_offset_get =
1970 hal_rx_mpdu_start_offset_get_generic;
1971 hal_soc->ops->hal_rx_mpdu_end_offset_get =
1972 hal_rx_mpdu_end_offset_get_generic;
1973 #ifndef NO_RX_PKT_HDR_TLV
1974 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1975 hal_rx_pkt_tlv_offset_get_generic;
1976 #endif
1977 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9000;
1978
1979 hal_soc->ops->hal_rx_flow_get_tuple_info =
1980 hal_rx_flow_get_tuple_info_li;
1981 hal_soc->ops->hal_rx_flow_delete_entry =
1982 hal_rx_flow_delete_entry_li;
1983 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li;
1984 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1985 hal_compute_reo_remap_ix2_ix3_9000;
1986 hal_soc->ops->hal_setup_link_idle_list =
1987 hal_setup_link_idle_list_generic_li;
1988 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li;
1989 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li;
1990 hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1991 hal_rx_tlv_decrypt_err_get_li;
1992 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
1993 hal_rx_tlv_get_pkt_capture_flags_li;
1994 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1995 hal_rx_mpdu_info_ampdu_flag_get_li;
1996 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
1997 hal_soc->ops->hal_rx_tlv_msdu_len_get =
1998 hal_rx_msdu_start_get_len_9000;
1999 };
2000
2001 struct hal_hw_srng_config hw_srng_table_9000[] = {
2002 /* TODO: max_rings can populated by querying HW capabilities */
2003 { /* REO_DST */
2004 .start_ring_id = HAL_SRNG_REO2SW1,
2005 .max_rings = 4,
2006 .entry_size = sizeof(struct reo_destination_ring) >> 2,
2007 .lmac_ring = FALSE,
2008 .ring_dir = HAL_SRNG_DST_RING,
2009 .reg_start = {
2010 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
2011 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2012 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
2013 SEQ_WCSS_UMAC_REO_REG_OFFSET)
2014 },
2015 .reg_size = {
2016 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
2017 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
2018 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
2019 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
2020 },
2021 .max_size =
2022 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
2023 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
2024 },
2025 { /* REO_EXCEPTION */
2026 /* Designating REO2TCL ring as exception ring. This ring is
2027 * similar to other REO2SW rings though it is named as REO2TCL.
2028 * Any of theREO2SW rings can be used as exception ring.
2029 */
2030 .start_ring_id = HAL_SRNG_REO2TCL,
2031 .max_rings = 1,
2032 .entry_size = sizeof(struct reo_destination_ring) >> 2,
2033 .lmac_ring = FALSE,
2034 .ring_dir = HAL_SRNG_DST_RING,
2035 .reg_start = {
2036 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
2037 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2038 HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
2039 SEQ_WCSS_UMAC_REO_REG_OFFSET)
2040 },
2041 /* Single ring - provide ring size if multiple rings of this
2042 * type are supported
2043 */
2044 .reg_size = {},
2045 .max_size =
2046 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
2047 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
2048 },
2049 { /* REO_REINJECT */
2050 .start_ring_id = HAL_SRNG_SW2REO,
2051 .max_rings = 1,
2052 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2053 .lmac_ring = FALSE,
2054 .ring_dir = HAL_SRNG_SRC_RING,
2055 .reg_start = {
2056 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
2057 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2058 HWIO_REO_R2_SW2REO_RING_HP_ADDR(
2059 SEQ_WCSS_UMAC_REO_REG_OFFSET)
2060 },
2061 /* Single ring - provide ring size if multiple rings of this
2062 * type are supported
2063 */
2064 .reg_size = {},
2065 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
2066 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
2067 },
2068 { /* REO_CMD */
2069 .start_ring_id = HAL_SRNG_REO_CMD,
2070 .max_rings = 1,
2071 .entry_size = (sizeof(struct tlv_32_hdr) +
2072 sizeof(struct reo_get_queue_stats)) >> 2,
2073 .lmac_ring = FALSE,
2074 .ring_dir = HAL_SRNG_SRC_RING,
2075 .reg_start = {
2076 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
2077 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2078 HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
2079 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2080 },
2081 /* Single ring - provide ring size if multiple rings of this
2082 * type are supported
2083 */
2084 .reg_size = {},
2085 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
2086 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
2087 },
2088 { /* REO_STATUS */
2089 .start_ring_id = HAL_SRNG_REO_STATUS,
2090 .max_rings = 1,
2091 .entry_size = (sizeof(struct tlv_32_hdr) +
2092 sizeof(struct reo_get_queue_stats_status)) >> 2,
2093 .lmac_ring = FALSE,
2094 .ring_dir = HAL_SRNG_DST_RING,
2095 .reg_start = {
2096 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
2097 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2098 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
2099 SEQ_WCSS_UMAC_REO_REG_OFFSET),
2100 },
2101 /* Single ring - provide ring size if multiple rings of this
2102 * type are supported
2103 */
2104 .reg_size = {},
2105 .max_size =
2106 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
2107 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
2108 },
2109 { /* TCL_DATA */
2110 .start_ring_id = HAL_SRNG_SW2TCL1,
2111 .max_rings = 3,
2112 .entry_size = (sizeof(struct tlv_32_hdr) +
2113 sizeof(struct tcl_data_cmd)) >> 2,
2114 .lmac_ring = FALSE,
2115 .ring_dir = HAL_SRNG_SRC_RING,
2116 .reg_start = {
2117 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
2118 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2119 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
2120 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2121 },
2122 .reg_size = {
2123 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
2124 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
2125 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
2126 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
2127 },
2128 .max_size =
2129 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
2130 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
2131 },
2132 { /* TCL_CMD/CREDIT */
2133 /* qca8074v2 and qcn9000 uses this ring for data commands */
2134 .start_ring_id = HAL_SRNG_SW2TCL_CMD,
2135 .max_rings = 1,
2136 .entry_size = (sizeof(struct tlv_32_hdr) +
2137 sizeof(struct tcl_data_cmd)) >> 2,
2138 .lmac_ring = FALSE,
2139 .ring_dir = HAL_SRNG_SRC_RING,
2140 .reg_start = {
2141 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
2142 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2143 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
2144 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2145 },
2146 /* Single ring - provide ring size if multiple rings of this
2147 * type are supported
2148 */
2149 .reg_size = {},
2150 .max_size =
2151 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
2152 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
2153 },
2154 { /* TCL_STATUS */
2155 .start_ring_id = HAL_SRNG_TCL_STATUS,
2156 .max_rings = 1,
2157 .entry_size = (sizeof(struct tlv_32_hdr) +
2158 sizeof(struct tcl_status_ring)) >> 2,
2159 .lmac_ring = FALSE,
2160 .ring_dir = HAL_SRNG_DST_RING,
2161 .reg_start = {
2162 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
2163 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2164 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
2165 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
2166 },
2167 /* Single ring - provide ring size if multiple rings of this
2168 * type are supported
2169 */
2170 .reg_size = {},
2171 .max_size =
2172 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
2173 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
2174 },
2175 { /* CE_SRC */
2176 .start_ring_id = HAL_SRNG_CE_0_SRC,
2177 .max_rings = 12,
2178 .entry_size = sizeof(struct ce_src_desc) >> 2,
2179 .lmac_ring = FALSE,
2180 .ring_dir = HAL_SRNG_SRC_RING,
2181 .reg_start = {
2182 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
2183 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
2184 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
2185 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
2186 },
2187 .reg_size = {
2188 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
2189 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
2190 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
2191 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
2192 },
2193 .max_size =
2194 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
2195 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
2196 },
2197 { /* CE_DST */
2198 .start_ring_id = HAL_SRNG_CE_0_DST,
2199 .max_rings = 12,
2200 .entry_size = 8 >> 2,
2201 /*TODO: entry_size above should actually be
2202 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
2203 * of struct ce_dst_desc in HW header files
2204 */
2205 .lmac_ring = FALSE,
2206 .ring_dir = HAL_SRNG_SRC_RING,
2207 .reg_start = {
2208 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
2209 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
2210 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
2211 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
2212 },
2213 .reg_size = {
2214 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
2215 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
2216 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
2217 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
2218 },
2219 .max_size =
2220 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
2221 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
2222 },
2223 { /* CE_DST_STATUS */
2224 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
2225 .max_rings = 12,
2226 .entry_size = sizeof(struct ce_stat_desc) >> 2,
2227 .lmac_ring = FALSE,
2228 .ring_dir = HAL_SRNG_DST_RING,
2229 .reg_start = {
2230 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
2231 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
2232 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
2233 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
2234 },
2235 /* TODO: check destination status ring registers */
2236 .reg_size = {
2237 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
2238 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
2239 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
2240 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
2241 },
2242 .max_size =
2243 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
2244 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
2245 },
2246 { /* WBM_IDLE_LINK */
2247 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
2248 .max_rings = 1,
2249 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
2250 .lmac_ring = FALSE,
2251 .ring_dir = HAL_SRNG_SRC_RING,
2252 .reg_start = {
2253 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2254 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2255 },
2256 /* Single ring - provide ring size if multiple rings of this
2257 * type are supported
2258 */
2259 .reg_size = {},
2260 .max_size =
2261 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
2262 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
2263 },
2264 { /* SW2WBM_RELEASE */
2265 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
2266 .max_rings = 1,
2267 .entry_size = sizeof(struct wbm_release_ring) >> 2,
2268 .lmac_ring = FALSE,
2269 .ring_dir = HAL_SRNG_SRC_RING,
2270 .reg_start = {
2271 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2272 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2273 },
2274 /* Single ring - provide ring size if multiple rings of this
2275 * type are supported
2276 */
2277 .reg_size = {},
2278 .max_size =
2279 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2280 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2281 },
2282 { /* WBM2SW_RELEASE */
2283 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
2284 .max_rings = 5,
2285 .entry_size = sizeof(struct wbm_release_ring) >> 2,
2286 .lmac_ring = FALSE,
2287 .ring_dir = HAL_SRNG_DST_RING,
2288 .reg_start = {
2289 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2290 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2291 },
2292 .reg_size = {
2293 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
2294 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2295 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
2296 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
2297 },
2298 .max_size =
2299 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
2300 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
2301 },
2302 { /* RXDMA_BUF */
2303 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
2304 #ifdef IPA_OFFLOAD
2305 #ifdef IPA_WDI3_VLAN_SUPPORT
2306 .max_rings = 4,
2307 #else
2308 .max_rings = 3,
2309 #endif
2310 #else
2311 .max_rings = 2,
2312 #endif
2313 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2314 .lmac_ring = TRUE,
2315 .ring_dir = HAL_SRNG_SRC_RING,
2316 /* reg_start is not set because LMAC rings are not accessed
2317 * from host
2318 */
2319 .reg_start = {},
2320 .reg_size = {},
2321 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2322 },
2323 { /* RXDMA_DST */
2324 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
2325 .max_rings = 1,
2326 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2327 .lmac_ring = TRUE,
2328 .ring_dir = HAL_SRNG_DST_RING,
2329 /* reg_start is not set because LMAC rings are not accessed
2330 * from host
2331 */
2332 .reg_start = {},
2333 .reg_size = {},
2334 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2335 },
2336 { /* RXDMA_MONITOR_BUF */
2337 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
2338 .max_rings = 1,
2339 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2340 .lmac_ring = TRUE,
2341 .ring_dir = HAL_SRNG_SRC_RING,
2342 /* reg_start is not set because LMAC rings are not accessed
2343 * from host
2344 */
2345 .reg_start = {},
2346 .reg_size = {},
2347 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2348 },
2349 { /* RXDMA_MONITOR_STATUS */
2350 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
2351 .max_rings = 1,
2352 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2353 .lmac_ring = TRUE,
2354 .ring_dir = HAL_SRNG_SRC_RING,
2355 /* reg_start is not set because LMAC rings are not accessed
2356 * from host
2357 */
2358 .reg_start = {},
2359 .reg_size = {},
2360 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2361 },
2362 { /* RXDMA_MONITOR_DST */
2363 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
2364 .max_rings = 1,
2365 .entry_size = sizeof(struct sw_monitor_ring) >> 2,
2366 .lmac_ring = TRUE,
2367 .ring_dir = HAL_SRNG_DST_RING,
2368 /* reg_start is not set because LMAC rings are not accessed
2369 * from host
2370 */
2371 .reg_start = {},
2372 .reg_size = {},
2373 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2374 },
2375 { /* RXDMA_MONITOR_DESC */
2376 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
2377 .max_rings = 1,
2378 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
2379 .lmac_ring = TRUE,
2380 .ring_dir = HAL_SRNG_SRC_RING,
2381 /* reg_start is not set because LMAC rings are not accessed
2382 * from host
2383 */
2384 .reg_start = {},
2385 .reg_size = {},
2386 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2387 },
2388 { /* DIR_BUF_RX_DMA_SRC */
2389 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
2390 /* one ring for spectral and one ring for cfr */
2391 .max_rings = 2,
2392 .entry_size = 2,
2393 .lmac_ring = TRUE,
2394 .ring_dir = HAL_SRNG_SRC_RING,
2395 /* reg_start is not set because LMAC rings are not accessed
2396 * from host
2397 */
2398 .reg_start = {},
2399 .reg_size = {},
2400 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2401 },
2402 #ifdef WLAN_FEATURE_CIF_CFR
2403 { /* WIFI_POS_SRC */
2404 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
2405 .max_rings = 1,
2406 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
2407 .lmac_ring = TRUE,
2408 .ring_dir = HAL_SRNG_SRC_RING,
2409 /* reg_start is not set because LMAC rings are not accessed
2410 * from host
2411 */
2412 .reg_start = {},
2413 .reg_size = {},
2414 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2415 },
2416 #endif
2417 { /* REO2PPE */ 0},
2418 { /* PPE2TCL */ 0},
2419 { /* PPE_RELEASE */ 0},
2420 { /* TX_MONITOR_BUF */ 0},
2421 { /* TX_MONITOR_DST */ 0},
2422 { /* SW2RXDMA_NEW */ 0},
2423 { /* SW2RXDMA_LINK_RELEASE */ 0},
2424 };
2425
2426 /**
2427 * hal_qcn9000_attach()- Attach 9000 target specific hal_soc ops, offset and
2428 * srng table
2429 * @hal_soc: HAL SoC context
2430 *
2431 * Return: void
2432 */
hal_qcn9000_attach(struct hal_soc * hal_soc)2433 void hal_qcn9000_attach(struct hal_soc *hal_soc)
2434 {
2435 hal_soc->hw_srng_table = hw_srng_table_9000;
2436 hal_srng_hw_reg_offset_init_generic(hal_soc);
2437 hal_hw_txrx_default_ops_attach_li(hal_soc);
2438 hal_hw_txrx_ops_attach_qcn9000(hal_soc);
2439 if (hal_soc->static_window_map)
2440 hal_write_window_register(hal_soc);
2441 }
2442