1 /*
2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "hal_hw_headers.h"
20 #include "hal_internal.h"
21 #include "cdp_txrx_mon_struct.h"
22 #include "qdf_trace.h"
23 #include "hal_li_rx.h"
24 #include "hal_tx.h"
25 #include "dp_types.h"
26 #include "hal_api_mon.h"
27 #if (!defined(QCA_WIFI_QCA6018)) && (!defined(QCA_WIFI_QCA9574))
28 #include "phyrx_other_receive_info_su_evm_details.h"
29 #endif
30
31 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
32 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
33 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
34 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
35 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
36
37 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
38 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
39 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
40 RX_MSDU_END_5_DA_IS_MCBC_MASK, \
41 RX_MSDU_END_5_DA_IS_MCBC_LSB))
42
43 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
44 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
45 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \
46 RX_MSDU_END_5_SA_IS_VALID_MASK, \
47 RX_MSDU_END_5_SA_IS_VALID_LSB))
48
49 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
50 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
51 RX_MSDU_END_13_SA_IDX_OFFSET)), \
52 RX_MSDU_END_13_SA_IDX_MASK, \
53 RX_MSDU_END_13_SA_IDX_LSB))
54
55 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
56 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
57 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
58 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
59 RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
60
61 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
62 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
63 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
64 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \
65 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB))
66
67 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
68 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
69 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \
70 RX_MPDU_INFO_4_PN_31_0_MASK, \
71 RX_MPDU_INFO_4_PN_31_0_LSB))
72
73 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
74 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
75 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \
76 RX_MPDU_INFO_5_PN_63_32_MASK, \
77 RX_MPDU_INFO_5_PN_63_32_LSB))
78
79 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
80 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
81 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \
82 RX_MPDU_INFO_6_PN_95_64_MASK, \
83 RX_MPDU_INFO_6_PN_95_64_LSB))
84
85 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
86 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
87 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \
88 RX_MPDU_INFO_7_PN_127_96_MASK, \
89 RX_MPDU_INFO_7_PN_127_96_LSB))
90
91 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
92 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
93 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \
94 RX_MSDU_END_5_FIRST_MSDU_MASK, \
95 RX_MSDU_END_5_FIRST_MSDU_LSB))
96
97 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
98 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
99 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
100 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
101 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
102
103 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
104 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
105 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \
106 RX_MSDU_END_5_DA_IS_VALID_MASK, \
107 RX_MSDU_END_5_DA_IS_VALID_LSB))
108
109 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \
110 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
111 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \
112 RX_MSDU_END_5_LAST_MSDU_MASK, \
113 RX_MSDU_END_5_LAST_MSDU_LSB))
114
115 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \
116 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
117 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
118 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
119 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
120
121 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
122 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
123 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \
124 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \
125 RX_MPDU_INFO_1_SW_PEER_ID_LSB))
126
127 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
128 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
129 RX_MPDU_INFO_2_TO_DS_OFFSET)), \
130 RX_MPDU_INFO_2_TO_DS_MASK, \
131 RX_MPDU_INFO_2_TO_DS_LSB))
132
133 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
134 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
135 RX_MPDU_INFO_2_FR_DS_OFFSET)), \
136 RX_MPDU_INFO_2_FR_DS_MASK, \
137 RX_MPDU_INFO_2_FR_DS_LSB))
138
139 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \
140 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
141 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \
142 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \
143 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB))
144
145 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
146 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
147 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \
148 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \
149 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB))
150
151 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \
152 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
153 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
154 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \
155 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
156
157 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \
158 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
159 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
160 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \
161 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
162
163 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
164 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
165 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \
166 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \
167 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB))
168
169 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \
170 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
171 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
172 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \
173 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
174
175 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \
176 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
177 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
178 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \
179 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
180
181 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \
182 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
183 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \
184 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \
185 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB))
186
187 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \
188 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
189 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \
190 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \
191 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB))
192
193 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \
194 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
195 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \
196 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \
197 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB))
198
199 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
200 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
201 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
202 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
203 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
204
205 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
206 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
207 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
208 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
209 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
210
211 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
212 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
213 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
214 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
215 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
216
217 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \
218 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
219 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
220 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
221 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB))
222
223 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
224 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
225 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \
226 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \
227 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB))
228
229 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \
230 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
231 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \
232 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
233 RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
234
235 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
236 (uint8_t *)(link_desc_va) + \
237 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
238
239 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
240 (uint8_t *)(msdu0) + \
241 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
242
243 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
244 (uint8_t *)(ent_ring_desc) + \
245 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
246
247 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
248 (uint8_t *)(dst_ring_desc) + \
249 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
250
251 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \
252 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID)
253
254 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \
255 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS)
256
257 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
258 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID)
259
260 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \
261 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID)
262
263 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \
264 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY)
265
266 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \
267 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID)
268
269 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
270 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID)
271
272 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \
273 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_1, SW_PEER_ID)
274
275 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
276 do { \
277 reg_val &= \
278 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\
279 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \
280 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
281 reg_val |= \
282 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
283 FRAGMENT_DEST_RING, \
284 (reo_params)->frag_dst_ring) | \
285 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
286 AGING_LIST_ENABLE, 1) |\
287 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
288 AGING_FLUSH_ENABLE, 1);\
289 HAL_REG_WRITE((soc), \
290 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
291 SEQ_WCSS_UMAC_REO_REG_OFFSET), \
292 (reg_val)); \
293 (reg_val) = \
294 HAL_REG_READ((soc), \
295 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \
296 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \
297 (reg_val) &= \
298 ~(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK); \
299 (reg_val) |= \
300 HAL_SM(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0, \
301 DEST_RING_ALT_MAPPING_0, \
302 (reo_params)->alt_dst_ind_0); \
303 HAL_REG_WRITE((soc), \
304 HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR( \
305 SEQ_WCSS_UMAC_REO_REG_OFFSET), \
306 (reg_val)); \
307 } while (0)
308
309 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
310 ((struct rx_msdu_desc_info *) \
311 _OFFSET_TO_BYTE_PTR((msdu_details_ptr), \
312 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
313
314 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
315 ((struct rx_msdu_details *) \
316 _OFFSET_TO_BYTE_PTR((link_desc),\
317 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET))
318
319 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \
320 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
321 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \
322 RX_MSDU_END_14_FLOW_IDX_MASK, \
323 RX_MSDU_END_14_FLOW_IDX_LSB))
324
325 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \
326 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
327 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \
328 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \
329 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB))
330
331 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
332 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
333 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \
334 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \
335 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB))
336
337 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \
338 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
339 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \
340 RX_MSDU_END_15_FSE_METADATA_MASK, \
341 RX_MSDU_END_15_FSE_METADATA_LSB))
342
343 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \
344 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
345 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \
346 RX_MSDU_END_16_CCE_METADATA_MASK, \
347 RX_MSDU_END_16_CCE_METADATA_LSB))
348
349 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \
350 (_HAL_MS( \
351 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
352 msdu_end_tlv.rx_msdu_end), \
353 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \
354 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \
355 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB))
356
357 /**
358 * hal_rx_msdu_start_nss_get_8074v2() - API to get the NSS Interval from
359 * rx_msdu_start
360 * @buf: pointer to the start of RX PKT TLV header
361 *
362 * Return: uint32_t(nss)
363 */
hal_rx_msdu_start_nss_get_8074v2(uint8_t * buf)364 static uint32_t hal_rx_msdu_start_nss_get_8074v2(uint8_t *buf)
365 {
366 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
367 struct rx_msdu_start *msdu_start =
368 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
369 uint8_t mimo_ss_bitmap;
370
371 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
372
373 return qdf_get_hweight8(mimo_ss_bitmap);
374 }
375
376 /**
377 * hal_rx_mon_hw_desc_get_mpdu_status_8074v2() - Retrieve MPDU status
378 * @hw_desc_addr: Start address of Rx HW TLVs
379 * @rs: Status for monitor mode
380 *
381 * Return: void
382 */
hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void * hw_desc_addr,struct mon_rx_status * rs)383 static void hal_rx_mon_hw_desc_get_mpdu_status_8074v2(void *hw_desc_addr,
384 struct mon_rx_status *rs)
385 {
386 struct rx_msdu_start *rx_msdu_start;
387 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
388 uint32_t reg_value;
389 const uint32_t sgi_hw_to_cdp[] = {
390 CDP_SGI_0_8_US,
391 CDP_SGI_0_4_US,
392 CDP_SGI_1_6_US,
393 CDP_SGI_3_2_US,
394 };
395
396 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
397
398 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
399
400 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
401 RX_MSDU_START_5, USER_RSSI);
402 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
403
404 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
405 rs->sgi = sgi_hw_to_cdp[reg_value];
406 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
407 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
408 /* TODO: rs->beamformed should be set for SU beamforming also */
409 }
410
411 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
hal_get_link_desc_size_8074v2(void)412 static uint32_t hal_get_link_desc_size_8074v2(void)
413 {
414 return LINK_DESC_SIZE;
415 }
416
417 /**
418 * hal_rx_get_tlv_8074v2() - API to get the tlv
419 * @rx_tlv: TLV data extracted from the rx packet
420 *
421 * Return: uint8_t
422 */
hal_rx_get_tlv_8074v2(void * rx_tlv)423 static uint8_t hal_rx_get_tlv_8074v2(void *rx_tlv)
424 {
425 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
426 }
427
428 #if (!defined(QCA_WIFI_QCA6018)) && (!defined(QCA_WIFI_QCA9574))
429 #define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \
430 (ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \
431 PHYRX_OTHER_RECEIVE_INFO, \
432 SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM)
433
434 static inline void
hal_rx_update_su_evm_info(void * rx_tlv,void * ppdu_info_hdl)435 hal_rx_update_su_evm_info(void *rx_tlv,
436 void *ppdu_info_hdl)
437 {
438 struct hal_rx_ppdu_info *ppdu_info =
439 (struct hal_rx_ppdu_info *)ppdu_info_hdl;
440
441 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0);
442 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1);
443 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2);
444 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3);
445 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4);
446 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5);
447 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6);
448 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7);
449 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8);
450 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9);
451 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10);
452 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11);
453 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12);
454 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13);
455 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14);
456 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15);
457 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16);
458 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17);
459 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18);
460 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19);
461 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20);
462 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21);
463 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22);
464 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23);
465 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24);
466 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25);
467 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26);
468 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27);
469 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28);
470 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29);
471 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30);
472 HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31);
473 }
474 /**
475 * hal_rx_proc_phyrx_other_receive_info_tlv_8074v2()
476 * - process other receive info TLV
477 * @rx_tlv_hdr: pointer to TLV header
478 * @ppdu_info_hdl: pointer to ppdu_info
479 *
480 * Return: None
481 */
482 static
hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void * rx_tlv_hdr,void * ppdu_info_hdl)483 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr,
484 void *ppdu_info_hdl)
485 {
486 uint16_t tlv_tag;
487 void *rx_tlv;
488 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
489
490 /* Skip TLV_HDR for OTHER_RECEIVE_INFO and follows the
491 * embedded TLVs inside
492 */
493 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
494 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
495
496 switch (tlv_tag) {
497 case WIFIPHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_E:
498
499 /* Skip TLV length to get TLV content */
500 rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV32_HDR_SIZE;
501
502 ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv,
503 PHYRX_OTHER_RECEIVE_INFO,
504 SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS);
505 ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv,
506 PHYRX_OTHER_RECEIVE_INFO,
507 SU_EVM_DETAILS_0_PILOT_COUNT);
508 ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv,
509 PHYRX_OTHER_RECEIVE_INFO,
510 SU_EVM_DETAILS_0_NSS_COUNT);
511 hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl);
512 break;
513 }
514 }
515 #else
516 static inline
hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void * rx_tlv_hdr,void * ppdu_info_hdl)517 void hal_rx_proc_phyrx_other_receive_info_tlv_8074v2(void *rx_tlv_hdr,
518 void *ppdu_info_hdl)
519 {
520 }
521 #endif
522
523 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \
524 defined(WLAN_ENH_CFR_ENABLE)
525 static inline
hal_rx_get_bb_info_8074v2(void * rx_tlv,void * ppdu_info_hdl)526 void hal_rx_get_bb_info_8074v2(void *rx_tlv,
527 void *ppdu_info_hdl)
528 {
529 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
530
531 ppdu_info->cfr_info.bb_captured_channel =
532 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL);
533
534 ppdu_info->cfr_info.bb_captured_timeout =
535 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT);
536
537 ppdu_info->cfr_info.bb_captured_reason =
538 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON);
539 }
540
541 static inline
hal_rx_get_rtt_info_8074v2(void * rx_tlv,void * ppdu_info_hdl)542 void hal_rx_get_rtt_info_8074v2(void *rx_tlv,
543 void *ppdu_info_hdl)
544 {
545 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
546
547 ppdu_info->cfr_info.rx_location_info_valid =
548 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS,
549 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID);
550
551 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
552 HAL_RX_GET(rx_tlv,
553 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
554 RTT_CHE_BUFFER_POINTER_LOW32);
555
556 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
557 HAL_RX_GET(rx_tlv,
558 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
559 RTT_CHE_BUFFER_POINTER_HIGH8);
560
561 ppdu_info->cfr_info.chan_capture_status =
562 HAL_RX_GET(rx_tlv,
563 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
564 RESERVED_8);
565
566 ppdu_info->cfr_info.rx_start_ts =
567 HAL_RX_GET(rx_tlv,
568 PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
569 RX_START_TS);
570
571 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
572 HAL_RX_GET(rx_tlv,
573 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
574 RTT_CFO_MEASUREMENT);
575
576 ppdu_info->cfr_info.agc_gain_info0 =
577 HAL_RX_GET(rx_tlv,
578 PHYRX_PKT_END_1_RX_PKT_END_DETAILS,
579 PHY_TIMESTAMP_1_LOWER_32);
580
581 ppdu_info->cfr_info.agc_gain_info1 =
582 HAL_RX_GET(rx_tlv,
583 PHYRX_PKT_END_2_RX_PKT_END_DETAILS,
584 PHY_TIMESTAMP_1_UPPER_32);
585
586 ppdu_info->cfr_info.agc_gain_info2 =
587 HAL_RX_GET(rx_tlv,
588 PHYRX_PKT_END_3_RX_PKT_END_DETAILS,
589 PHY_TIMESTAMP_2_LOWER_32);
590
591 ppdu_info->cfr_info.agc_gain_info3 =
592 HAL_RX_GET(rx_tlv,
593 PHYRX_PKT_END_4_RX_PKT_END_DETAILS,
594 PHY_TIMESTAMP_2_UPPER_32);
595
596 ppdu_info->cfr_info.mcs_rate =
597 HAL_RX_GET(rx_tlv,
598 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
599 RTT_MCS_RATE);
600
601 ppdu_info->cfr_info.gi_type =
602 HAL_RX_GET(rx_tlv,
603 PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
604 RTT_GI_TYPE);
605 }
606 #endif
607
608 /**
609 * hal_rx_dump_msdu_start_tlv_8074v2() - dump RX msdu_start TLV in structured
610 * human readable format.
611 * @pkttlvs: pointer to the pkttlvs.
612 * @dbg_level: log level.
613 *
614 * Return: void
615 */
hal_rx_dump_msdu_start_tlv_8074v2(void * pkttlvs,uint8_t dbg_level)616 static void hal_rx_dump_msdu_start_tlv_8074v2(void *pkttlvs,
617 uint8_t dbg_level)
618 {
619 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
620 struct rx_msdu_start *msdu_start =
621 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
622
623 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
624 "rx_msdu_start tlv - "
625 "rxpcu_mpdu_filter_in_category: %d "
626 "sw_frame_group_id: %d "
627 "phy_ppdu_id: %d "
628 "msdu_length: %d "
629 "ipsec_esp: %d "
630 "l3_offset: %d "
631 "ipsec_ah: %d "
632 "l4_offset: %d "
633 "msdu_number: %d "
634 "decap_format: %d "
635 "ipv4_proto: %d "
636 "ipv6_proto: %d "
637 "tcp_proto: %d "
638 "udp_proto: %d "
639 "ip_frag: %d "
640 "tcp_only_ack: %d "
641 "da_is_bcast_mcast: %d "
642 "ip4_protocol_ip6_next_header: %d "
643 "toeplitz_hash_2_or_4: %d "
644 "flow_id_toeplitz: %d "
645 "user_rssi: %d "
646 "pkt_type: %d "
647 "stbc: %d "
648 "sgi: %d "
649 "rate_mcs: %d "
650 "receive_bandwidth: %d "
651 "reception_type: %d "
652 "ppdu_start_timestamp: %d "
653 "sw_phy_meta_data: %d ",
654 msdu_start->rxpcu_mpdu_filter_in_category,
655 msdu_start->sw_frame_group_id,
656 msdu_start->phy_ppdu_id,
657 msdu_start->msdu_length,
658 msdu_start->ipsec_esp,
659 msdu_start->l3_offset,
660 msdu_start->ipsec_ah,
661 msdu_start->l4_offset,
662 msdu_start->msdu_number,
663 msdu_start->decap_format,
664 msdu_start->ipv4_proto,
665 msdu_start->ipv6_proto,
666 msdu_start->tcp_proto,
667 msdu_start->udp_proto,
668 msdu_start->ip_frag,
669 msdu_start->tcp_only_ack,
670 msdu_start->da_is_bcast_mcast,
671 msdu_start->ip4_protocol_ip6_next_header,
672 msdu_start->toeplitz_hash_2_or_4,
673 msdu_start->flow_id_toeplitz,
674 msdu_start->user_rssi,
675 msdu_start->pkt_type,
676 msdu_start->stbc,
677 msdu_start->sgi,
678 msdu_start->rate_mcs,
679 msdu_start->receive_bandwidth,
680 msdu_start->reception_type,
681 msdu_start->ppdu_start_timestamp,
682 msdu_start->sw_phy_meta_data);
683 }
684
685 /**
686 * hal_rx_dump_msdu_end_tlv_8074v2() - dump RX msdu_end TLV in structured
687 * human readable format.
688 * @pkttlvs: pointer to the pkttlvs.
689 * @dbg_level: log level.
690 *
691 * Return: void
692 */
hal_rx_dump_msdu_end_tlv_8074v2(void * pkttlvs,uint8_t dbg_level)693 static void hal_rx_dump_msdu_end_tlv_8074v2(void *pkttlvs,
694 uint8_t dbg_level)
695 {
696 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
697 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
698
699 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
700 "rx_msdu_end tlv - "
701 "rxpcu_mpdu_filter_in_category: %d "
702 "sw_frame_group_id: %d "
703 "phy_ppdu_id: %d "
704 "ip_hdr_chksum: %d "
705 "tcp_udp_chksum: %d "
706 "key_id_octet: %d "
707 "cce_super_rule: %d "
708 "cce_classify_not_done_truncat: %d "
709 "cce_classify_not_done_cce_dis: %d "
710 "ext_wapi_pn_63_48: %d "
711 "ext_wapi_pn_95_64: %d "
712 "ext_wapi_pn_127_96: %d "
713 "reported_mpdu_length: %d "
714 "first_msdu: %d "
715 "last_msdu: %d "
716 "sa_idx_timeout: %d "
717 "da_idx_timeout: %d "
718 "msdu_limit_error: %d "
719 "flow_idx_timeout: %d "
720 "flow_idx_invalid: %d "
721 "wifi_parser_error: %d "
722 "amsdu_parser_error: %d "
723 "sa_is_valid: %d "
724 "da_is_valid: %d "
725 "da_is_mcbc: %d "
726 "l3_header_padding: %d "
727 "ipv6_options_crc: %d "
728 "tcp_seq_number: %d "
729 "tcp_ack_number: %d "
730 "tcp_flag: %d "
731 "lro_eligible: %d "
732 "window_size: %d "
733 "da_offset: %d "
734 "sa_offset: %d "
735 "da_offset_valid: %d "
736 "sa_offset_valid: %d "
737 "rule_indication_31_0: %d "
738 "rule_indication_63_32: %d "
739 "sa_idx: %d "
740 "msdu_drop: %d "
741 "reo_destination_indication: %d "
742 "flow_idx: %d "
743 "fse_metadata: %d "
744 "cce_metadata: %d "
745 "sa_sw_peer_id: %d ",
746 msdu_end->rxpcu_mpdu_filter_in_category,
747 msdu_end->sw_frame_group_id,
748 msdu_end->phy_ppdu_id,
749 msdu_end->ip_hdr_chksum,
750 msdu_end->tcp_udp_chksum,
751 msdu_end->key_id_octet,
752 msdu_end->cce_super_rule,
753 msdu_end->cce_classify_not_done_truncate,
754 msdu_end->cce_classify_not_done_cce_dis,
755 msdu_end->ext_wapi_pn_63_48,
756 msdu_end->ext_wapi_pn_95_64,
757 msdu_end->ext_wapi_pn_127_96,
758 msdu_end->reported_mpdu_length,
759 msdu_end->first_msdu,
760 msdu_end->last_msdu,
761 msdu_end->sa_idx_timeout,
762 msdu_end->da_idx_timeout,
763 msdu_end->msdu_limit_error,
764 msdu_end->flow_idx_timeout,
765 msdu_end->flow_idx_invalid,
766 msdu_end->wifi_parser_error,
767 msdu_end->amsdu_parser_error,
768 msdu_end->sa_is_valid,
769 msdu_end->da_is_valid,
770 msdu_end->da_is_mcbc,
771 msdu_end->l3_header_padding,
772 msdu_end->ipv6_options_crc,
773 msdu_end->tcp_seq_number,
774 msdu_end->tcp_ack_number,
775 msdu_end->tcp_flag,
776 msdu_end->lro_eligible,
777 msdu_end->window_size,
778 msdu_end->da_offset,
779 msdu_end->sa_offset,
780 msdu_end->da_offset_valid,
781 msdu_end->sa_offset_valid,
782 msdu_end->rule_indication_31_0,
783 msdu_end->rule_indication_63_32,
784 msdu_end->sa_idx,
785 msdu_end->msdu_drop,
786 msdu_end->reo_destination_indication,
787 msdu_end->flow_idx,
788 msdu_end->fse_metadata,
789 msdu_end->cce_metadata,
790 msdu_end->sa_sw_peer_id);
791 }
792
793
794 /*
795 * Get tid from RX_MPDU_START
796 */
797 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
798 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
799 RX_MPDU_INFO_3_TID_OFFSET)), \
800 RX_MPDU_INFO_3_TID_MASK, \
801 RX_MPDU_INFO_3_TID_LSB))
802
hal_rx_mpdu_start_tid_get_8074v2(uint8_t * buf)803 static uint32_t hal_rx_mpdu_start_tid_get_8074v2(uint8_t *buf)
804 {
805 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
806 struct rx_mpdu_start *mpdu_start =
807 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
808 uint32_t tid;
809
810 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
811
812 return tid;
813 }
814
815 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
816 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
817 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
818 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
819 RX_MSDU_START_5_RECEPTION_TYPE_LSB))
820
821 /**
822 * hal_rx_msdu_start_reception_type_get_8074v2() - API to get the reception type
823 * Interval from rx_msdu_start
824 * @buf: pointer to the start of RX PKT TLV header
825 *
826 * Return: uint32_t(reception_type)
827 */
hal_rx_msdu_start_reception_type_get_8074v2(uint8_t * buf)828 static uint32_t hal_rx_msdu_start_reception_type_get_8074v2(uint8_t *buf)
829 {
830 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
831 struct rx_msdu_start *msdu_start =
832 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
833 uint32_t reception_type;
834
835 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
836
837 return reception_type;
838 }
839
840 /* RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET */
841 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
842 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
843 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \
844 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \
845 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB))
846 /**
847 * hal_rx_msdu_end_da_idx_get_8074v2() - API to get da_idx from rx_msdu_end TLV
848 * @buf: pointer to the start of RX PKT TLV headers
849 *
850 * Return: da index
851 */
hal_rx_msdu_end_da_idx_get_8074v2(uint8_t * buf)852 static uint16_t hal_rx_msdu_end_da_idx_get_8074v2(uint8_t *buf)
853 {
854 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
855 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
856 uint16_t da_idx;
857
858 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
859
860 return da_idx;
861 }
862