1 /*
2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "qdf_util.h"
20 #include "qdf_types.h"
21 #include "qdf_lock.h"
22 #include "qdf_mem.h"
23 #include "qdf_nbuf.h"
24 #include "tcl_data_cmd.h"
25 #include "mac_tcl_reg_seq_hwioreg.h"
26 #include "phyrx_rssi_legacy.h"
27 #include "rx_msdu_start.h"
28 #include "tlv_tag_def.h"
29 #include "hal_hw_headers.h"
30 #include "hal_internal.h"
31 #include "cdp_txrx_mon_struct.h"
32 #include "qdf_trace.h"
33 #include "hal_li_rx.h"
34 #include "hal_tx.h"
35 #include "dp_types.h"
36 #include "hal_api_mon.h"
37 #include "phyrx_other_receive_info_ru_details.h"
38
39 #define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
40 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
41 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET)), \
42 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK, \
43 RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB))
44
45 #define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
46 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
47 RX_MSDU_END_5_DA_IS_MCBC_OFFSET)), \
48 RX_MSDU_END_5_DA_IS_MCBC_MASK, \
49 RX_MSDU_END_5_DA_IS_MCBC_LSB))
50
51 #define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
52 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
53 RX_MSDU_END_5_SA_IS_VALID_OFFSET)), \
54 RX_MSDU_END_5_SA_IS_VALID_MASK, \
55 RX_MSDU_END_5_SA_IS_VALID_LSB))
56
57 #define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
58 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
59 RX_MSDU_END_13_SA_IDX_OFFSET)), \
60 RX_MSDU_END_13_SA_IDX_MASK, \
61 RX_MSDU_END_13_SA_IDX_LSB))
62
63 #define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
64 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
65 RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET)), \
66 RX_MSDU_END_5_L3_HEADER_PADDING_MASK, \
67 RX_MSDU_END_5_L3_HEADER_PADDING_LSB))
68
69 #define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
70 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
71 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
72 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK, \
73 RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB))
74
75 #define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
76 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
77 RX_MPDU_INFO_4_PN_31_0_OFFSET)), \
78 RX_MPDU_INFO_4_PN_31_0_MASK, \
79 RX_MPDU_INFO_4_PN_31_0_LSB))
80
81 #define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
82 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
83 RX_MPDU_INFO_5_PN_63_32_OFFSET)), \
84 RX_MPDU_INFO_5_PN_63_32_MASK, \
85 RX_MPDU_INFO_5_PN_63_32_LSB))
86
87 #define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
88 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
89 RX_MPDU_INFO_6_PN_95_64_OFFSET)), \
90 RX_MPDU_INFO_6_PN_95_64_MASK, \
91 RX_MPDU_INFO_6_PN_95_64_LSB))
92
93 #define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
94 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
95 RX_MPDU_INFO_7_PN_127_96_OFFSET)), \
96 RX_MPDU_INFO_7_PN_127_96_MASK, \
97 RX_MPDU_INFO_7_PN_127_96_LSB))
98
99 #define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
100 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
101 RX_MSDU_END_5_FIRST_MSDU_OFFSET)), \
102 RX_MSDU_END_5_FIRST_MSDU_MASK, \
103 RX_MSDU_END_5_FIRST_MSDU_LSB))
104
105 #define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
106 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
107 RX_MSDU_END_5_DA_IS_VALID_OFFSET)), \
108 RX_MSDU_END_5_DA_IS_VALID_MASK, \
109 RX_MSDU_END_5_DA_IS_VALID_LSB))
110
111 #define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \
112 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
113 RX_MSDU_END_5_LAST_MSDU_OFFSET)), \
114 RX_MSDU_END_5_LAST_MSDU_MASK, \
115 RX_MSDU_END_5_LAST_MSDU_LSB))
116
117 #define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \
118 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
119 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
120 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
121 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
122
123 #define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
124 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
125 RX_MPDU_INFO_1_SW_PEER_ID_OFFSET)), \
126 RX_MPDU_INFO_1_SW_PEER_ID_MASK, \
127 RX_MPDU_INFO_1_SW_PEER_ID_LSB))
128
129 #define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
130 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
131 RX_MPDU_INFO_2_TO_DS_OFFSET)), \
132 RX_MPDU_INFO_2_TO_DS_MASK, \
133 RX_MPDU_INFO_2_TO_DS_LSB))
134
135 #define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
136 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
137 RX_MPDU_INFO_2_FR_DS_OFFSET)), \
138 RX_MPDU_INFO_2_FR_DS_MASK, \
139 RX_MPDU_INFO_2_FR_DS_LSB))
140
141 #define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \
142 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
143 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET)), \
144 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK, \
145 RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB))
146
147 #define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
148 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
149 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET)), \
150 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK, \
151 RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB))
152
153 #define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \
154 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
155 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
156 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \
157 RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
158
159 #define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \
160 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
161 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
162 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \
163 RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
164
165 #define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
166 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
167 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET)), \
168 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK, \
169 RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB))
170
171 #define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \
172 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
173 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
174 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \
175 RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
176
177 #define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \
178 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
179 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
180 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \
181 RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
182
183 #define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \
184 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
185 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET)), \
186 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK, \
187 RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB))
188
189 #define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \
190 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
191 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \
192 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \
193 RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB))
194
195 #define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \
196 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
197 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \
198 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \
199 RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB))
200
201 #define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
202 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
203 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET)), \
204 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK, \
205 RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB))
206
207 #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
208 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
209 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
210 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
211 RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
212
213 #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
214 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
215 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
216 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
217 RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
218
219 #define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \
220 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
221 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
222 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
223 RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB))
224
225 #define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
226 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
227 RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
228 RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
229 RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
230
231 #define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
232 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
233 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), \
234 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, \
235 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB))
236
237 #define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \
238 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
239 RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET)), \
240 RX_MSDU_END_16_SA_SW_PEER_ID_MASK, \
241 RX_MSDU_END_16_SA_SW_PEER_ID_LSB))
242
243 #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
244 (uint8_t *)(link_desc_va) + \
245 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
246
247 #define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
248 (uint8_t *)(msdu0) + \
249 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
250
251 #define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
252 (uint8_t *)(ent_ring_desc) + \
253 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
254
255 #define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
256 (uint8_t *)(dst_ring_desc) + \
257 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
258
259 #define HAL_RX_GET_FC_VALID(rx_mpdu_start) \
260 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MPDU_FRAME_CONTROL_VALID)
261
262 #define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \
263 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, TO_DS)
264
265 #define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
266 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD1_VALID)
267
268 #define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \
269 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_2, MAC_ADDR_AD2_VALID)
270
271 #define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \
272 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, RXPCU_MPDU_FILTER_IN_CATEGORY)
273
274 #define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \
275 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, PHY_PPDU_ID)
276
277 #define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
278 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_0, SW_FRAME_GROUP_ID)
279
280 #define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \
281 HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_1, SW_PEER_ID)
282
283 #define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
284 do { \
285 reg_val &= \
286 ~(HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK |\
287 HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK | \
288 HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
289 reg_val |= \
290 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
291 FRAGMENT_DEST_RING, \
292 (reo_params)->frag_dst_ring) | \
293 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
294 AGING_LIST_ENABLE, 1) |\
295 HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
296 AGING_FLUSH_ENABLE, 1);\
297 HAL_REG_WRITE((soc), \
298 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
299 SEQ_WCSS_UMAC_REO_REG_OFFSET), \
300 (reg_val)); \
301 reg_val = \
302 HAL_REG_READ((soc), \
303 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
304 SEQ_WCSS_UMAC_REO_REG_OFFSET)); \
305 reg_val &= \
306 (~HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK |\
307 (REO_REMAP_TCL << HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT)); \
308 HAL_REG_WRITE((soc), \
309 HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
310 SEQ_WCSS_UMAC_REO_REG_OFFSET), \
311 (reg_val)); \
312 } while (0)
313
314 #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
315 ((struct rx_msdu_desc_info *) \
316 _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
317 UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
318
319 #define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
320 ((struct rx_msdu_details *) \
321 _OFFSET_TO_BYTE_PTR((link_desc),\
322 UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET))
323
324 #define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \
325 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
326 RX_MSDU_END_14_FLOW_IDX_OFFSET)), \
327 RX_MSDU_END_14_FLOW_IDX_MASK, \
328 RX_MSDU_END_14_FLOW_IDX_LSB))
329
330 #define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \
331 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
332 RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET)), \
333 RX_MSDU_END_5_FLOW_IDX_INVALID_MASK, \
334 RX_MSDU_END_5_FLOW_IDX_INVALID_LSB))
335
336 #define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
337 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
338 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET)), \
339 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK, \
340 RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB))
341
342 #define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \
343 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
344 RX_MSDU_END_15_FSE_METADATA_OFFSET)), \
345 RX_MSDU_END_15_FSE_METADATA_MASK, \
346 RX_MSDU_END_15_FSE_METADATA_LSB))
347
348 #define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \
349 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
350 RX_MSDU_END_16_CCE_METADATA_OFFSET)), \
351 RX_MSDU_END_16_CCE_METADATA_MASK, \
352 RX_MSDU_END_16_CCE_METADATA_LSB))
353
354 #define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \
355 (_HAL_MS( \
356 (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
357 msdu_end_tlv.rx_msdu_end), \
358 RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET)), \
359 RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK, \
360 RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB))
361 /*
362 * hal_rx_msdu_start_nss_get_6390(): API to get the NSS
363 * Interval from rx_msdu_start
364 *
365 * @buf: pointer to the start of RX PKT TLV header
366 * Return: uint32_t(nss)
367 */
368 static uint32_t
hal_rx_msdu_start_nss_get_6390(uint8_t * buf)369 hal_rx_msdu_start_nss_get_6390(uint8_t *buf)
370 {
371 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
372 struct rx_msdu_start *msdu_start =
373 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
374 uint8_t mimo_ss_bitmap;
375
376 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
377
378 return qdf_get_hweight8(mimo_ss_bitmap);
379
380 }
381
382 /**
383 * hal_rx_mon_hw_desc_get_mpdu_status_6390(): Retrieve MPDU status
384 * @hw_desc_addr: Start address of Rx HW TLVs
385 * @rs: Status for monitor mode
386 *
387 * Return: void
388 */
hal_rx_mon_hw_desc_get_mpdu_status_6390(void * hw_desc_addr,struct mon_rx_status * rs)389 static void hal_rx_mon_hw_desc_get_mpdu_status_6390(void *hw_desc_addr,
390 struct mon_rx_status *rs)
391 {
392 struct rx_msdu_start *rx_msdu_start;
393 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
394 uint32_t reg_value;
395 const uint32_t sgi_hw_to_cdp[] = {
396 CDP_SGI_0_8_US,
397 CDP_SGI_0_4_US,
398 CDP_SGI_1_6_US,
399 CDP_SGI_3_2_US,
400 };
401
402 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
403
404 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
405
406 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
407 RX_MSDU_START_5, USER_RSSI);
408 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
409
410 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
411 rs->sgi = sgi_hw_to_cdp[reg_value];
412
413 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
414 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
415 /* TODO: rs->beamformed should be set for SU beamforming also */
416 }
417
418 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
419
hal_get_link_desc_size_6390(void)420 static uint32_t hal_get_link_desc_size_6390(void)
421 {
422 return LINK_DESC_SIZE;
423 }
424
425 /*
426 * hal_rx_get_tlv_6390(): API to get the tlv
427 *
428 * @rx_tlv: TLV data extracted from the rx packet
429 * Return: uint8_t
430 */
hal_rx_get_tlv_6390(void * rx_tlv)431 static uint8_t hal_rx_get_tlv_6390(void *rx_tlv)
432 {
433 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
434 }
435
436 /**
437 * hal_rx_proc_phyrx_other_receive_info_tlv_6390()
438 * - process other receive info TLV
439 * @rx_tlv_hdr: pointer to TLV header
440 * @ppdu_info_handle: pointer to ppdu_info
441 *
442 * Return: None
443 */
444 static
hal_rx_proc_phyrx_other_receive_info_tlv_6390(void * rx_tlv_hdr,void * ppdu_info_handle)445 void hal_rx_proc_phyrx_other_receive_info_tlv_6390(void *rx_tlv_hdr,
446 void *ppdu_info_handle)
447 {
448 uint32_t tlv_tag, tlv_len;
449 uint32_t temp_len, other_tlv_len, other_tlv_tag;
450 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
451 void *other_tlv_hdr = NULL;
452 void *other_tlv = NULL;
453
454 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
455 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
456 temp_len = 0;
457
458 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
459
460 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
461 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
462 temp_len += other_tlv_len;
463 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
464
465 switch (other_tlv_tag) {
466 default:
467 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
468 "%s unhandled TLV type: %d, TLV len:%d",
469 __func__, other_tlv_tag, other_tlv_len);
470 break;
471 }
472 }
473
474 /**
475 * hal_rx_dump_msdu_start_tlv_6390() - dump RX msdu_start TLV in structured
476 * human readable format.
477 * @pkttlvs: pointer to the pkttlvs.
478 * @dbg_level: log level.
479 *
480 * Return: void
481 */
hal_rx_dump_msdu_start_tlv_6390(void * pkttlvs,uint8_t dbg_level)482 static void hal_rx_dump_msdu_start_tlv_6390(void *pkttlvs, uint8_t dbg_level)
483 {
484 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
485 struct rx_msdu_start *msdu_start =
486 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
487
488 hal_verbose_debug(
489 "rx_msdu_start tlv (1/2) - "
490 "rxpcu_mpdu_filter_in_category: %x "
491 "sw_frame_group_id: %x "
492 "phy_ppdu_id: %x "
493 "msdu_length: %x "
494 "ipsec_esp: %x "
495 "l3_offset: %x "
496 "ipsec_ah: %x "
497 "l4_offset: %x "
498 "msdu_number: %x "
499 "decap_format: %x "
500 "ipv4_proto: %x "
501 "ipv6_proto: %x "
502 "tcp_proto: %x "
503 "udp_proto: %x "
504 "ip_frag: %x "
505 "tcp_only_ack: %x "
506 "da_is_bcast_mcast: %x "
507 "ip4_protocol_ip6_next_header: %x "
508 "toeplitz_hash_2_or_4: %x "
509 "flow_id_toeplitz: %x "
510 "user_rssi: %x "
511 "pkt_type: %x "
512 "stbc: %x "
513 "sgi: %x "
514 "rate_mcs: %x "
515 "receive_bandwidth: %x "
516 "reception_type: %x "
517 "ppdu_start_timestamp: %u ",
518 msdu_start->rxpcu_mpdu_filter_in_category,
519 msdu_start->sw_frame_group_id,
520 msdu_start->phy_ppdu_id,
521 msdu_start->msdu_length,
522 msdu_start->ipsec_esp,
523 msdu_start->l3_offset,
524 msdu_start->ipsec_ah,
525 msdu_start->l4_offset,
526 msdu_start->msdu_number,
527 msdu_start->decap_format,
528 msdu_start->ipv4_proto,
529 msdu_start->ipv6_proto,
530 msdu_start->tcp_proto,
531 msdu_start->udp_proto,
532 msdu_start->ip_frag,
533 msdu_start->tcp_only_ack,
534 msdu_start->da_is_bcast_mcast,
535 msdu_start->ip4_protocol_ip6_next_header,
536 msdu_start->toeplitz_hash_2_or_4,
537 msdu_start->flow_id_toeplitz,
538 msdu_start->user_rssi,
539 msdu_start->pkt_type,
540 msdu_start->stbc,
541 msdu_start->sgi,
542 msdu_start->rate_mcs,
543 msdu_start->receive_bandwidth,
544 msdu_start->reception_type,
545 msdu_start->ppdu_start_timestamp);
546
547 hal_verbose_debug(
548 "rx_msdu_start tlv (2/2) - "
549 "sw_phy_meta_data: %x ",
550 msdu_start->sw_phy_meta_data);
551 }
552
553 /**
554 * hal_rx_dump_msdu_end_tlv_6390() - dump RX msdu_end TLV in structured
555 * human readable format.
556 * @pkttlvs: pointer to the pkttlvs.
557 * @dbg_level: log level.
558 *
559 * Return: void
560 */
hal_rx_dump_msdu_end_tlv_6390(void * pkttlvs,uint8_t dbg_level)561 static void hal_rx_dump_msdu_end_tlv_6390(void *pkttlvs,
562 uint8_t dbg_level)
563 {
564 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
565 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
566
567 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
568 "rx_msdu_end tlv (1/2) - "
569 "rxpcu_mpdu_filter_in_category: %x "
570 "sw_frame_group_id: %x "
571 "phy_ppdu_id: %x "
572 "ip_hdr_chksum: %x "
573 "tcp_udp_chksum: %x "
574 "key_id_octet: %x "
575 "cce_super_rule: %x "
576 "cce_classify_not_done_truncat: %x "
577 "cce_classify_not_done_cce_dis: %x "
578 "ext_wapi_pn_63_48: %x "
579 "ext_wapi_pn_95_64: %x "
580 "ext_wapi_pn_127_96: %x "
581 "reported_mpdu_length: %x "
582 "first_msdu: %x "
583 "last_msdu: %x "
584 "sa_idx_timeout: %x "
585 "da_idx_timeout: %x "
586 "msdu_limit_error: %x "
587 "flow_idx_timeout: %x "
588 "flow_idx_invalid: %x "
589 "wifi_parser_error: %x "
590 "amsdu_parser_error: %x",
591 msdu_end->rxpcu_mpdu_filter_in_category,
592 msdu_end->sw_frame_group_id,
593 msdu_end->phy_ppdu_id,
594 msdu_end->ip_hdr_chksum,
595 msdu_end->tcp_udp_chksum,
596 msdu_end->key_id_octet,
597 msdu_end->cce_super_rule,
598 msdu_end->cce_classify_not_done_truncate,
599 msdu_end->cce_classify_not_done_cce_dis,
600 msdu_end->ext_wapi_pn_63_48,
601 msdu_end->ext_wapi_pn_95_64,
602 msdu_end->ext_wapi_pn_127_96,
603 msdu_end->reported_mpdu_length,
604 msdu_end->first_msdu,
605 msdu_end->last_msdu,
606 msdu_end->sa_idx_timeout,
607 msdu_end->da_idx_timeout,
608 msdu_end->msdu_limit_error,
609 msdu_end->flow_idx_timeout,
610 msdu_end->flow_idx_invalid,
611 msdu_end->wifi_parser_error,
612 msdu_end->amsdu_parser_error);
613
614 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
615 "rx_msdu_end tlv (2/2)- "
616 "sa_is_valid: %x "
617 "da_is_valid: %x "
618 "da_is_mcbc: %x "
619 "l3_header_padding: %x "
620 "ipv6_options_crc: %x "
621 "tcp_seq_number: %x "
622 "tcp_ack_number: %x "
623 "tcp_flag: %x "
624 "lro_eligible: %x "
625 "window_size: %x "
626 "da_offset: %x "
627 "sa_offset: %x "
628 "da_offset_valid: %x "
629 "sa_offset_valid: %x "
630 "rule_indication_31_0: %x "
631 "rule_indication_63_32: %x "
632 "sa_idx: %x "
633 "da_idx: %x "
634 "msdu_drop: %x "
635 "reo_destination_indication: %x "
636 "flow_idx: %x "
637 "fse_metadata: %x "
638 "cce_metadata: %x "
639 "sa_sw_peer_id: %x ",
640 msdu_end->sa_is_valid,
641 msdu_end->da_is_valid,
642 msdu_end->da_is_mcbc,
643 msdu_end->l3_header_padding,
644 msdu_end->ipv6_options_crc,
645 msdu_end->tcp_seq_number,
646 msdu_end->tcp_ack_number,
647 msdu_end->tcp_flag,
648 msdu_end->lro_eligible,
649 msdu_end->window_size,
650 msdu_end->da_offset,
651 msdu_end->sa_offset,
652 msdu_end->da_offset_valid,
653 msdu_end->sa_offset_valid,
654 msdu_end->rule_indication_31_0,
655 msdu_end->rule_indication_63_32,
656 msdu_end->sa_idx,
657 msdu_end->da_idx_or_sw_peer_id,
658 msdu_end->msdu_drop,
659 msdu_end->reo_destination_indication,
660 msdu_end->flow_idx,
661 msdu_end->fse_metadata,
662 msdu_end->cce_metadata,
663 msdu_end->sa_sw_peer_id);
664 }
665
666
667 /*
668 * Get tid from RX_MPDU_START
669 */
670 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
671 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
672 RX_MPDU_INFO_3_TID_OFFSET)), \
673 RX_MPDU_INFO_3_TID_MASK, \
674 RX_MPDU_INFO_3_TID_LSB))
675
hal_rx_mpdu_start_tid_get_6390(uint8_t * buf)676 static uint32_t hal_rx_mpdu_start_tid_get_6390(uint8_t *buf)
677 {
678 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
679 struct rx_mpdu_start *mpdu_start =
680 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
681 uint32_t tid;
682
683 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
684
685 return tid;
686 }
687
688 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
689 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
690 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
691 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
692 RX_MSDU_START_5_RECEPTION_TYPE_LSB))
693
694 /*
695 * hal_rx_msdu_start_reception_type_get(): API to get the reception type
696 * Interval from rx_msdu_start
697 *
698 * @buf: pointer to the start of RX PKT TLV header
699 * Return: uint32_t(reception_type)
700 */
701 static
hal_rx_msdu_start_reception_type_get_6390(uint8_t * buf)702 uint32_t hal_rx_msdu_start_reception_type_get_6390(uint8_t *buf)
703 {
704 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
705 struct rx_msdu_start *msdu_start =
706 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
707 uint32_t reception_type;
708
709 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
710
711 return reception_type;
712 }
713
714 #define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
715 (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
716 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_OFFSET)), \
717 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_MASK, \
718 RX_MSDU_END_13_DA_IDX_OR_SW_PEER_ID_LSB))
719
720 /**
721 * hal_rx_msdu_end_da_idx_get_6390: API to get da_idx
722 * from rx_msdu_end TLV
723 *
724 * @ buf: pointer to the start of RX PKT TLV headers
725 * Return: da index
726 */
hal_rx_msdu_end_da_idx_get_6390(uint8_t * buf)727 static uint16_t hal_rx_msdu_end_da_idx_get_6390(uint8_t *buf)
728 {
729 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
730 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
731 uint16_t da_idx;
732
733 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
734
735 return da_idx;
736 }
737
738