1 /*
2 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19
20 #include "qdf_types.h"
21 #include "qdf_util.h"
22 #include "qdf_types.h"
23 #include "qdf_lock.h"
24 #include "qdf_mem.h"
25 #include "qdf_nbuf.h"
26 #include "hal_internal.h"
27 #include "hal_api.h"
28 #include "target_type.h"
29 #include "wcss_version.h"
30 #include "qdf_module.h"
31 #include "hal_flow.h"
32 #include "rx_flow_search_entry.h"
33 #include "hal_rx_flow_info.h"
34
35 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
36 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
37 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
38 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK
39 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
40 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB
41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
42 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
59
60 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
61 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET
62 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
63 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
64 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
65 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET
66 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
67 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
68 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
69 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
70 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
71 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
72 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
73 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET
74 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
75 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER
76 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
77 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET
78 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
79 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET
80
81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
83 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
84 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
85 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
86 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
87 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
88 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
89 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
90 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
93 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
94 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
97 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
98 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
101 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
102 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
107
108 #include "hal_wcn6450_tx.h"
109 #include "hal_wcn6450_rx.h"
110 #include <hal_generic_api.h>
111 #include "hal_rh_rx.h"
112 #include "hal_rh_api.h"
113 #include "hal_api_mon.h"
114 #include "hal_rh_generic_api.h"
115
116 struct hal_hw_srng_config hw_srng_table_wcn6450[] = {
117 /* TODO: max_rings can populated by querying HW capabilities */
118 {/* REO_DST */ 0},
119 {/* REO_EXCEPTION */ 0},
120 {/* REO_REINJECT */ 0},
121 {/* REO_CMD */ 0},
122 {/* REO_STATUS */ 0},
123 {/* TCL_DATA */ 0},
124 {/* TCL_CMD */ 0},
125 {/* TCL_STATUS */ 0},
126 {/* CE_SRC */ 0},
127 {/* CE_DST */ 0},
128 {/* CE_DST_STATUS */ 0},
129 {/* WBM_IDLE_LINK */ 0},
130 {/* SW2WBM_RELEASE */ 0},
131 {/* WBM2SW_RELEASE */ 0},
132 { /* RXDMA_BUF */
133 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
134 #ifdef IPA_OFFLOAD
135 .max_rings = 3,
136 #else
137 .max_rings = 2,
138 #endif
139 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
140 .lmac_ring = TRUE,
141 .ring_dir = HAL_SRNG_SRC_RING,
142 /* reg_start is not set because LMAC rings are not accessed
143 * from host
144 */
145 .reg_start = {},
146 .reg_size = {},
147 .max_size = HAL_RXDMA_MAX_RING_SIZE,
148 },
149 { /* RXDMA_DST */
150 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
151 .max_rings = 1,
152 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
153 .lmac_ring = TRUE,
154 .ring_dir = HAL_SRNG_DST_RING,
155 /* reg_start is not set because LMAC rings are not accessed
156 * from host
157 */
158 .reg_start = {},
159 .reg_size = {},
160 .max_size = HAL_RXDMA_MAX_RING_SIZE,
161 },
162 {/* RXDMA_MONITOR_BUF */ 0},
163 { /* RXDMA_MONITOR_STATUS */
164 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
165 .max_rings = 1,
166 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
167 .lmac_ring = TRUE,
168 .ring_dir = HAL_SRNG_SRC_RING,
169 /* reg_start is not set because LMAC rings are not accessed
170 * from host
171 */
172 .reg_start = {},
173 .reg_size = {},
174 .max_size = HAL_RXDMA_MAX_RING_SIZE,
175 },
176 {/* RXDMA_MONITOR_DST */ 0},
177 {/* RXDMA_MONITOR_DESC */ 0},
178 {/* DIR_BUF_RX_DMA_SRC */
179 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
180 /*
181 * one ring is for spectral scan
182 * the other is for cfr
183 */
184 .max_rings = 2,
185 .entry_size = 2,
186 .lmac_ring = TRUE,
187 .ring_dir = HAL_SRNG_SRC_RING,
188 /* reg_start is not set because LMAC rings are not accessed
189 * from host
190 */
191 .reg_start = {},
192 .reg_size = {},
193 .max_size = HAL_RXDMA_MAX_RING_SIZE,
194 },
195 #ifdef WLAN_FEATURE_CIF_CFR
196 {/* WIFI_POS_SRC */
197 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
198 .max_rings = 1,
199 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
200 .lmac_ring = TRUE,
201 .ring_dir = HAL_SRNG_SRC_RING,
202 /* reg_start is not set because LMAC rings are not accessed
203 * from host
204 */
205 .reg_start = {},
206 .reg_size = {},
207 .max_size = HAL_RXDMA_MAX_RING_SIZE,
208 },
209 #endif
210 { /* REO2PPE */ 0},
211 { /* PPE2TCL */ 0},
212 { /* PPE_RELEASE */ 0},
213 { /* TX_MONITOR_BUF */ 0},
214 { /* TX_MONITOR_DST */ 0},
215 { /* SW2RXDMA_NEW */ 0},
216 { /* SW2RXDMA_LINK_RELEASE */
217 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA_LINK_RING,
218 .max_rings = 1,
219 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
220 .lmac_ring = TRUE,
221 .ring_dir = HAL_SRNG_SRC_RING,
222 /* reg_start is not set because LMAC rings are not accessed
223 * from host
224 */
225 .reg_start = {},
226 .reg_size = {},
227 .max_size = HAL_RXDMA_MAX_RING_SIZE,
228 },
229
230 };
231
hal_get_hw_hptp_6450(struct hal_soc * hal_soc,hal_ring_handle_t hal_ring_hdl,uint32_t * headp,uint32_t * tailp,uint8_t ring)232 static void hal_get_hw_hptp_6450(struct hal_soc *hal_soc,
233 hal_ring_handle_t hal_ring_hdl,
234 uint32_t *headp, uint32_t *tailp,
235 uint8_t ring)
236 {
237 }
238
hal_reo_setup_6450(struct hal_soc * soc,void * reoparams,int qref_reset)239 static void hal_reo_setup_6450(struct hal_soc *soc, void *reoparams,
240 int qref_reset)
241 {
242 }
243
hal_reo_set_err_dst_remap_6450(void * hal_soc)244 static void hal_reo_set_err_dst_remap_6450(void *hal_soc)
245 {
246 }
247
hal_tx_desc_set_dscp_tid_table_id_6450(void * desc,uint8_t id)248 static void hal_tx_desc_set_dscp_tid_table_id_6450(void *desc, uint8_t id)
249 {
250 }
251
hal_tx_set_dscp_tid_map_6450(struct hal_soc * hal_soc,uint8_t * map,uint8_t id)252 static void hal_tx_set_dscp_tid_map_6450(struct hal_soc *hal_soc,
253 uint8_t *map, uint8_t id)
254 {
255 }
256
hal_tx_update_dscp_tid_6450(struct hal_soc * hal_soc,uint8_t tid,uint8_t id,uint8_t dscp)257 static void hal_tx_update_dscp_tid_6450(struct hal_soc *hal_soc, uint8_t tid,
258 uint8_t id, uint8_t dscp)
259 {
260 }
261
hal_tx_comp_get_release_reason_6450(void * hal_desc)262 static uint8_t hal_tx_comp_get_release_reason_6450(void *hal_desc)
263 {
264 return 0;
265 }
266
hal_get_wbm_internal_error_6450(void * hal_desc)267 static uint8_t hal_get_wbm_internal_error_6450(void *hal_desc)
268 {
269 return 0;
270 }
271
hal_tx_init_cmd_credit_ring_6450(hal_soc_handle_t hal_soc_hdl,hal_ring_handle_t hal_ring_hdl)272 static void hal_tx_init_cmd_credit_ring_6450(hal_soc_handle_t hal_soc_hdl,
273 hal_ring_handle_t hal_ring_hdl)
274 {
275 }
276
277 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
hal_get_link_desc_size_6450(void)278 static uint32_t hal_get_link_desc_size_6450(void)
279 {
280 return LINK_DESC_SIZE;
281 }
282
hal_reo_status_get_header_6450(hal_ring_desc_t ring_desc,int b,void * h1)283 static void hal_reo_status_get_header_6450(hal_ring_desc_t ring_desc,
284 int b, void *h1)
285 {
286 }
287
hal_rx_wbm_err_info_get_6450(void * wbm_desc,void * wbm_er_info1)288 static void hal_rx_wbm_err_info_get_6450(void *wbm_desc,
289 void *wbm_er_info1)
290 {
291 }
292
hal_rx_is_unicast_6450(uint8_t * buf)293 static bool hal_rx_is_unicast_6450(uint8_t *buf)
294 {
295 return true;
296 }
297
hal_rx_tid_get_6450(hal_soc_handle_t hal_soc_hdl,uint8_t * buf)298 static uint32_t hal_rx_tid_get_6450(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
299 {
300 return 0;
301 }
302
hal_rx_msdu0_buffer_addr_lsb_6450(void * link_desc_va)303 static void *hal_rx_msdu0_buffer_addr_lsb_6450(void *link_desc_va)
304 {
305 return NULL;
306 }
307
hal_rx_msdu_desc_info_ptr_get_6450(void * msdu0)308 static void *hal_rx_msdu_desc_info_ptr_get_6450(void *msdu0)
309 {
310 return NULL;
311 }
312
hal_ent_mpdu_desc_info_6450(void * ent_ring_desc)313 static void *hal_ent_mpdu_desc_info_6450(void *ent_ring_desc)
314 {
315 return NULL;
316 }
317
hal_dst_mpdu_desc_info_6450(void * dst_ring_desc)318 static void *hal_dst_mpdu_desc_info_6450(void *dst_ring_desc)
319 {
320 return NULL;
321 }
322
hal_rx_get_fc_valid_6450(uint8_t * buf)323 static uint8_t hal_rx_get_fc_valid_6450(uint8_t *buf)
324 {
325 return HAL_RX_GET_FC_VALID(buf);
326 }
327
hal_rx_get_to_ds_flag_6450(uint8_t * buf)328 static uint8_t hal_rx_get_to_ds_flag_6450(uint8_t *buf)
329 {
330 return HAL_RX_GET_TO_DS_FLAG(buf);
331 }
332
hal_rx_get_mac_addr2_valid_6450(uint8_t * buf)333 static uint8_t hal_rx_get_mac_addr2_valid_6450(uint8_t *buf)
334 {
335 return HAL_RX_GET_MAC_ADDR2_VALID(buf);
336 }
337
hal_rx_get_filter_category_6450(uint8_t * buf)338 static uint8_t hal_rx_get_filter_category_6450(uint8_t *buf)
339 {
340 return HAL_RX_GET_FILTER_CATEGORY(buf);
341 }
342
hal_reo_config_6450(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)343 static void hal_reo_config_6450(struct hal_soc *soc,
344 uint32_t reg_val,
345 struct hal_reo_params *reo_params)
346 {
347 }
348
349 /**
350 * hal_rx_msdu_flow_idx_get_6450: API to get flow index
351 * from rx_msdu_end TLV
352 * @buf: pointer to the start of RX PKT TLV headers
353 *
354 * Return: flow index value from MSDU END TLV
355 */
hal_rx_msdu_flow_idx_get_6450(uint8_t * buf)356 static inline uint32_t hal_rx_msdu_flow_idx_get_6450(uint8_t *buf)
357 {
358 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
359 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
360
361 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
362 }
363
hal_compute_reo_remap_ix2_ix3_6450(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)364 static void hal_compute_reo_remap_ix2_ix3_6450(uint32_t *ring,
365 uint32_t num_rings,
366 uint32_t *remap1,
367 uint32_t *remap2)
368 {
369 }
370
371 static void
hal_setup_link_idle_list_6450(struct hal_soc * soc,qdf_dma_addr_t scatter_bufs_base_paddr[],void * scatter_bufs_base_vaddr[],uint32_t num_scatter_bufs,uint32_t scatter_buf_size,uint32_t last_buf_end_offset,uint32_t num_entries)372 hal_setup_link_idle_list_6450(struct hal_soc *soc,
373 qdf_dma_addr_t scatter_bufs_base_paddr[],
374 void *scatter_bufs_base_vaddr[],
375 uint32_t num_scatter_bufs,
376 uint32_t scatter_buf_size,
377 uint32_t last_buf_end_offset,
378 uint32_t num_entries)
379 {
380 }
381
hal_compute_reo_remap_ix0_6450(uint32_t * remap0)382 static void hal_compute_reo_remap_ix0_6450(uint32_t *remap0)
383 {
384 }
385
386 #define UMAC_WINDOW_REMAP_RANGE 0x14
387 #define CE_WINDOW_REMAP_RANGE 0X37
388 #define CMEM_WINDOW_REMAP_RANGE 0x2
389
390 /**
391 * hal_get_window_address_6450(): Function to get the ioremap address
392 * @hal_soc: Pointer to hal_soc
393 * @addr: address offset of register
394 *
395 * Return: modified address offset of register
396 */
hal_get_window_address_6450(struct hal_soc * hal_soc,qdf_iomem_t addr)397 static inline qdf_iomem_t hal_get_window_address_6450(struct hal_soc *hal_soc,
398 qdf_iomem_t addr)
399 {
400 uint32_t offset;
401 uint32_t window;
402 uint8_t scale;
403
404 offset = addr - hal_soc->dev_base_addr;
405 window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
406
407 /* UMAC: 2nd window(unused) CE: 3rd window, CMEM: 4th window */
408 switch (window) {
409 case UMAC_WINDOW_REMAP_RANGE:
410 scale = 1;
411 break;
412 case CE_WINDOW_REMAP_RANGE:
413 scale = 2;
414 break;
415 case CMEM_WINDOW_REMAP_RANGE:
416 scale = 3;
417 break;
418 default:
419 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
420 "%s: ERROR: Accessing Wrong register\n", __func__);
421 qdf_assert_always(0);
422 return 0;
423 }
424
425 return hal_soc->dev_base_addr + (scale * WINDOW_START) +
426 (offset & WINDOW_RANGE_MASK);
427 }
428
429 /*
430 * hal_rx_msdu_start_nss_get_6450(): API to get the NSS
431 * Interval from rx_msdu_start
432 *
433 * @buf: pointer to the start of RX PKT TLV header
434 * Return: uint32_t(nss)
435 */
hal_rx_msdu_start_nss_get_6450(uint8_t * buf)436 static uint32_t hal_rx_msdu_start_nss_get_6450(uint8_t *buf)
437 {
438 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
439 struct rx_msdu_start *msdu_start =
440 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
441 uint8_t mimo_ss_bitmap;
442
443 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
444
445 return qdf_get_hweight8(mimo_ss_bitmap);
446 }
447
448 /**
449 * hal_rx_mon_hw_desc_get_mpdu_status_6450(): Retrieve MPDU status
450 *
451 * @hw_desc_addr: Start address of Rx HW TLVs
452 * @rs: Status for monitor mode
453 *
454 * Return: void
455 */
hal_rx_mon_hw_desc_get_mpdu_status_6450(void * hw_desc_addr,struct mon_rx_status * rs)456 static void hal_rx_mon_hw_desc_get_mpdu_status_6450(void *hw_desc_addr,
457 struct mon_rx_status *rs)
458 {
459 struct rx_msdu_start *rx_msdu_start;
460 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
461 uint32_t reg_value;
462 const uint32_t sgi_hw_to_cdp[] = {
463 CDP_SGI_0_8_US,
464 CDP_SGI_0_4_US,
465 CDP_SGI_1_6_US,
466 CDP_SGI_3_2_US,
467 };
468
469 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
470
471 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
472
473 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
474 RX_MSDU_START_5, USER_RSSI);
475 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
476
477 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
478 rs->sgi = sgi_hw_to_cdp[reg_value];
479
480 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
481 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
482 /* TODO: rs->beamformed should be set for SU beamforming also */
483 }
484
485 /*
486 * hal_rx_get_tlv_6450(): API to get the tlv
487 *
488 * @rx_tlv: TLV data extracted from the rx packet
489 * Return: uint8_t
490 */
hal_rx_get_tlv_6450(void * rx_tlv)491 static uint8_t hal_rx_get_tlv_6450(void *rx_tlv)
492 {
493 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
494 }
495
496 /**
497 * hal_rx_proc_phyrx_other_receive_info_tlv_6450()
498 * - process other receive info TLV
499 * @rx_tlv_hdr: pointer to TLV header
500 * @ppdu_info_handle: pointer to ppdu_info
501 *
502 * Return: None
503 */
504 static
hal_rx_proc_phyrx_other_receive_info_tlv_6450(void * rx_tlv_hdr,void * ppdu_info_handle)505 void hal_rx_proc_phyrx_other_receive_info_tlv_6450(void *rx_tlv_hdr,
506 void *ppdu_info_handle)
507 {
508 uint32_t tlv_tag, tlv_len;
509 uint32_t temp_len, other_tlv_len, other_tlv_tag;
510 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
511 void *other_tlv_hdr = NULL;
512 void *other_tlv = NULL;
513
514 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
515 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
516 temp_len = 0;
517
518 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
519
520 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
521 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
522 temp_len += other_tlv_len;
523 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
524
525 switch (other_tlv_tag) {
526 default:
527 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
528 "%s unhandled TLV type: %d, TLV len:%d",
529 __func__, other_tlv_tag, other_tlv_len);
530 break;
531 }
532 }
533
534 /**
535 * hal_rx_dump_msdu_start_tlv_6450() : dump RX msdu_start TLV in structured
536 * human readable format.
537 * @pkttlvs: pointer to pkttlvs.
538 * @dbg_level: log level.
539 *
540 * Return: void
541 */
hal_rx_dump_msdu_start_tlv_6450(void * pkttlvs,uint8_t dbg_level)542 static void hal_rx_dump_msdu_start_tlv_6450(void *pkttlvs, uint8_t dbg_level)
543 {
544 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
545 struct rx_msdu_start *msdu_start =
546 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
547
548 hal_verbose_debug(
549 "rx_msdu_start tlv (1/2) - "
550 "rxpcu_mpdu_filter_in_category: %x "
551 "sw_frame_group_id: %x "
552 "phy_ppdu_id: %x "
553 "msdu_length: %x "
554 "ipsec_esp: %x "
555 "l3_offset: %x "
556 "ipsec_ah: %x "
557 "l4_offset: %x "
558 "msdu_number: %x "
559 "decap_format: %x "
560 "ipv4_proto: %x "
561 "ipv6_proto: %x "
562 "tcp_proto: %x "
563 "udp_proto: %x "
564 "ip_frag: %x "
565 "tcp_only_ack: %x "
566 "da_is_bcast_mcast: %x "
567 "ip4_protocol_ip6_next_header: %x "
568 "toeplitz_hash_2_or_4: %x "
569 "flow_id_toeplitz: %x "
570 "user_rssi: %x "
571 "pkt_type: %x "
572 "stbc: %x "
573 "sgi: %x "
574 "rate_mcs: %x "
575 "receive_bandwidth: %x "
576 "reception_type: %x "
577 "ppdu_start_timestamp: %u ",
578 msdu_start->rxpcu_mpdu_filter_in_category,
579 msdu_start->sw_frame_group_id,
580 msdu_start->phy_ppdu_id,
581 msdu_start->msdu_length,
582 msdu_start->ipsec_esp,
583 msdu_start->l3_offset,
584 msdu_start->ipsec_ah,
585 msdu_start->l4_offset,
586 msdu_start->msdu_number,
587 msdu_start->decap_format,
588 msdu_start->ipv4_proto,
589 msdu_start->ipv6_proto,
590 msdu_start->tcp_proto,
591 msdu_start->udp_proto,
592 msdu_start->ip_frag,
593 msdu_start->tcp_only_ack,
594 msdu_start->da_is_bcast_mcast,
595 msdu_start->ip4_protocol_ip6_next_header,
596 msdu_start->toeplitz_hash_2_or_4,
597 msdu_start->flow_id_toeplitz,
598 msdu_start->user_rssi,
599 msdu_start->pkt_type,
600 msdu_start->stbc,
601 msdu_start->sgi,
602 msdu_start->rate_mcs,
603 msdu_start->receive_bandwidth,
604 msdu_start->reception_type,
605 msdu_start->ppdu_start_timestamp);
606
607 hal_verbose_debug(
608 "rx_msdu_start tlv (2/2) - "
609 "sw_phy_meta_data: %x ",
610 msdu_start->sw_phy_meta_data);
611 }
612
613 /**
614 * hal_rx_dump_msdu_end_tlv_6450: dump RX msdu_end TLV in structured
615 * human readable format.
616 * @pkttlvs: pointer to pkttlvs.
617 * @dbg_level: log level.
618 *
619 * Return: void
620 */
hal_rx_dump_msdu_end_tlv_6450(void * pkttlvs,uint8_t dbg_level)621 static void hal_rx_dump_msdu_end_tlv_6450(void *pkttlvs,
622 uint8_t dbg_level)
623 {
624 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs;
625 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
626
627 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
628 "rx_msdu_end tlv (1/3) - "
629 "rxpcu_mpdu_filter_in_category: %x "
630 "sw_frame_group_id: %x "
631 "phy_ppdu_id: %x "
632 "ip_hdr_chksum: %x "
633 "tcp_udp_chksum: %x "
634 "key_id_octet: %x "
635 "cce_super_rule: %x "
636 "cce_classify_not_done_truncat: %x "
637 "cce_classify_not_done_cce_dis: %x "
638 "reported_mpdu_length: %x "
639 "first_msdu: %x "
640 "last_msdu: %x "
641 "sa_idx_timeout: %x "
642 "da_idx_timeout: %x "
643 "msdu_limit_error: %x "
644 "flow_idx_timeout: %x "
645 "flow_idx_invalid: %x "
646 "wifi_parser_error: %x "
647 "amsdu_parser_error: %x",
648 msdu_end->rxpcu_mpdu_filter_in_category,
649 msdu_end->sw_frame_group_id,
650 msdu_end->phy_ppdu_id,
651 msdu_end->ip_hdr_chksum,
652 msdu_end->tcp_udp_chksum,
653 msdu_end->key_id_octet,
654 msdu_end->cce_super_rule,
655 msdu_end->cce_classify_not_done_truncate,
656 msdu_end->cce_classify_not_done_cce_dis,
657 msdu_end->reported_mpdu_length,
658 msdu_end->first_msdu,
659 msdu_end->last_msdu,
660 msdu_end->sa_idx_timeout,
661 msdu_end->da_idx_timeout,
662 msdu_end->msdu_limit_error,
663 msdu_end->flow_idx_timeout,
664 msdu_end->flow_idx_invalid,
665 msdu_end->wifi_parser_error,
666 msdu_end->amsdu_parser_error);
667
668 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
669 "rx_msdu_end tlv (2/3)- "
670 "sa_is_valid: %x "
671 "da_is_valid: %x "
672 "da_is_mcbc: %x "
673 "l3_header_padding: %x "
674 "ipv6_options_crc: %x "
675 "tcp_seq_number: %x "
676 "tcp_ack_number: %x "
677 "tcp_flag: %x "
678 "lro_eligible: %x "
679 "window_size: %x "
680 "da_offset: %x "
681 "sa_offset: %x "
682 "da_offset_valid: %x "
683 "sa_offset_valid: %x "
684 "rule_indication_31_0: %x "
685 "rule_indication_63_32: %x "
686 "sa_idx: %x "
687 "da_idx: %x "
688 "msdu_drop: %x "
689 "reo_destination_indication: %x "
690 "flow_idx: %x "
691 "fse_metadata: %x "
692 "cce_metadata: %x "
693 "sa_sw_peer_id: %x ",
694 msdu_end->sa_is_valid,
695 msdu_end->da_is_valid,
696 msdu_end->da_is_mcbc,
697 msdu_end->l3_header_padding,
698 msdu_end->ipv6_options_crc,
699 msdu_end->tcp_seq_number,
700 msdu_end->tcp_ack_number,
701 msdu_end->tcp_flag,
702 msdu_end->lro_eligible,
703 msdu_end->window_size,
704 msdu_end->da_offset,
705 msdu_end->sa_offset,
706 msdu_end->da_offset_valid,
707 msdu_end->sa_offset_valid,
708 msdu_end->rule_indication_31_0,
709 msdu_end->rule_indication_63_32,
710 msdu_end->sa_idx,
711 msdu_end->da_idx_or_sw_peer_id,
712 msdu_end->msdu_drop,
713 msdu_end->reo_destination_indication,
714 msdu_end->flow_idx,
715 msdu_end->fse_metadata,
716 msdu_end->cce_metadata,
717 msdu_end->sa_sw_peer_id);
718 __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP,
719 "rx_msdu_end tlv (3/3)"
720 "aggregation_count %x "
721 "flow_aggregation_continuation %x "
722 "fisa_timeout %x "
723 "cumulative_l4_checksum %x "
724 "cumulative_ip_length %x",
725 msdu_end->aggregation_count,
726 msdu_end->flow_aggregation_continuation,
727 msdu_end->fisa_timeout,
728 msdu_end->cumulative_l4_checksum,
729 msdu_end->cumulative_ip_length);
730 }
731
732 /*
733 * Get tid from RX_MPDU_START
734 */
735 #define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
736 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
737 RX_MPDU_INFO_7_TID_OFFSET)), \
738 RX_MPDU_INFO_7_TID_MASK, \
739 RX_MPDU_INFO_7_TID_LSB))
740
hal_rx_mpdu_start_tid_get_6450(uint8_t * buf)741 static uint32_t hal_rx_mpdu_start_tid_get_6450(uint8_t *buf)
742 {
743 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
744 struct rx_mpdu_start *mpdu_start =
745 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
746 uint32_t tid;
747
748 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
749
750 return tid;
751 }
752
753 #define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
754 (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
755 RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
756 RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
757 RX_MSDU_START_5_RECEPTION_TYPE_LSB))
758
759 /*
760 * hal_rx_msdu_start_reception_type_get(): API to get the reception type
761 * Interval from rx_msdu_start
762 *
763 * @buf: pointer to the start of RX PKT TLV header
764 * Return: uint32_t(reception_type)
765 */
766 static
hal_rx_msdu_start_reception_type_get_6450(uint8_t * buf)767 uint32_t hal_rx_msdu_start_reception_type_get_6450(uint8_t *buf)
768 {
769 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
770 struct rx_msdu_start *msdu_start =
771 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
772 uint32_t reception_type;
773
774 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
775
776 return reception_type;
777 }
778
779 /**
780 * hal_rx_msdu_end_da_idx_get_6450: API to get da_idx
781 * from rx_msdu_end TLV
782 *
783 * @buf: pointer to the start of RX PKT TLV headers
784 * Return: da index
785 */
hal_rx_msdu_end_da_idx_get_6450(uint8_t * buf)786 static uint16_t hal_rx_msdu_end_da_idx_get_6450(uint8_t *buf)
787 {
788 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
789 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
790 uint16_t da_idx;
791
792 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end);
793
794 return da_idx;
795 }
796
797 /**
798 * hal_rx_msdu_desc_info_get_ptr_6450() - Get msdu desc info ptr
799 * @msdu_details_ptr: Pointer to msdu_details_ptr
800 *
801 * Return - Pointer to rx_msdu_desc_info structure.
802 *
803 */
hal_rx_msdu_desc_info_get_ptr_6450(void * msdu_details_ptr)804 static void *hal_rx_msdu_desc_info_get_ptr_6450(void *msdu_details_ptr)
805 {
806 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
807 }
808
809 /**
810 * hal_rx_link_desc_msdu0_ptr_6450 - Get pointer to rx_msdu details
811 * @link_desc: Pointer to link desc
812 *
813 * Return - Pointer to rx_msdu_details structure
814 *
815 */
hal_rx_link_desc_msdu0_ptr_6450(void * link_desc)816 static void *hal_rx_link_desc_msdu0_ptr_6450(void *link_desc)
817 {
818 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
819 }
820
821 /**
822 * hal_rx_get_rx_fragment_number_6450(): Function to retrieve rx fragment number
823 *
824 * @buf: Network buffer
825 * Returns: rx fragment number
826 */
827 static
hal_rx_get_rx_fragment_number_6450(uint8_t * buf)828 uint8_t hal_rx_get_rx_fragment_number_6450(uint8_t *buf)
829 {
830 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
831 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
832
833 /* Return first 4 bits as fragment number */
834 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
835 DOT11_SEQ_FRAG_MASK);
836 }
837
838 /**
839 * hal_rx_msdu_end_da_is_mcbc_get_6450(): API to check if pkt is MCBC
840 * from rx_msdu_end TLV
841 *
842 * @buf: pointer to the start of RX PKT TLV headers
843 * Return: da_is_mcbc
844 */
845 static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_6450(uint8_t * buf)846 hal_rx_msdu_end_da_is_mcbc_get_6450(uint8_t *buf)
847 {
848 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
849 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
850
851 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
852 }
853
854 /**
855 * hal_rx_msdu_end_sa_is_valid_get_6450(): API to get_6450 the
856 * sa_is_valid bit from rx_msdu_end TLV
857 *
858 * @buf: pointer to the start of RX PKT TLV headers
859 * Return: sa_is_valid bit
860 */
861 static uint8_t
hal_rx_msdu_end_sa_is_valid_get_6450(uint8_t * buf)862 hal_rx_msdu_end_sa_is_valid_get_6450(uint8_t *buf)
863 {
864 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
865 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
866 uint8_t sa_is_valid;
867
868 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
869
870 return sa_is_valid;
871 }
872
873 /**
874 * hal_rx_msdu_end_sa_idx_get_6450(): API to get_6450 the
875 * sa_idx from rx_msdu_end TLV
876 *
877 * @buf: pointer to the start of RX PKT TLV headers
878 * Return: sa_idx (SA AST index)
879 */
880 static
hal_rx_msdu_end_sa_idx_get_6450(uint8_t * buf)881 uint16_t hal_rx_msdu_end_sa_idx_get_6450(uint8_t *buf)
882 {
883 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
884 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
885 uint16_t sa_idx;
886
887 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
888
889 return sa_idx;
890 }
891
892 /**
893 * hal_rx_desc_is_first_msdu_6450() - Check if first msdu
894 *
895 * @hw_desc_addr: hardware descriptor address
896 *
897 * Return: 0 - success/ non-zero failure
898 */
hal_rx_desc_is_first_msdu_6450(void * hw_desc_addr)899 static uint32_t hal_rx_desc_is_first_msdu_6450(void *hw_desc_addr)
900 {
901 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
902 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
903
904 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU);
905 }
906
907 /**
908 * hal_rx_msdu_end_l3_hdr_padding_get_6450(): API to get_6450 the
909 * l3_header padding from rx_msdu_end TLV
910 *
911 * @buf: pointer to the start of RX PKT TLV headers
912 * Return: number of l3 header padding bytes
913 */
hal_rx_msdu_end_l3_hdr_padding_get_6450(uint8_t * buf)914 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6450(uint8_t *buf)
915 {
916 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
917 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
918 uint32_t l3_header_padding;
919
920 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
921
922 return l3_header_padding;
923 }
924
925 /*
926 * @ hal_rx_encryption_info_valid_6450: Returns encryption type.
927 *
928 * @ buf: rx_tlv_hdr of the received packet
929 * @ Return: encryption type
930 */
hal_rx_encryption_info_valid_6450(uint8_t * buf)931 static uint32_t hal_rx_encryption_info_valid_6450(uint8_t *buf)
932 {
933 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
934 struct rx_mpdu_start *mpdu_start =
935 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
936 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
937 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
938
939 return encryption_info;
940 }
941
942 /*
943 * @ hal_rx_print_pn_6450: Prints the PN of rx packet.
944 *
945 * @ buf: rx_tlv_hdr of the received packet
946 * @ Return: void
947 */
hal_rx_print_pn_6450(uint8_t * buf)948 static void hal_rx_print_pn_6450(uint8_t *buf)
949 {
950 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
951 struct rx_mpdu_start *mpdu_start =
952 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
953 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
954
955 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
956 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
957 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
958 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
959
960 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x",
961 pn_127_96, pn_95_64, pn_63_32, pn_31_0);
962 }
963
964 /**
965 * hal_rx_msdu_end_first_msdu_get_6450: API to get first msdu status
966 * from rx_msdu_end TLV
967 *
968 * @buf: pointer to the start of RX PKT TLV headers
969 * Return: first_msdu
970 */
hal_rx_msdu_end_first_msdu_get_6450(uint8_t * buf)971 static uint8_t hal_rx_msdu_end_first_msdu_get_6450(uint8_t *buf)
972 {
973 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
974 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
975 uint8_t first_msdu;
976
977 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
978
979 return first_msdu;
980 }
981
982 /**
983 * hal_rx_msdu_end_da_is_valid_get_6450: API to check if da is valid
984 * from rx_msdu_end TLV
985 *
986 * @buf: pointer to the start of RX PKT TLV headers
987 * Return: da_is_valid
988 */
hal_rx_msdu_end_da_is_valid_get_6450(uint8_t * buf)989 static uint8_t hal_rx_msdu_end_da_is_valid_get_6450(uint8_t *buf)
990 {
991 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
992 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
993 uint8_t da_is_valid;
994
995 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
996
997 return da_is_valid;
998 }
999
1000 /**
1001 * hal_rx_msdu_end_last_msdu_get_6450: API to get last msdu status
1002 * from rx_msdu_end TLV
1003 *
1004 * @buf: pointer to the start of RX PKT TLV headers
1005 * Return: last_msdu
1006 */
hal_rx_msdu_end_last_msdu_get_6450(uint8_t * buf)1007 static uint8_t hal_rx_msdu_end_last_msdu_get_6450(uint8_t *buf)
1008 {
1009 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1010 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1011 uint8_t last_msdu;
1012
1013 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
1014
1015 return last_msdu;
1016 }
1017
1018 /*
1019 * hal_rx_get_mpdu_mac_ad4_valid_6450(): Retrieves if mpdu 4th addr is valid
1020 *
1021 * @nbuf: Network buffer
1022 * Returns: value of mpdu 4th address valid field
1023 */
hal_rx_get_mpdu_mac_ad4_valid_6450(uint8_t * buf)1024 static bool hal_rx_get_mpdu_mac_ad4_valid_6450(uint8_t *buf)
1025 {
1026 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1027 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1028 bool ad4_valid = 0;
1029
1030 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info);
1031
1032 return ad4_valid;
1033 }
1034
1035 /**
1036 * hal_rx_mpdu_start_sw_peer_id_get_6450: Retrieve sw peer_id
1037 * @buf: network buffer
1038 *
1039 * Return: sw peer_id
1040 */
hal_rx_mpdu_start_sw_peer_id_get_6450(uint8_t * buf)1041 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6450(uint8_t *buf)
1042 {
1043 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1044 struct rx_mpdu_start *mpdu_start =
1045 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1046
1047 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
1048 &mpdu_start->rx_mpdu_info_details);
1049 }
1050
1051 /**
1052 * hal_rx_mpdu_get_to_ds_6450(): API to get the tods info
1053 * from rx_mpdu_start
1054 *
1055 * @buf: pointer to the start of RX PKT TLV header
1056 * Return: uint32_t(to_ds)
1057 */
hal_rx_mpdu_get_to_ds_6450(uint8_t * buf)1058 static uint32_t hal_rx_mpdu_get_to_ds_6450(uint8_t *buf)
1059 {
1060 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1061 struct rx_mpdu_start *mpdu_start =
1062 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1063
1064 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1065
1066 return HAL_RX_MPDU_GET_TODS(mpdu_info);
1067 }
1068
1069 /*
1070 * hal_rx_mpdu_get_fr_ds_6450(): API to get the from ds info
1071 * from rx_mpdu_start
1072 *
1073 * @buf: pointer to the start of RX PKT TLV header
1074 * Return: uint32_t(fr_ds)
1075 */
hal_rx_mpdu_get_fr_ds_6450(uint8_t * buf)1076 static uint32_t hal_rx_mpdu_get_fr_ds_6450(uint8_t *buf)
1077 {
1078 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1079 struct rx_mpdu_start *mpdu_start =
1080 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1081
1082 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1083
1084 return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
1085 }
1086
1087 /*
1088 * hal_rx_get_mpdu_frame_control_valid_6450(): Retrieves mpdu
1089 * frame control valid
1090 *
1091 * @nbuf: Network buffer
1092 * Returns: value of frame control valid field
1093 */
hal_rx_get_mpdu_frame_control_valid_6450(uint8_t * buf)1094 static uint8_t hal_rx_get_mpdu_frame_control_valid_6450(uint8_t *buf)
1095 {
1096 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1097 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1098
1099 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
1100 }
1101
1102 /*
1103 * hal_rx_mpdu_get_addr1_6450(): API to check get address1 of the mpdu
1104 *
1105 * @buf: pointer to the start of RX PKT TLV headera
1106 * @mac_addr: pointer to mac address
1107 * Return: success/failure
1108 */
hal_rx_mpdu_get_addr1_6450(uint8_t * buf,uint8_t * mac_addr)1109 static QDF_STATUS hal_rx_mpdu_get_addr1_6450(uint8_t *buf, uint8_t *mac_addr)
1110 {
1111 struct __attribute__((__packed__)) hal_addr1 {
1112 uint32_t ad1_31_0;
1113 uint16_t ad1_47_32;
1114 };
1115
1116 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1117 struct rx_mpdu_start *mpdu_start =
1118 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1119
1120 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1121 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
1122 uint32_t mac_addr_ad1_valid;
1123
1124 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
1125
1126 if (mac_addr_ad1_valid) {
1127 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
1128 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
1129 return QDF_STATUS_SUCCESS;
1130 }
1131
1132 return QDF_STATUS_E_FAILURE;
1133 }
1134
1135 /*
1136 * hal_rx_mpdu_get_addr2_6450(): API to check get address2 of the mpdu
1137 * in the packet
1138 *
1139 * @buf: pointer to the start of RX PKT TLV header
1140 * @mac_addr: pointer to mac address
1141 * Return: success/failure
1142 */
hal_rx_mpdu_get_addr2_6450(uint8_t * buf,uint8_t * mac_addr)1143 static QDF_STATUS hal_rx_mpdu_get_addr2_6450(uint8_t *buf,
1144 uint8_t *mac_addr)
1145 {
1146 struct __attribute__((__packed__)) hal_addr2 {
1147 uint16_t ad2_15_0;
1148 uint32_t ad2_47_16;
1149 };
1150
1151 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1152 struct rx_mpdu_start *mpdu_start =
1153 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1154
1155 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1156 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
1157 uint32_t mac_addr_ad2_valid;
1158
1159 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
1160
1161 if (mac_addr_ad2_valid) {
1162 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
1163 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
1164 return QDF_STATUS_SUCCESS;
1165 }
1166
1167 return QDF_STATUS_E_FAILURE;
1168 }
1169
1170 /*
1171 * hal_rx_mpdu_get_addr3_6450(): API to get address3 of the mpdu
1172 * in the packet
1173 *
1174 * @buf: pointer to the start of RX PKT TLV header
1175 * @mac_addr: pointer to mac address
1176 * Return: success/failure
1177 */
hal_rx_mpdu_get_addr3_6450(uint8_t * buf,uint8_t * mac_addr)1178 static QDF_STATUS hal_rx_mpdu_get_addr3_6450(uint8_t *buf, uint8_t *mac_addr)
1179 {
1180 struct __attribute__((__packed__)) hal_addr3 {
1181 uint32_t ad3_31_0;
1182 uint16_t ad3_47_32;
1183 };
1184
1185 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1186 struct rx_mpdu_start *mpdu_start =
1187 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1188
1189 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1190 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
1191 uint32_t mac_addr_ad3_valid;
1192
1193 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
1194
1195 if (mac_addr_ad3_valid) {
1196 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
1197 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
1198 return QDF_STATUS_SUCCESS;
1199 }
1200
1201 return QDF_STATUS_E_FAILURE;
1202 }
1203
1204 /*
1205 * hal_rx_mpdu_get_addr4_6450(): API to get address4 of the mpdu
1206 * in the packet
1207 *
1208 * @buf: pointer to the start of RX PKT TLV header
1209 * @mac_addr: pointer to mac address
1210 * Return: success/failure
1211 */
hal_rx_mpdu_get_addr4_6450(uint8_t * buf,uint8_t * mac_addr)1212 static QDF_STATUS hal_rx_mpdu_get_addr4_6450(uint8_t *buf, uint8_t *mac_addr)
1213 {
1214 struct __attribute__((__packed__)) hal_addr4 {
1215 uint32_t ad4_31_0;
1216 uint16_t ad4_47_32;
1217 };
1218
1219 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1220 struct rx_mpdu_start *mpdu_start =
1221 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1222
1223 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
1224 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
1225 uint32_t mac_addr_ad4_valid;
1226
1227 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
1228
1229 if (mac_addr_ad4_valid) {
1230 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
1231 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
1232 return QDF_STATUS_SUCCESS;
1233 }
1234
1235 return QDF_STATUS_E_FAILURE;
1236 }
1237
1238 /*
1239 * hal_rx_get_mpdu_sequence_control_valid_6450(): Get mpdu
1240 * sequence control valid
1241 *
1242 * @nbuf: Network buffer
1243 * Returns: value of sequence control valid field
1244 */
hal_rx_get_mpdu_sequence_control_valid_6450(uint8_t * buf)1245 static uint8_t hal_rx_get_mpdu_sequence_control_valid_6450(uint8_t *buf)
1246 {
1247 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1248 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1249
1250 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
1251 }
1252
1253 /**
1254 * hal_rx_hw_desc_get_ppduid_get_6450(): retrieve ppdu id
1255 * @rx_tlv_hdr: rx tlv header
1256 * @rxdma_dst_ring_desc: rxdma HW descriptor
1257 *
1258 * Return: ppdu id
1259 */
hal_rx_hw_desc_get_ppduid_get_6450(void * rx_tlv_hdr,void * rxdma_dst_ring_desc)1260 static uint32_t hal_rx_hw_desc_get_ppduid_get_6450(void *rx_tlv_hdr,
1261 void *rxdma_dst_ring_desc)
1262 {
1263 struct rx_mpdu_info *rx_mpdu_info;
1264 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
1265
1266 rx_mpdu_info =
1267 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
1268
1269 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID);
1270 }
1271
1272 static uint32_t
hal_rx_get_ppdu_id_6450(uint8_t * buf)1273 hal_rx_get_ppdu_id_6450(uint8_t *buf)
1274 {
1275 return HAL_RX_GET_PPDU_ID(buf);
1276 }
1277
1278 /**
1279 * hal_rx_msdu_flow_idx_invalid_6450: API to get flow index invalid
1280 * from rx_msdu_end TLV
1281 * @buf: pointer to the start of RX PKT TLV headers
1282 *
1283 * Return: flow index invalid value from MSDU END TLV
1284 */
hal_rx_msdu_flow_idx_invalid_6450(uint8_t * buf)1285 static bool hal_rx_msdu_flow_idx_invalid_6450(uint8_t *buf)
1286 {
1287 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1288 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1289
1290 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
1291 }
1292
1293 /**
1294 * hal_rx_msdu_flow_idx_timeout_6450: API to get flow index timeout
1295 * from rx_msdu_end TLV
1296 * @buf: pointer to the start of RX PKT TLV headers
1297 *
1298 * Return: flow index timeout value from MSDU END TLV
1299 */
hal_rx_msdu_flow_idx_timeout_6450(uint8_t * buf)1300 static bool hal_rx_msdu_flow_idx_timeout_6450(uint8_t *buf)
1301 {
1302 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1303 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1304
1305 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
1306 }
1307
1308 /**
1309 * hal_rx_msdu_fse_metadata_get_6450: API to get FSE metadata
1310 * from rx_msdu_end TLV
1311 * @buf: pointer to the start of RX PKT TLV headers
1312 *
1313 * Return: fse metadata value from MSDU END TLV
1314 */
hal_rx_msdu_fse_metadata_get_6450(uint8_t * buf)1315 static uint32_t hal_rx_msdu_fse_metadata_get_6450(uint8_t *buf)
1316 {
1317 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1318 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1319
1320 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
1321 }
1322
1323 /**
1324 * hal_rx_msdu_cce_metadata_get_6450: API to get CCE metadata
1325 * from rx_msdu_end TLV
1326 * @buf: pointer to the start of RX PKT TLV headers
1327 *
1328 * Return: cce_metadata
1329 */
1330 static uint16_t
hal_rx_msdu_cce_metadata_get_6450(uint8_t * buf)1331 hal_rx_msdu_cce_metadata_get_6450(uint8_t *buf)
1332 {
1333 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1334 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1335
1336 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
1337 }
1338
1339 /**
1340 * hal_rx_msdu_get_flow_params_6450: API to get flow index, flow index invalid
1341 * and flow index timeout from rx_msdu_end TLV
1342 * @buf: pointer to the start of RX PKT TLV headers
1343 * @flow_invalid: pointer to return value of flow_idx_valid
1344 * @flow_timeout: pointer to return value of flow_idx_timeout
1345 * @flow_index: pointer to return value of flow_idx
1346 *
1347 * Return: none
1348 */
1349 static inline void
hal_rx_msdu_get_flow_params_6450(uint8_t * buf,bool * flow_invalid,bool * flow_timeout,uint32_t * flow_index)1350 hal_rx_msdu_get_flow_params_6450(uint8_t *buf,
1351 bool *flow_invalid,
1352 bool *flow_timeout,
1353 uint32_t *flow_index)
1354 {
1355 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1356 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1357
1358 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
1359 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
1360 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
1361 }
1362
1363 /**
1364 * hal_rx_tlv_get_tcp_chksum_6450() - API to get tcp checksum
1365 * @buf: rx_tlv_hdr
1366 *
1367 * Return: tcp checksum
1368 */
1369 static uint16_t
hal_rx_tlv_get_tcp_chksum_6450(uint8_t * buf)1370 hal_rx_tlv_get_tcp_chksum_6450(uint8_t *buf)
1371 {
1372 return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
1373 }
1374
1375 /**
1376 * hal_rx_get_rx_sequence_6450(): Function to retrieve rx sequence number
1377 *
1378 * @buf: Network buffer
1379 * Returns: rx sequence number
1380 */
1381 static
hal_rx_get_rx_sequence_6450(uint8_t * buf)1382 uint16_t hal_rx_get_rx_sequence_6450(uint8_t *buf)
1383 {
1384 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1385 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1386
1387 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
1388 }
1389
1390 /**
1391 * hal_rx_get_fisa_cumulative_l4_checksum_6450() - Retrieve cumulative
1392 * checksum
1393 * @buf: buffer pointer
1394 *
1395 * Return: cumulative checksum
1396 */
1397 static inline
hal_rx_get_fisa_cumulative_l4_checksum_6450(uint8_t * buf)1398 uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6450(uint8_t *buf)
1399 {
1400 return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf);
1401 }
1402
1403 /**
1404 * hal_rx_get_fisa_cumulative_ip_length_6450() - Retrieve cumulative
1405 * ip length
1406 * @buf: buffer pointer
1407 *
1408 * Return: cumulative length
1409 */
1410 static inline
hal_rx_get_fisa_cumulative_ip_length_6450(uint8_t * buf)1411 uint16_t hal_rx_get_fisa_cumulative_ip_length_6450(uint8_t *buf)
1412 {
1413 return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf);
1414 }
1415
1416 /**
1417 * hal_rx_get_udp_proto_6450() - Retrieve udp proto value
1418 * @buf: buffer
1419 *
1420 * Return: udp proto bit
1421 */
1422 static inline
hal_rx_get_udp_proto_6450(uint8_t * buf)1423 bool hal_rx_get_udp_proto_6450(uint8_t *buf)
1424 {
1425 return HAL_RX_TLV_GET_UDP_PROTO(buf);
1426 }
1427
1428 /**
1429 * hal_rx_get_flow_agg_continuation_6450() - retrieve flow agg
1430 * continuation
1431 * @buf: buffer
1432 *
1433 * Return: flow agg
1434 */
1435 static inline
hal_rx_get_flow_agg_continuation_6450(uint8_t * buf)1436 bool hal_rx_get_flow_agg_continuation_6450(uint8_t *buf)
1437 {
1438 return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf);
1439 }
1440
1441 /**
1442 * hal_rx_get_flow_agg_count_6450()- Retrieve flow agg count
1443 * @buf: buffer
1444 *
1445 * Return: flow agg count
1446 */
1447 static inline
hal_rx_get_flow_agg_count_6450(uint8_t * buf)1448 uint8_t hal_rx_get_flow_agg_count_6450(uint8_t *buf)
1449 {
1450 return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf);
1451 }
1452
1453 /**
1454 * hal_rx_get_fisa_timeout_6450() - Retrieve fisa timeout
1455 * @buf: buffer
1456 *
1457 * Return: fisa timeout
1458 */
1459 static inline
hal_rx_get_fisa_timeout_6450(uint8_t * buf)1460 bool hal_rx_get_fisa_timeout_6450(uint8_t *buf)
1461 {
1462 return HAL_RX_TLV_GET_FISA_TIMEOUT(buf);
1463 }
1464
1465 /**
1466 * hal_rx_mpdu_start_tlv_tag_valid_6450 () - API to check if RX_MPDU_START
1467 * tlv tag is valid
1468 *
1469 *@rx_tlv_hdr: start address of rx_pkt_tlvs
1470 *
1471 * Return: true if RX_MPDU_START is valid, else false.
1472 */
hal_rx_mpdu_start_tlv_tag_valid_6450(void * rx_tlv_hdr)1473 static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6450(void *rx_tlv_hdr)
1474 {
1475 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
1476 uint32_t tlv_tag;
1477
1478 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
1479
1480 return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
1481 }
1482
1483 /*
1484 * hal_rx_flow_setup_fse_6450() - Setup a flow search entry in HW FST
1485 * @fst: Pointer to the Rx Flow Search Table
1486 * @table_offset: offset into the table where the flow is to be setup
1487 * @flow: Flow Parameters
1488 *
1489 * Flow table entry fields are updated in host byte order, little endian order.
1490 *
1491 * Return: Success/Failure
1492 */
1493 static void *
hal_rx_flow_setup_fse_6450(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)1494 hal_rx_flow_setup_fse_6450(uint8_t *rx_fst, uint32_t table_offset,
1495 uint8_t *rx_flow)
1496 {
1497 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
1498 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1499 uint8_t *fse;
1500 bool fse_valid;
1501
1502 if (table_offset >= fst->max_entries) {
1503 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1504 "HAL FSE table offset %u exceeds max entries %u",
1505 table_offset, fst->max_entries);
1506 return NULL;
1507 }
1508
1509 fse = (uint8_t *)fst->base_vaddr +
1510 (table_offset * HAL_RX_FST_ENTRY_SIZE);
1511
1512 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1513
1514 if (fse_valid) {
1515 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1516 "HAL FSE %pK already valid", fse);
1517 return NULL;
1518 }
1519
1520 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) =
1521 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
1522 (flow->tuple_info.src_ip_127_96));
1523
1524 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) =
1525 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
1526 (flow->tuple_info.src_ip_95_64));
1527
1528 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) =
1529 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
1530 (flow->tuple_info.src_ip_63_32));
1531
1532 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) =
1533 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
1534 (flow->tuple_info.src_ip_31_0));
1535
1536 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) =
1537 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
1538 (flow->tuple_info.dest_ip_127_96));
1539
1540 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) =
1541 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
1542 (flow->tuple_info.dest_ip_95_64));
1543
1544 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) =
1545 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
1546 (flow->tuple_info.dest_ip_63_32));
1547
1548 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) =
1549 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
1550 (flow->tuple_info.dest_ip_31_0));
1551
1552 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT);
1553 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |=
1554 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
1555 (flow->tuple_info.dest_port));
1556
1557 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT);
1558 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |=
1559 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
1560 (flow->tuple_info.src_port));
1561
1562 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL);
1563 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |=
1564 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
1565 flow->tuple_info.l4_protocol);
1566
1567 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER);
1568 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |=
1569 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
1570 flow->reo_destination_handler);
1571
1572 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1573 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |=
1574 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
1575
1576 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA);
1577 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) =
1578 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
1579 (flow->fse_metadata));
1580
1581 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION);
1582 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |=
1583 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9,
1584 REO_DESTINATION_INDICATION,
1585 flow->reo_destination_indication);
1586
1587 /* Reset all the other fields in FSE */
1588 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9);
1589 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP);
1590 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT);
1591 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT);
1592 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP);
1593
1594 return fse;
1595 }
1596
1597 /*
1598 * hal_rx_flow_setup_cmem_fse_6450() - Setup a flow search entry in HW CMEM FST
1599 * @hal_soc: hal_soc reference
1600 * @cmem_ba: CMEM base address
1601 * @table_offset: offset into the table where the flow is to be setup
1602 * @flow: Flow Parameters
1603 *
1604 * Return: Success/Failure
1605 */
1606 static uint32_t
hal_rx_flow_setup_cmem_fse_6450(struct hal_soc * hal_soc,uint32_t cmem_ba,uint32_t table_offset,uint8_t * rx_flow)1607 hal_rx_flow_setup_cmem_fse_6450(struct hal_soc *hal_soc, uint32_t cmem_ba,
1608 uint32_t table_offset, uint8_t *rx_flow)
1609 {
1610 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1611 uint32_t fse_offset;
1612 uint32_t value;
1613
1614 fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE);
1615
1616 /* Reset the Valid bit */
1617 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9,
1618 VALID), 0);
1619
1620 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
1621 (flow->tuple_info.src_ip_127_96));
1622 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_0,
1623 SRC_IP_127_96), value);
1624
1625 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
1626 (flow->tuple_info.src_ip_95_64));
1627 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_1,
1628 SRC_IP_95_64), value);
1629
1630 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
1631 (flow->tuple_info.src_ip_63_32));
1632 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_2,
1633 SRC_IP_63_32), value);
1634
1635 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
1636 (flow->tuple_info.src_ip_31_0));
1637 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_3,
1638 SRC_IP_31_0), value);
1639
1640 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
1641 (flow->tuple_info.dest_ip_127_96));
1642 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_4,
1643 DEST_IP_127_96), value);
1644
1645 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
1646 (flow->tuple_info.dest_ip_95_64));
1647 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_5,
1648 DEST_IP_95_64), value);
1649
1650 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
1651 (flow->tuple_info.dest_ip_63_32));
1652 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_6,
1653 DEST_IP_63_32), value);
1654
1655 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
1656 (flow->tuple_info.dest_ip_31_0));
1657 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_7,
1658 DEST_IP_31_0), value);
1659
1660 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
1661 (flow->tuple_info.dest_port));
1662 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
1663 (flow->tuple_info.src_port));
1664 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_8,
1665 SRC_PORT), value);
1666
1667 value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
1668 (flow->fse_metadata));
1669 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_10,
1670 METADATA), value);
1671
1672 /* Reset all the other fields in FSE */
1673 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_11,
1674 MSDU_COUNT), 0);
1675 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_12,
1676 MSDU_BYTE_COUNT), 0);
1677 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13,
1678 TIMESTAMP), 0);
1679
1680 value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
1681 flow->tuple_info.l4_protocol);
1682 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
1683 flow->reo_destination_handler);
1684 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9,
1685 REO_DESTINATION_INDICATION,
1686 flow->reo_destination_indication);
1687 value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
1688 HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9,
1689 L4_PROTOCOL), value);
1690
1691 return fse_offset;
1692 }
1693
1694 /**
1695 * hal_rx_flow_get_cmem_fse_ts_6450() - Get timestamp field from CMEM FSE
1696 * @hal_soc: hal_soc reference
1697 * @fse_offset: CMEM FSE offset
1698 *
1699 * Return: Timestamp
1700 */
hal_rx_flow_get_cmem_fse_ts_6450(struct hal_soc * hal_soc,uint32_t fse_offset)1701 static uint32_t hal_rx_flow_get_cmem_fse_ts_6450(struct hal_soc *hal_soc,
1702 uint32_t fse_offset)
1703 {
1704 return HAL_CMEM_READ(hal_soc, fse_offset +
1705 HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP));
1706 }
1707
1708 /**
1709 * hal_rx_flow_get_cmem_fse_6450() - Get FSE from CMEM
1710 * @hal_soc: hal_soc reference
1711 * @fse_offset: CMEM FSE offset
1712 * @fse: reference where FSE will be copied
1713 * @len: length of FSE
1714 *
1715 * Return: If read is successful or not
1716 */
1717 static void
hal_rx_flow_get_cmem_fse_6450(struct hal_soc * hal_soc,uint32_t fse_offset,uint32_t * fse,qdf_size_t len)1718 hal_rx_flow_get_cmem_fse_6450(struct hal_soc *hal_soc, uint32_t fse_offset,
1719 uint32_t *fse, qdf_size_t len)
1720 {
1721 int i;
1722
1723 if (len != HAL_RX_FST_ENTRY_SIZE)
1724 return;
1725
1726 for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++)
1727 fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4);
1728 }
1729
1730 /**
1731 * hal_rx_msdu_get_reo_destination_indication_6450: API to get
1732 * reo_destination_indication from rx_msdu_end TLV
1733 * @buf: pointer to the start of RX PKT TLV headers
1734 * @reo_destination_ind: pointer to return value
1735 * of reo_destination_indication
1736 *
1737 * Return: none
1738 */
1739 static void
hal_rx_msdu_get_reo_destination_indication_6450(uint8_t * buf,uint32_t * reo_destination_ind)1740 hal_rx_msdu_get_reo_destination_indication_6450(uint8_t *buf,
1741 uint32_t *reo_destination_ind)
1742 {
1743 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1744 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1745
1746 *reo_destination_ind =
1747 HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end);
1748 }
1749
1750 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
hal_get_first_wow_wakeup_packet_6450(uint8_t * buf)1751 static inline uint8_t hal_get_first_wow_wakeup_packet_6450(uint8_t *buf)
1752 {
1753 return 0;
1754 }
1755 #endif
1756
1757 /**
1758 * hal_rx_tlv_l3_type_get_6450() - Function to retrieve l3_type
1759 * @buf: Network buffer
1760 *
1761 * Return: l3_type
1762 */
hal_rx_tlv_l3_type_get_6450(uint8_t * buf)1763 static uint32_t hal_rx_tlv_l3_type_get_6450(uint8_t *buf)
1764 {
1765 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1766 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1767
1768 return HAL_RX_MSDU_END_L3_TYPE_GET(msdu_end);
1769 }
1770
1771 /**
1772 * hal_rx_msdu_start_get_len_6450(): API to get the MSDU length
1773 * from rx_msdu_start TLV
1774 *
1775 * @buf: pointer to the start of RX PKT TLV headers
1776 * Return: (uint32_t)msdu length
1777 */
hal_rx_msdu_start_get_len_6450(uint8_t * buf)1778 static uint32_t hal_rx_msdu_start_get_len_6450(uint8_t *buf)
1779 {
1780 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1781 struct rx_msdu_start *msdu_start =
1782 &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
1783 uint32_t msdu_len;
1784
1785 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
1786
1787 return msdu_len;
1788 }
1789
hal_hw_txrx_ops_attach_wcn6450(struct hal_soc * hal_soc)1790 static void hal_hw_txrx_ops_attach_wcn6450(struct hal_soc *hal_soc)
1791 {
1792 /* Initialize setup tx/rx ops here */
1793 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1794 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1795 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_6450;
1796 hal_soc->ops->hal_reo_setup = hal_reo_setup_6450;
1797 hal_soc->ops->hal_get_window_address = hal_get_window_address_6450;
1798 hal_soc->ops->hal_reo_set_err_dst_remap =
1799 hal_reo_set_err_dst_remap_6450;
1800
1801 /* tx */
1802 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
1803 hal_tx_desc_set_dscp_tid_table_id_6450;
1804 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6450;
1805 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6450;
1806 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6450;
1807 hal_soc->ops->hal_tx_desc_set_buf_addr =
1808 hal_tx_desc_set_buf_addr_generic_rh;
1809 hal_soc->ops->hal_tx_desc_set_search_type =
1810 hal_tx_desc_set_search_type_generic_rh;
1811 hal_soc->ops->hal_tx_desc_set_search_index =
1812 hal_tx_desc_set_search_index_generic_rh;
1813 hal_soc->ops->hal_tx_desc_set_cache_set_num =
1814 hal_tx_desc_set_cache_set_num_generic_rh;
1815 hal_soc->ops->hal_tx_comp_get_status =
1816 hal_tx_comp_get_status_generic_rh;
1817 hal_soc->ops->hal_tx_comp_get_release_reason =
1818 hal_tx_comp_get_release_reason_6450;
1819 hal_soc->ops->hal_get_wbm_internal_error =
1820 hal_get_wbm_internal_error_6450;
1821 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6450;
1822 hal_soc->ops->hal_tx_init_cmd_credit_ring =
1823 hal_tx_init_cmd_credit_ring_6450;
1824
1825 /* rx */
1826 hal_soc->ops->hal_rx_msdu_start_nss_get =
1827 hal_rx_msdu_start_nss_get_6450;
1828 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1829 hal_rx_mon_hw_desc_get_mpdu_status_6450;
1830 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6450;
1831 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1832 hal_rx_proc_phyrx_other_receive_info_tlv_6450;
1833
1834 hal_soc->ops->hal_rx_dump_msdu_end_tlv =
1835 hal_rx_dump_msdu_end_tlv_6450;
1836 hal_soc->ops->hal_rx_dump_rx_attention_tlv =
1837 hal_rx_dump_rx_attention_tlv_generic_rh;
1838 hal_soc->ops->hal_rx_dump_msdu_start_tlv =
1839 hal_rx_dump_msdu_start_tlv_6450;
1840 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1841 hal_rx_dump_mpdu_start_tlv_generic_rh;
1842 hal_soc->ops->hal_rx_dump_mpdu_end_tlv =
1843 hal_rx_dump_mpdu_end_tlv_generic_rh;
1844 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv =
1845 hal_rx_dump_pkt_hdr_tlv_generic_rh;
1846
1847 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6450;
1848 hal_soc->ops->hal_rx_mpdu_start_tid_get =
1849 hal_rx_mpdu_start_tid_get_6450;
1850 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1851 hal_rx_msdu_start_reception_type_get_6450;
1852 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1853 hal_rx_msdu_end_da_idx_get_6450;
1854 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1855 hal_rx_msdu_desc_info_get_ptr_6450;
1856 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1857 hal_rx_link_desc_msdu0_ptr_6450;
1858 hal_soc->ops->hal_reo_status_get_header =
1859 hal_reo_status_get_header_6450;
1860 hal_soc->ops->hal_rx_status_get_tlv_info =
1861 hal_rx_status_get_tlv_info_generic_rh;
1862 hal_soc->ops->hal_rx_wbm_err_info_get =
1863 hal_rx_wbm_err_info_get_6450;
1864 hal_soc->ops->hal_tx_set_pcp_tid_map =
1865 hal_tx_set_pcp_tid_map_generic_rh;
1866 hal_soc->ops->hal_tx_update_pcp_tid_map =
1867 hal_tx_update_pcp_tid_generic_rh;
1868 hal_soc->ops->hal_tx_set_tidmap_prty =
1869 hal_tx_update_tidmap_prty_generic_rh;
1870 hal_soc->ops->hal_rx_get_rx_fragment_number =
1871 hal_rx_get_rx_fragment_number_6450;
1872 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1873 hal_rx_msdu_end_da_is_mcbc_get_6450;
1874 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1875 hal_rx_msdu_end_sa_is_valid_get_6450;
1876 hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
1877 hal_rx_msdu_end_sa_idx_get_6450;
1878 hal_soc->ops->hal_rx_desc_is_first_msdu =
1879 hal_rx_desc_is_first_msdu_6450;
1880 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1881 hal_rx_msdu_end_l3_hdr_padding_get_6450;
1882 hal_soc->ops->hal_rx_encryption_info_valid =
1883 hal_rx_encryption_info_valid_6450;
1884 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6450;
1885 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1886 hal_rx_msdu_end_first_msdu_get_6450;
1887 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1888 hal_rx_msdu_end_da_is_valid_get_6450;
1889 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1890 hal_rx_msdu_end_last_msdu_get_6450;
1891 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1892 hal_rx_get_mpdu_mac_ad4_valid_6450;
1893 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1894 hal_rx_mpdu_start_sw_peer_id_get_6450;
1895 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1896 hal_rx_mpdu_peer_meta_data_get_rh;
1897 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6450;
1898 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6450;
1899 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1900 hal_rx_get_mpdu_frame_control_valid_6450;
1901 hal_soc->ops->hal_rx_get_frame_ctrl_field =
1902 hal_rx_get_frame_ctrl_field_rh;
1903 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6450;
1904 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6450;
1905 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6450;
1906 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6450;
1907 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1908 hal_rx_get_mpdu_sequence_control_valid_6450;
1909 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6450;
1910 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6450;
1911 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1912 hal_rx_hw_desc_get_ppduid_get_6450;
1913 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1914 hal_rx_msdu0_buffer_addr_lsb_6450;
1915 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1916 hal_rx_msdu_desc_info_ptr_get_6450;
1917 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6450;
1918 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6450;
1919 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6450;
1920 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6450;
1921 hal_soc->ops->hal_rx_get_mac_addr2_valid =
1922 hal_rx_get_mac_addr2_valid_6450;
1923 hal_soc->ops->hal_rx_get_filter_category =
1924 hal_rx_get_filter_category_6450;
1925 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6450;
1926 hal_soc->ops->hal_reo_config = hal_reo_config_6450;
1927 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6450;
1928 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1929 hal_rx_msdu_flow_idx_invalid_6450;
1930 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1931 hal_rx_msdu_flow_idx_timeout_6450;
1932 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1933 hal_rx_msdu_fse_metadata_get_6450;
1934 hal_soc->ops->hal_rx_msdu_cce_match_get =
1935 hal_rx_msdu_cce_match_get_rh;
1936 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1937 hal_rx_msdu_cce_metadata_get_6450;
1938 hal_soc->ops->hal_rx_msdu_get_flow_params =
1939 hal_rx_msdu_get_flow_params_6450;
1940 hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
1941 hal_rx_tlv_get_tcp_chksum_6450;
1942 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6450;
1943 #if defined(QCA_WIFI_WCN6450) && defined(WLAN_CFR_ENABLE) && \
1944 defined(WLAN_ENH_CFR_ENABLE)
1945 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6450;
1946 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6450;
1947 #endif
1948
1949 /* rx - msdu end fast path info fields */
1950 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1951 hal_rx_msdu_packet_metadata_get_generic_rh;
1952 hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum =
1953 hal_rx_get_fisa_cumulative_l4_checksum_6450;
1954 hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length =
1955 hal_rx_get_fisa_cumulative_ip_length_6450;
1956 hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6450;
1957 hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation =
1958 hal_rx_get_flow_agg_continuation_6450;
1959 hal_soc->ops->hal_rx_get_fisa_flow_agg_count =
1960 hal_rx_get_flow_agg_count_6450;
1961 hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6450;
1962 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1963 hal_rx_mpdu_start_tlv_tag_valid_6450;
1964
1965 /* rx - TLV struct offsets */
1966 hal_soc->ops->hal_rx_msdu_end_offset_get =
1967 hal_rx_msdu_end_offset_get_generic;
1968 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
1969 hal_soc->ops->hal_rx_msdu_start_offset_get =
1970 hal_rx_msdu_start_offset_get_generic;
1971 hal_soc->ops->hal_rx_mpdu_start_offset_get =
1972 hal_rx_mpdu_start_offset_get_generic;
1973 hal_soc->ops->hal_rx_mpdu_end_offset_get =
1974 hal_rx_mpdu_end_offset_get_generic;
1975 #ifndef NO_RX_PKT_HDR_TLV
1976 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1977 hal_rx_pkt_tlv_offset_get_generic;
1978 #endif
1979 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6450;
1980 hal_soc->ops->hal_rx_flow_get_tuple_info =
1981 hal_rx_flow_get_tuple_info_rh;
1982 hal_soc->ops->hal_rx_flow_delete_entry =
1983 hal_rx_flow_delete_entry_rh;
1984 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_rh;
1985 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1986 hal_compute_reo_remap_ix2_ix3_6450;
1987
1988 /* CMEM FSE */
1989 hal_soc->ops->hal_rx_flow_setup_cmem_fse =
1990 hal_rx_flow_setup_cmem_fse_6450;
1991 hal_soc->ops->hal_rx_flow_get_cmem_fse_ts =
1992 hal_rx_flow_get_cmem_fse_ts_6450;
1993 hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_6450;
1994 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
1995 hal_rx_msdu_get_reo_destination_indication_6450;
1996 hal_soc->ops->hal_setup_link_idle_list =
1997 hal_setup_link_idle_list_6450;
1998 #ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET
1999 hal_soc->ops->hal_get_first_wow_wakeup_packet =
2000 hal_get_first_wow_wakeup_packet_6450;
2001 #endif
2002 hal_soc->ops->hal_compute_reo_remap_ix0 =
2003 hal_compute_reo_remap_ix0_6450;
2004 hal_soc->ops->hal_rx_tlv_l3_type_get =
2005 hal_rx_tlv_l3_type_get_6450;
2006 hal_soc->ops->hal_rx_tlv_msdu_len_get =
2007 hal_rx_msdu_start_get_len_6450;
2008 }
2009
2010 /**
2011 * hal_wcn6450_attach() - Attach 6450 target specific hal_soc ops,
2012 * offset and srng table
2013 * @hal_soc: HAL Soc handle
2014 *
2015 * Return: None
2016 */
hal_wcn6450_attach(struct hal_soc * hal_soc)2017 void hal_wcn6450_attach(struct hal_soc *hal_soc)
2018 {
2019 hal_soc->hw_srng_table = hw_srng_table_wcn6450;
2020 hal_hw_txrx_default_ops_attach_rh(hal_soc);
2021 hal_hw_txrx_ops_attach_wcn6450(hal_soc);
2022 }
2023