1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/of_address.h>
8 #include <linux/platform_device.h>
9 
10 #include "ccu_common.h"
11 #include "ccu_reset.h"
12 
13 #include "ccu_div.h"
14 #include "ccu_gate.h"
15 #include "ccu_mp.h"
16 #include "ccu_mult.h"
17 #include "ccu_nk.h"
18 #include "ccu_nkm.h"
19 #include "ccu_nkmp.h"
20 #include "ccu_nm.h"
21 
22 #include "ccu-sun50i-h6.h"
23 
24 /*
25  * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
26  * P should only be used for output frequencies lower than 288 MHz.
27  *
28  * For now we can just model it as a multiplier clock, and force P to /1.
29  *
30  * The M factor is present in the register's description, but not in the
31  * frequency formula, and it's documented as "M is only used for backdoor
32  * testing", so it's not modelled and then force to 0.
33  */
34 #define SUN50I_H6_PLL_CPUX_REG		0x000
35 static struct ccu_mult pll_cpux_clk = {
36 	.enable		= BIT(31),
37 	.lock		= BIT(28),
38 	.mult		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
39 	.common		= {
40 		.reg		= 0x000,
41 		.hw.init	= CLK_HW_INIT("pll-cpux", "osc24M",
42 					      &ccu_mult_ops,
43 					      CLK_SET_RATE_UNGATE),
44 	},
45 };
46 
47 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
48 #define SUN50I_H6_PLL_DDR0_REG		0x010
49 static struct ccu_nkmp pll_ddr0_clk = {
50 	.enable		= BIT(31),
51 	.lock		= BIT(28),
52 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
53 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
54 	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */
55 	.common		= {
56 		.reg		= 0x010,
57 		.hw.init	= CLK_HW_INIT("pll-ddr0", "osc24M",
58 					      &ccu_nkmp_ops,
59 					      CLK_SET_RATE_UNGATE),
60 	},
61 };
62 
63 #define SUN50I_H6_PLL_PERIPH0_REG	0x020
64 static struct ccu_nkmp pll_periph0_clk = {
65 	.enable		= BIT(31),
66 	.lock		= BIT(28),
67 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
68 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
69 	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */
70 	.fixed_post_div	= 4,
71 	.common		= {
72 		.reg		= 0x020,
73 		.features	= CCU_FEATURE_FIXED_POSTDIV,
74 		.hw.init	= CLK_HW_INIT("pll-periph0", "osc24M",
75 					      &ccu_nkmp_ops,
76 					      CLK_SET_RATE_UNGATE),
77 	},
78 };
79 
80 #define SUN50I_H6_PLL_PERIPH1_REG	0x028
81 static struct ccu_nkmp pll_periph1_clk = {
82 	.enable		= BIT(31),
83 	.lock		= BIT(28),
84 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
85 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
86 	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */
87 	.fixed_post_div	= 4,
88 	.common		= {
89 		.reg		= 0x028,
90 		.features	= CCU_FEATURE_FIXED_POSTDIV,
91 		.hw.init	= CLK_HW_INIT("pll-periph1", "osc24M",
92 					      &ccu_nkmp_ops,
93 					      CLK_SET_RATE_UNGATE),
94 	},
95 };
96 
97 #define SUN50I_H6_PLL_GPU_REG		0x030
98 static struct ccu_nkmp pll_gpu_clk = {
99 	.enable		= BIT(31),
100 	.lock		= BIT(28),
101 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
102 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
103 	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */
104 	.common		= {
105 		.reg		= 0x030,
106 		.hw.init	= CLK_HW_INIT("pll-gpu", "osc24M",
107 					      &ccu_nkmp_ops,
108 					      CLK_SET_RATE_UNGATE),
109 	},
110 };
111 
112 /*
113  * For Video PLLs, the output divider is described as "used for testing"
114  * in the user manual. So it's not modelled and forced to 0.
115  */
116 #define SUN50I_H6_PLL_VIDEO0_REG	0x040
117 static struct ccu_nm pll_video0_clk = {
118 	.enable		= BIT(31),
119 	.lock		= BIT(28),
120 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
121 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
122 	.fixed_post_div	= 4,
123 	.common		= {
124 		.reg		= 0x040,
125 		.features	= CCU_FEATURE_FIXED_POSTDIV,
126 		.hw.init	= CLK_HW_INIT("pll-video0", "osc24M",
127 					      &ccu_nm_ops,
128 					      CLK_SET_RATE_UNGATE),
129 	},
130 };
131 
132 #define SUN50I_H6_PLL_VIDEO1_REG	0x048
133 static struct ccu_nm pll_video1_clk = {
134 	.enable		= BIT(31),
135 	.lock		= BIT(28),
136 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
137 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
138 	.fixed_post_div	= 4,
139 	.common		= {
140 		.reg		= 0x048,
141 		.features	= CCU_FEATURE_FIXED_POSTDIV,
142 		.hw.init	= CLK_HW_INIT("pll-video1", "osc24M",
143 					      &ccu_nm_ops,
144 					      CLK_SET_RATE_UNGATE),
145 	},
146 };
147 
148 #define SUN50I_H6_PLL_VE_REG		0x058
149 static struct ccu_nkmp pll_ve_clk = {
150 	.enable		= BIT(31),
151 	.lock		= BIT(28),
152 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
153 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
154 	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */
155 	.common		= {
156 		.reg		= 0x058,
157 		.hw.init	= CLK_HW_INIT("pll-ve", "osc24M",
158 					      &ccu_nkmp_ops,
159 					      CLK_SET_RATE_UNGATE),
160 	},
161 };
162 
163 #define SUN50I_H6_PLL_DE_REG		0x060
164 static struct ccu_nkmp pll_de_clk = {
165 	.enable		= BIT(31),
166 	.lock		= BIT(28),
167 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
168 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
169 	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */
170 	.common		= {
171 		.reg		= 0x060,
172 		.hw.init	= CLK_HW_INIT("pll-de", "osc24M",
173 					      &ccu_nkmp_ops,
174 					      CLK_SET_RATE_UNGATE),
175 	},
176 };
177 
178 #define SUN50I_H6_PLL_HSIC_REG		0x070
179 static struct ccu_nkmp pll_hsic_clk = {
180 	.enable		= BIT(31),
181 	.lock		= BIT(28),
182 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
183 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
184 	.p		= _SUNXI_CCU_DIV(0, 1), /* output divider */
185 	.common		= {
186 		.reg		= 0x070,
187 		.hw.init	= CLK_HW_INIT("pll-hsic", "osc24M",
188 					      &ccu_nkmp_ops,
189 					      CLK_SET_RATE_UNGATE),
190 	},
191 };
192 
193 /*
194  * The Audio PLL is supposed to have 3 outputs: 2 fixed factors from
195  * the base (2x and 4x), and one variable divider (the one true pll audio).
196  *
197  * We don't have any need for the variable divider for now, so we just
198  * hardcode it to match with the clock names.
199  */
200 #define SUN50I_H6_PLL_AUDIO_REG		0x078
201 static struct ccu_nm pll_audio_base_clk = {
202 	.enable		= BIT(31),
203 	.lock		= BIT(28),
204 	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),
205 	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */
206 	.common		= {
207 		.reg		= 0x078,
208 		.hw.init	= CLK_HW_INIT("pll-audio-base", "osc24M",
209 					      &ccu_nm_ops,
210 					      CLK_SET_RATE_UNGATE),
211 	},
212 };
213 
214 static const char * const cpux_parents[] = { "osc24M", "osc32k",
215 					     "iosc", "pll-cpux" };
216 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
217 		     0x500, 24, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
218 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
219 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
220 
221 static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
222 						      "iosc", "pll-periph0" };
223 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
224 			     psi_ahb1_ahb2_parents,
225 			     0x510,
226 			     0, 2,	/* M */
227 			     8, 2,	/* P */
228 			     24, 2,	/* mux */
229 			     0);
230 
231 static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
232 						       "psi-ahb1-ahb2",
233 						       "pll-periph0" };
234 static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
235 			     0, 2,	/* M */
236 			     8, 2,	/* P */
237 			     24, 2,	/* mux */
238 			     0);
239 
240 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
241 			     0, 2,	/* M */
242 			     8, 2,	/* P */
243 			     24, 2,	/* mux */
244 			     0);
245 
246 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
247 			     0, 2,	/* M */
248 			     8, 2,	/* P */
249 			     24, 2,	/* mux */
250 			     0);
251 
252 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
253 					     "pll-ddr0", "pll-periph0-4x" };
254 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
255 				       0, 3,	/* M */
256 				       24, 2,	/* mux */
257 				       BIT(31),	/* gate */
258 				       CLK_IS_CRITICAL);
259 
260 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
261 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
262 				       0, 4,	/* M */
263 				       24, 1,	/* mux */
264 				       BIT(31),	/* gate */
265 				       0);
266 
267 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
268 		      0x60c, BIT(0), 0);
269 
270 static const char * const deinterlace_parents[] = { "pll-periph0",
271 						    "pll-periph1" };
272 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
273 				       deinterlace_parents,
274 				       0x620,
275 				       0, 4,	/* M */
276 				       24, 1,	/* mux */
277 				       BIT(31),	/* gate */
278 				       0);
279 
280 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
281 		      0x62c, BIT(0), 0);
282 
283 static const char * const gpu_parents[] = { "pll-gpu" };
284 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
285 				       0, 3,	/* M */
286 				       24, 1,	/* mux */
287 				       BIT(31),	/* gate */
288 				       0);
289 
290 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
291 		      0x67c, BIT(0), 0);
292 
293 /* Also applies to EMCE */
294 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
295 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
296 					0, 4,	/* M */
297 					8, 2,	/* N */
298 					24, 1,	/* mux */
299 					BIT(31),/* gate */
300 					0);
301 
302 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
303 		      0x68c, BIT(0), 0);
304 
305 static const char * const ve_parents[] = { "pll-ve" };
306 static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
307 				       0, 3,	/* M */
308 				       24, 1,	/* mux */
309 				       BIT(31),	/* gate */
310 				       0);
311 
312 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
313 		      0x69c, BIT(0), 0);
314 
315 static SUNXI_CCU_MP_WITH_MUX_GATE(emce_clk, "emce", ce_parents, 0x6b0,
316 					0, 4,	/* M */
317 					8, 2,	/* N */
318 					24, 1,	/* mux */
319 					BIT(31),/* gate */
320 					0);
321 
322 static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2",
323 		      0x6bc, BIT(0), 0);
324 
325 static const char * const vp9_parents[] = { "pll-ve", "pll-periph0-2x" };
326 static SUNXI_CCU_M_WITH_MUX_GATE(vp9_clk, "vp9", vp9_parents, 0x6c0,
327 				       0, 3,	/* M */
328 				       24, 1,	/* mux */
329 				       BIT(31),	/* gate */
330 				       0);
331 
332 static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2",
333 		      0x6cc, BIT(0), 0);
334 
335 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
336 		      0x70c, BIT(0), 0);
337 
338 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
339 		      0x71c, BIT(0), 0);
340 
341 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
342 		      0x72c, BIT(0), 0);
343 
344 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
345 		      0x73c, BIT(0), 0);
346 
347 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
348 
349 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
350 		      0x78c, BIT(0), 0);
351 
352 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
353 		      0x79c, BIT(0), 0);
354 
355 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
356 
357 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
358 
359 static const char * const dram_parents[] = { "pll-ddr0" };
360 static struct ccu_div dram_clk = {
361 	.div		= _SUNXI_CCU_DIV(0, 2),
362 	.mux		= _SUNXI_CCU_MUX(24, 2),
363 	.common	= {
364 		.reg		= 0x800,
365 		.hw.init	= CLK_HW_INIT_PARENTS("dram",
366 						      dram_parents,
367 						      &ccu_div_ops,
368 						      CLK_IS_CRITICAL),
369 	},
370 };
371 
372 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
373 		      0x804, BIT(0), 0);
374 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
375 		      0x804, BIT(1), 0);
376 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
377 		      0x804, BIT(2), 0);
378 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
379 		      0x804, BIT(3), 0);
380 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
381 		      0x804, BIT(5), 0);
382 static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
383 		      0x804, BIT(8), 0);
384 static SUNXI_CCU_GATE(mbus_deinterlace_clk, "mbus-deinterlace", "mbus",
385 		      0x804, BIT(11), 0);
386 
387 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
388 		      0x80c, BIT(0), CLK_IS_CRITICAL);
389 
390 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
391 					     "pll-periph1", "pll-periph0-2x",
392 					     "pll-periph1-2x" };
393 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
394 					0, 4,	/* M */
395 					8, 2,	/* N */
396 					24, 3,	/* mux */
397 					BIT(31),/* gate */
398 					0);
399 
400 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
401 					0, 4,	/* M */
402 					8, 2,	/* N */
403 					24, 3,	/* mux */
404 					BIT(31),/* gate */
405 					0);
406 
407 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
408 
409 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
410 					    "pll-periph1-2x" };
411 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_parents, 0x830,
412 					0, 4,	/* M */
413 					8, 2,	/* N */
414 					24, 3,	/* mux */
415 					BIT(31),/* gate */
416 					0);
417 
418 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_parents, 0x834,
419 					0, 4,	/* M */
420 					8, 2,	/* N */
421 					24, 3,	/* mux */
422 					BIT(31),/* gate */
423 					0);
424 
425 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_parents, 0x838,
426 					0, 4,	/* M */
427 					8, 2,	/* N */
428 					24, 3,	/* mux */
429 					BIT(31),/* gate */
430 					0);
431 
432 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
433 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
434 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
435 
436 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
437 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
438 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
439 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
440 
441 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
442 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
443 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
444 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
445 
446 static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0);
447 static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", 0x93c, BIT(1), 0);
448 
449 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
450 					0, 4,	/* M */
451 					8, 2,	/* N */
452 					24, 3,	/* mux */
453 					BIT(31),/* gate */
454 					0);
455 
456 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
457 					0, 4,	/* M */
458 					8, 2,	/* N */
459 					24, 3,	/* mux */
460 					BIT(31),/* gate */
461 					0);
462 
463 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
464 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
465 
466 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
467 
468 static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
469 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
470 					0, 4,	/* M */
471 					8, 2,	/* N */
472 					24, 1,	/* mux */
473 					BIT(31),/* gate */
474 					0);
475 
476 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
477 
478 static const char * const ir_tx_parents[] = { "osc32k", "osc24M" };
479 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_parents, 0x9c0,
480 					0, 4,	/* M */
481 					8, 2,	/* N */
482 					24, 1,	/* mux */
483 					BIT(31),/* gate */
484 					0);
485 
486 static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
487 
488 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
489 
490 static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x", "pll-audio-4x" };
491 static struct ccu_div i2s3_clk = {
492 	.enable		= BIT(31),
493 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
494 	.mux		= _SUNXI_CCU_MUX(24, 2),
495 	.common		= {
496 		.reg		= 0xa0c,
497 		.hw.init	= CLK_HW_INIT_PARENTS("i2s3",
498 						      audio_parents,
499 						      &ccu_div_ops,
500 						      0),
501 	},
502 };
503 
504 static struct ccu_div i2s0_clk = {
505 	.enable		= BIT(31),
506 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
507 	.mux		= _SUNXI_CCU_MUX(24, 2),
508 	.common		= {
509 		.reg		= 0xa10,
510 		.hw.init	= CLK_HW_INIT_PARENTS("i2s0",
511 						      audio_parents,
512 						      &ccu_div_ops,
513 						      0),
514 	},
515 };
516 
517 static struct ccu_div i2s1_clk = {
518 	.enable		= BIT(31),
519 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
520 	.mux		= _SUNXI_CCU_MUX(24, 2),
521 	.common		= {
522 		.reg		= 0xa14,
523 		.hw.init	= CLK_HW_INIT_PARENTS("i2s1",
524 						      audio_parents,
525 						      &ccu_div_ops,
526 						      0),
527 	},
528 };
529 
530 static struct ccu_div i2s2_clk = {
531 	.enable		= BIT(31),
532 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
533 	.mux		= _SUNXI_CCU_MUX(24, 2),
534 	.common		= {
535 		.reg		= 0xa18,
536 		.hw.init	= CLK_HW_INIT_PARENTS("i2s2",
537 						      audio_parents,
538 						      &ccu_div_ops,
539 						      0),
540 	},
541 };
542 
543 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa1c, BIT(0), 0);
544 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa1c, BIT(1), 0);
545 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa1c, BIT(2), 0);
546 static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa1c, BIT(3), 0);
547 
548 static struct ccu_div spdif_clk = {
549 	.enable		= BIT(31),
550 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
551 	.mux		= _SUNXI_CCU_MUX(24, 2),
552 	.common		= {
553 		.reg		= 0xa20,
554 		.hw.init	= CLK_HW_INIT_PARENTS("spdif",
555 						      audio_parents,
556 						      &ccu_div_ops,
557 						      0),
558 	},
559 };
560 
561 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
562 
563 static struct ccu_div dmic_clk = {
564 	.enable		= BIT(31),
565 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
566 	.mux		= _SUNXI_CCU_MUX(24, 2),
567 	.common		= {
568 		.reg		= 0xa40,
569 		.hw.init	= CLK_HW_INIT_PARENTS("dmic",
570 						      audio_parents,
571 						      &ccu_div_ops,
572 						      0),
573 	},
574 };
575 
576 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
577 
578 static struct ccu_div audio_hub_clk = {
579 	.enable		= BIT(31),
580 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
581 	.mux		= _SUNXI_CCU_MUX(24, 2),
582 	.common		= {
583 		.reg		= 0xa60,
584 		.hw.init	= CLK_HW_INIT_PARENTS("audio-hub",
585 						      audio_parents,
586 						      &ccu_div_ops,
587 						      0),
588 	},
589 };
590 
591 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
592 
593 /*
594  * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
595  * We will force them to 0 (12M divided from 48M).
596  */
597 #define SUN50I_H6_USB0_CLK_REG		0xa70
598 #define SUN50I_H6_USB3_CLK_REG		0xa7c
599 
600 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
601 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
602 
603 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
604 
605 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
606 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc12M", 0xa7c, BIT(29), 0);
607 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0);
608 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0xa7c, BIT(26), 0);
609 
610 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
611 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
612 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
613 static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0);
614 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
615 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
616 
617 static CLK_FIXED_FACTOR(pcie_ref_100m_clk, "pcie-ref-100M",
618 			"pll-periph0-4x", 24, 1, 0);
619 static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M",
620 		      0xab0, BIT(31), 0);
621 static SUNXI_CCU_GATE(pcie_ref_out_clk, "pcie-ref-out", "pcie-ref",
622 		      0xab0, BIT(30), 0);
623 
624 static SUNXI_CCU_M_WITH_GATE(pcie_maxi_clk, "pcie-maxi",
625 			     "pll-periph0", 0xab4,
626 			     0, 4,	/* M */
627 			     BIT(31),	/* gate */
628 			     0);
629 
630 static SUNXI_CCU_M_WITH_GATE(pcie_aux_clk, "pcie-aux", "osc24M", 0xab8,
631 			     0, 5,	/* M */
632 			     BIT(31),	/* gate */
633 			     0);
634 
635 static SUNXI_CCU_GATE(bus_pcie_clk, "bus-pcie", "psi-ahb1-ahb2",
636 		      0xabc, BIT(0), 0);
637 
638 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1",
639 					      "pll-video1-4x" };
640 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00,
641 				 0, 4,		/* M */
642 				 24, 2,		/* mux */
643 				 BIT(31),	/* gate */
644 				 0);
645 
646 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
647 
648 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
649 static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = {
650 	{ .index = 1, .div = 36621 },
651 };
652 static struct ccu_mux hdmi_cec_clk = {
653 	.enable		= BIT(31),
654 
655 	.mux		= {
656 		.shift	= 24,
657 		.width	= 2,
658 
659 		.fixed_predivs	= hdmi_cec_predivs,
660 		.n_predivs	= ARRAY_SIZE(hdmi_cec_predivs),
661 	},
662 
663 	.common		= {
664 		.reg		= 0xb10,
665 		.features	= CCU_FEATURE_FIXED_PREDIV,
666 		.hw.init	= CLK_HW_INIT_PARENTS("hdmi-cec",
667 						      hdmi_cec_parents,
668 						      &ccu_mux_ops,
669 						      0),
670 	},
671 };
672 
673 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
674 
675 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
676 		      0xb5c, BIT(0), 0);
677 
678 static const char * const tcon_lcd0_parents[] = { "pll-video0",
679 						  "pll-video0-4x",
680 						  "pll-video1" };
681 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
682 			       tcon_lcd0_parents, 0xb60,
683 			       24, 3,	/* mux */
684 			       BIT(31),	/* gate */
685 			       0);
686 
687 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
688 		      0xb7c, BIT(0), 0);
689 
690 static const char * const tcon_tv0_parents[] = { "pll-video0",
691 						 "pll-video0-4x",
692 						 "pll-video1",
693 						 "pll-video1-4x" };
694 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
695 				  tcon_tv0_parents, 0xb80,
696 				  0, 4,		/* M */
697 				  8, 2,		/* P */
698 				  24, 3,	/* mux */
699 				  BIT(31),	/* gate */
700 				  0);
701 
702 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
703 		      0xb9c, BIT(0), 0);
704 
705 static SUNXI_CCU_GATE(csi_cci_clk, "csi-cci", "osc24M", 0xc00, BIT(0), 0);
706 
707 static const char * const csi_top_parents[] = { "pll-video0", "pll-ve",
708 					      "pll-periph0" };
709 static const u8 csi_top_table[] = { 0, 2, 3 };
710 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_top_clk, "csi-top",
711 				       csi_top_parents, csi_top_table, 0xc04,
712 				       0, 4,	/* M */
713 				       24, 3,	/* mux */
714 				       BIT(31),	/* gate */
715 				       0);
716 
717 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video0",
718 					       "pll-periph0", "pll-periph1" };
719 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk",
720 				 csi_mclk_parents, 0xc08,
721 				 0, 5,		/* M */
722 				 24, 3,		/* mux */
723 				 BIT(31),	/* gate */
724 				 0);
725 
726 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0);
727 
728 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
729 static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40,
730 				 0, 4,		/* M */
731 				 24, 2,		/* mux */
732 				 BIT(31),	/* gate */
733 				 0);
734 
735 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
736 
737 /* Fixed factor clocks */
738 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
739 
740 /*
741  * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
742  * fixed post-divider 2.
743  */
744 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
745 			"pll-audio-base", 8, 1, CLK_SET_RATE_PARENT);
746 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
747 			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
748 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
749 			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
750 
751 static CLK_FIXED_FACTOR(pll_periph0_4x_clk, "pll-periph0-4x",
752 			"pll-periph0", 1, 4, 0);
753 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
754 			"pll-periph0", 1, 2, 0);
755 
756 static CLK_FIXED_FACTOR(pll_periph1_4x_clk, "pll-periph1-4x",
757 			"pll-periph1", 1, 4, 0);
758 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
759 			"pll-periph1", 1, 2, 0);
760 
761 static CLK_FIXED_FACTOR(pll_video0_4x_clk, "pll-video0-4x",
762 			"pll-video0", 1, 4, CLK_SET_RATE_PARENT);
763 
764 static CLK_FIXED_FACTOR(pll_video1_4x_clk, "pll-video1-4x",
765 			"pll-video1", 1, 4, CLK_SET_RATE_PARENT);
766 
767 static struct ccu_common *sun50i_h6_ccu_clks[] = {
768 	&pll_cpux_clk.common,
769 	&pll_ddr0_clk.common,
770 	&pll_periph0_clk.common,
771 	&pll_periph1_clk.common,
772 	&pll_gpu_clk.common,
773 	&pll_video0_clk.common,
774 	&pll_video1_clk.common,
775 	&pll_ve_clk.common,
776 	&pll_de_clk.common,
777 	&pll_hsic_clk.common,
778 	&pll_audio_base_clk.common,
779 	&cpux_clk.common,
780 	&axi_clk.common,
781 	&cpux_apb_clk.common,
782 	&psi_ahb1_ahb2_clk.common,
783 	&ahb3_clk.common,
784 	&apb1_clk.common,
785 	&apb2_clk.common,
786 	&mbus_clk.common,
787 	&de_clk.common,
788 	&bus_de_clk.common,
789 	&deinterlace_clk.common,
790 	&bus_deinterlace_clk.common,
791 	&gpu_clk.common,
792 	&bus_gpu_clk.common,
793 	&ce_clk.common,
794 	&bus_ce_clk.common,
795 	&ve_clk.common,
796 	&bus_ve_clk.common,
797 	&emce_clk.common,
798 	&bus_emce_clk.common,
799 	&vp9_clk.common,
800 	&bus_vp9_clk.common,
801 	&bus_dma_clk.common,
802 	&bus_msgbox_clk.common,
803 	&bus_spinlock_clk.common,
804 	&bus_hstimer_clk.common,
805 	&avs_clk.common,
806 	&bus_dbg_clk.common,
807 	&bus_psi_clk.common,
808 	&bus_pwm_clk.common,
809 	&bus_iommu_clk.common,
810 	&dram_clk.common,
811 	&mbus_dma_clk.common,
812 	&mbus_ve_clk.common,
813 	&mbus_ce_clk.common,
814 	&mbus_ts_clk.common,
815 	&mbus_nand_clk.common,
816 	&mbus_csi_clk.common,
817 	&mbus_deinterlace_clk.common,
818 	&bus_dram_clk.common,
819 	&nand0_clk.common,
820 	&nand1_clk.common,
821 	&bus_nand_clk.common,
822 	&mmc0_clk.common,
823 	&mmc1_clk.common,
824 	&mmc2_clk.common,
825 	&bus_mmc0_clk.common,
826 	&bus_mmc1_clk.common,
827 	&bus_mmc2_clk.common,
828 	&bus_uart0_clk.common,
829 	&bus_uart1_clk.common,
830 	&bus_uart2_clk.common,
831 	&bus_uart3_clk.common,
832 	&bus_i2c0_clk.common,
833 	&bus_i2c1_clk.common,
834 	&bus_i2c2_clk.common,
835 	&bus_i2c3_clk.common,
836 	&bus_scr0_clk.common,
837 	&bus_scr1_clk.common,
838 	&spi0_clk.common,
839 	&spi1_clk.common,
840 	&bus_spi0_clk.common,
841 	&bus_spi1_clk.common,
842 	&bus_emac_clk.common,
843 	&ts_clk.common,
844 	&bus_ts_clk.common,
845 	&ir_tx_clk.common,
846 	&bus_ir_tx_clk.common,
847 	&bus_ths_clk.common,
848 	&i2s3_clk.common,
849 	&i2s0_clk.common,
850 	&i2s1_clk.common,
851 	&i2s2_clk.common,
852 	&bus_i2s0_clk.common,
853 	&bus_i2s1_clk.common,
854 	&bus_i2s2_clk.common,
855 	&bus_i2s3_clk.common,
856 	&spdif_clk.common,
857 	&bus_spdif_clk.common,
858 	&dmic_clk.common,
859 	&bus_dmic_clk.common,
860 	&audio_hub_clk.common,
861 	&bus_audio_hub_clk.common,
862 	&usb_ohci0_clk.common,
863 	&usb_phy0_clk.common,
864 	&usb_phy1_clk.common,
865 	&usb_ohci3_clk.common,
866 	&usb_phy3_clk.common,
867 	&usb_hsic_12m_clk.common,
868 	&usb_hsic_clk.common,
869 	&bus_ohci0_clk.common,
870 	&bus_ohci3_clk.common,
871 	&bus_ehci0_clk.common,
872 	&bus_xhci_clk.common,
873 	&bus_ehci3_clk.common,
874 	&bus_otg_clk.common,
875 	&pcie_ref_clk.common,
876 	&pcie_ref_out_clk.common,
877 	&pcie_maxi_clk.common,
878 	&pcie_aux_clk.common,
879 	&bus_pcie_clk.common,
880 	&hdmi_clk.common,
881 	&hdmi_slow_clk.common,
882 	&hdmi_cec_clk.common,
883 	&bus_hdmi_clk.common,
884 	&bus_tcon_top_clk.common,
885 	&tcon_lcd0_clk.common,
886 	&bus_tcon_lcd0_clk.common,
887 	&tcon_tv0_clk.common,
888 	&bus_tcon_tv0_clk.common,
889 	&csi_cci_clk.common,
890 	&csi_top_clk.common,
891 	&csi_mclk_clk.common,
892 	&bus_csi_clk.common,
893 	&hdcp_clk.common,
894 	&bus_hdcp_clk.common,
895 };
896 
897 static struct clk_hw_onecell_data sun50i_h6_hw_clks = {
898 	.hws	= {
899 		[CLK_OSC12M]		= &osc12M_clk.hw,
900 		[CLK_PLL_CPUX]		= &pll_cpux_clk.common.hw,
901 		[CLK_PLL_DDR0]		= &pll_ddr0_clk.common.hw,
902 		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
903 		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
904 		[CLK_PLL_PERIPH0_4X]	= &pll_periph0_4x_clk.hw,
905 		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
906 		[CLK_PLL_PERIPH1_2X]	= &pll_periph1_2x_clk.hw,
907 		[CLK_PLL_PERIPH1_4X]	= &pll_periph1_4x_clk.hw,
908 		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
909 		[CLK_PLL_VIDEO0]	= &pll_video0_clk.common.hw,
910 		[CLK_PLL_VIDEO0_4X]	= &pll_video0_4x_clk.hw,
911 		[CLK_PLL_VIDEO1]	= &pll_video1_clk.common.hw,
912 		[CLK_PLL_VIDEO1_4X]	= &pll_video1_4x_clk.hw,
913 		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
914 		[CLK_PLL_DE]		= &pll_de_clk.common.hw,
915 		[CLK_PLL_HSIC]		= &pll_hsic_clk.common.hw,
916 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
917 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
918 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
919 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
920 		[CLK_CPUX]		= &cpux_clk.common.hw,
921 		[CLK_AXI]		= &axi_clk.common.hw,
922 		[CLK_CPUX_APB]		= &cpux_apb_clk.common.hw,
923 		[CLK_PSI_AHB1_AHB2]	= &psi_ahb1_ahb2_clk.common.hw,
924 		[CLK_AHB3]		= &ahb3_clk.common.hw,
925 		[CLK_APB1]		= &apb1_clk.common.hw,
926 		[CLK_APB2]		= &apb2_clk.common.hw,
927 		[CLK_MBUS]		= &mbus_clk.common.hw,
928 		[CLK_DE]		= &de_clk.common.hw,
929 		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
930 		[CLK_DEINTERLACE]	= &deinterlace_clk.common.hw,
931 		[CLK_BUS_DEINTERLACE]	= &bus_deinterlace_clk.common.hw,
932 		[CLK_GPU]		= &gpu_clk.common.hw,
933 		[CLK_BUS_GPU]		= &bus_gpu_clk.common.hw,
934 		[CLK_CE]		= &ce_clk.common.hw,
935 		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
936 		[CLK_VE]		= &ve_clk.common.hw,
937 		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
938 		[CLK_EMCE]		= &emce_clk.common.hw,
939 		[CLK_BUS_EMCE]		= &bus_emce_clk.common.hw,
940 		[CLK_VP9]		= &vp9_clk.common.hw,
941 		[CLK_BUS_VP9]		= &bus_vp9_clk.common.hw,
942 		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
943 		[CLK_BUS_MSGBOX]	= &bus_msgbox_clk.common.hw,
944 		[CLK_BUS_SPINLOCK]	= &bus_spinlock_clk.common.hw,
945 		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
946 		[CLK_AVS]		= &avs_clk.common.hw,
947 		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
948 		[CLK_BUS_PSI]		= &bus_psi_clk.common.hw,
949 		[CLK_BUS_PWM]		= &bus_pwm_clk.common.hw,
950 		[CLK_BUS_IOMMU]		= &bus_iommu_clk.common.hw,
951 		[CLK_DRAM]		= &dram_clk.common.hw,
952 		[CLK_MBUS_DMA]		= &mbus_dma_clk.common.hw,
953 		[CLK_MBUS_VE]		= &mbus_ve_clk.common.hw,
954 		[CLK_MBUS_CE]		= &mbus_ce_clk.common.hw,
955 		[CLK_MBUS_TS]		= &mbus_ts_clk.common.hw,
956 		[CLK_MBUS_NAND]		= &mbus_nand_clk.common.hw,
957 		[CLK_MBUS_CSI]		= &mbus_csi_clk.common.hw,
958 		[CLK_MBUS_DEINTERLACE]	= &mbus_deinterlace_clk.common.hw,
959 		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
960 		[CLK_NAND0]		= &nand0_clk.common.hw,
961 		[CLK_NAND1]		= &nand1_clk.common.hw,
962 		[CLK_BUS_NAND]		= &bus_nand_clk.common.hw,
963 		[CLK_MMC0]		= &mmc0_clk.common.hw,
964 		[CLK_MMC1]		= &mmc1_clk.common.hw,
965 		[CLK_MMC2]		= &mmc2_clk.common.hw,
966 		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
967 		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
968 		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
969 		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
970 		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
971 		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
972 		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
973 		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
974 		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
975 		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
976 		[CLK_BUS_I2C3]		= &bus_i2c3_clk.common.hw,
977 		[CLK_BUS_SCR0]		= &bus_scr0_clk.common.hw,
978 		[CLK_BUS_SCR1]		= &bus_scr1_clk.common.hw,
979 		[CLK_SPI0]		= &spi0_clk.common.hw,
980 		[CLK_SPI1]		= &spi1_clk.common.hw,
981 		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
982 		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
983 		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
984 		[CLK_TS]		= &ts_clk.common.hw,
985 		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
986 		[CLK_IR_TX]		= &ir_tx_clk.common.hw,
987 		[CLK_BUS_IR_TX]		= &bus_ir_tx_clk.common.hw,
988 		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
989 		[CLK_I2S3]		= &i2s3_clk.common.hw,
990 		[CLK_I2S0]		= &i2s0_clk.common.hw,
991 		[CLK_I2S1]		= &i2s1_clk.common.hw,
992 		[CLK_I2S2]		= &i2s2_clk.common.hw,
993 		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
994 		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
995 		[CLK_BUS_I2S2]		= &bus_i2s2_clk.common.hw,
996 		[CLK_BUS_I2S3]		= &bus_i2s3_clk.common.hw,
997 		[CLK_SPDIF]		= &spdif_clk.common.hw,
998 		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,
999 		[CLK_DMIC]		= &dmic_clk.common.hw,
1000 		[CLK_BUS_DMIC]		= &bus_dmic_clk.common.hw,
1001 		[CLK_AUDIO_HUB]		= &audio_hub_clk.common.hw,
1002 		[CLK_BUS_AUDIO_HUB]	= &bus_audio_hub_clk.common.hw,
1003 		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
1004 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
1005 		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
1006 		[CLK_USB_OHCI3]		= &usb_ohci3_clk.common.hw,
1007 		[CLK_USB_PHY3]		= &usb_phy3_clk.common.hw,
1008 		[CLK_USB_HSIC_12M]	= &usb_hsic_12m_clk.common.hw,
1009 		[CLK_USB_HSIC]		= &usb_hsic_clk.common.hw,
1010 		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
1011 		[CLK_BUS_OHCI3]		= &bus_ohci3_clk.common.hw,
1012 		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
1013 		[CLK_BUS_XHCI]		= &bus_xhci_clk.common.hw,
1014 		[CLK_BUS_EHCI3]		= &bus_ehci3_clk.common.hw,
1015 		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
1016 		[CLK_PCIE_REF_100M]	= &pcie_ref_100m_clk.hw,
1017 		[CLK_PCIE_REF]		= &pcie_ref_clk.common.hw,
1018 		[CLK_PCIE_REF_OUT]	= &pcie_ref_out_clk.common.hw,
1019 		[CLK_PCIE_MAXI]		= &pcie_maxi_clk.common.hw,
1020 		[CLK_PCIE_AUX]		= &pcie_aux_clk.common.hw,
1021 		[CLK_BUS_PCIE]		= &bus_pcie_clk.common.hw,
1022 		[CLK_HDMI]		= &hdmi_clk.common.hw,
1023 		[CLK_HDMI_SLOW]		= &hdmi_slow_clk.common.hw,
1024 		[CLK_HDMI_CEC]		= &hdmi_cec_clk.common.hw,
1025 		[CLK_BUS_HDMI]		= &bus_hdmi_clk.common.hw,
1026 		[CLK_BUS_TCON_TOP]	= &bus_tcon_top_clk.common.hw,
1027 		[CLK_TCON_LCD0]		= &tcon_lcd0_clk.common.hw,
1028 		[CLK_BUS_TCON_LCD0]	= &bus_tcon_lcd0_clk.common.hw,
1029 		[CLK_TCON_TV0]		= &tcon_tv0_clk.common.hw,
1030 		[CLK_BUS_TCON_TV0]	= &bus_tcon_tv0_clk.common.hw,
1031 		[CLK_CSI_CCI]		= &csi_cci_clk.common.hw,
1032 		[CLK_CSI_TOP]		= &csi_top_clk.common.hw,
1033 		[CLK_CSI_MCLK]		= &csi_mclk_clk.common.hw,
1034 		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
1035 		[CLK_HDCP]		= &hdcp_clk.common.hw,
1036 		[CLK_BUS_HDCP]		= &bus_hdcp_clk.common.hw,
1037 	},
1038 	.num = CLK_NUMBER,
1039 };
1040 
1041 static struct ccu_reset_map sun50i_h6_ccu_resets[] = {
1042 	[RST_MBUS]		= { 0x540, BIT(30) },
1043 
1044 	[RST_BUS_DE]		= { 0x60c, BIT(16) },
1045 	[RST_BUS_DEINTERLACE]	= { 0x62c, BIT(16) },
1046 	[RST_BUS_GPU]		= { 0x67c, BIT(16) },
1047 	[RST_BUS_CE]		= { 0x68c, BIT(16) },
1048 	[RST_BUS_VE]		= { 0x69c, BIT(16) },
1049 	[RST_BUS_EMCE]		= { 0x6bc, BIT(16) },
1050 	[RST_BUS_VP9]		= { 0x6cc, BIT(16) },
1051 	[RST_BUS_DMA]		= { 0x70c, BIT(16) },
1052 	[RST_BUS_MSGBOX]	= { 0x71c, BIT(16) },
1053 	[RST_BUS_SPINLOCK]	= { 0x72c, BIT(16) },
1054 	[RST_BUS_HSTIMER]	= { 0x73c, BIT(16) },
1055 	[RST_BUS_DBG]		= { 0x78c, BIT(16) },
1056 	[RST_BUS_PSI]		= { 0x79c, BIT(16) },
1057 	[RST_BUS_PWM]		= { 0x7ac, BIT(16) },
1058 	[RST_BUS_IOMMU]		= { 0x7bc, BIT(16) },
1059 	[RST_BUS_DRAM]		= { 0x80c, BIT(16) },
1060 	[RST_BUS_NAND]		= { 0x82c, BIT(16) },
1061 	[RST_BUS_MMC0]		= { 0x84c, BIT(16) },
1062 	[RST_BUS_MMC1]		= { 0x84c, BIT(17) },
1063 	[RST_BUS_MMC2]		= { 0x84c, BIT(18) },
1064 	[RST_BUS_UART0]		= { 0x90c, BIT(16) },
1065 	[RST_BUS_UART1]		= { 0x90c, BIT(17) },
1066 	[RST_BUS_UART2]		= { 0x90c, BIT(18) },
1067 	[RST_BUS_UART3]		= { 0x90c, BIT(19) },
1068 	[RST_BUS_I2C0]		= { 0x91c, BIT(16) },
1069 	[RST_BUS_I2C1]		= { 0x91c, BIT(17) },
1070 	[RST_BUS_I2C2]		= { 0x91c, BIT(18) },
1071 	[RST_BUS_I2C3]		= { 0x91c, BIT(19) },
1072 	[RST_BUS_SCR0]		= { 0x93c, BIT(16) },
1073 	[RST_BUS_SCR1]		= { 0x93c, BIT(17) },
1074 	[RST_BUS_SPI0]		= { 0x96c, BIT(16) },
1075 	[RST_BUS_SPI1]		= { 0x96c, BIT(17) },
1076 	[RST_BUS_EMAC]		= { 0x97c, BIT(16) },
1077 	[RST_BUS_TS]		= { 0x9bc, BIT(16) },
1078 	[RST_BUS_IR_TX]		= { 0x9cc, BIT(16) },
1079 	[RST_BUS_THS]		= { 0x9fc, BIT(16) },
1080 	[RST_BUS_I2S0]		= { 0xa1c, BIT(16) },
1081 	[RST_BUS_I2S1]		= { 0xa1c, BIT(17) },
1082 	[RST_BUS_I2S2]		= { 0xa1c, BIT(18) },
1083 	[RST_BUS_I2S3]		= { 0xa1c, BIT(19) },
1084 	[RST_BUS_SPDIF]		= { 0xa2c, BIT(16) },
1085 	[RST_BUS_DMIC]		= { 0xa4c, BIT(16) },
1086 	[RST_BUS_AUDIO_HUB]	= { 0xa6c, BIT(16) },
1087 
1088 	[RST_USB_PHY0]		= { 0xa70, BIT(30) },
1089 	[RST_USB_PHY1]		= { 0xa74, BIT(30) },
1090 	[RST_USB_PHY3]		= { 0xa7c, BIT(30) },
1091 	[RST_USB_HSIC]		= { 0xa7c, BIT(28) },
1092 
1093 	[RST_BUS_OHCI0]		= { 0xa8c, BIT(16) },
1094 	[RST_BUS_OHCI3]		= { 0xa8c, BIT(19) },
1095 	[RST_BUS_EHCI0]		= { 0xa8c, BIT(20) },
1096 	[RST_BUS_XHCI]		= { 0xa8c, BIT(21) },
1097 	[RST_BUS_EHCI3]		= { 0xa8c, BIT(23) },
1098 	[RST_BUS_OTG]		= { 0xa8c, BIT(24) },
1099 	[RST_BUS_PCIE]		= { 0xabc, BIT(16) },
1100 
1101 	[RST_PCIE_POWERUP]	= { 0xabc, BIT(17) },
1102 
1103 	[RST_BUS_HDMI]		= { 0xb1c, BIT(16) },
1104 	[RST_BUS_HDMI_SUB]	= { 0xb1c, BIT(17) },
1105 	[RST_BUS_TCON_TOP]	= { 0xb5c, BIT(16) },
1106 	[RST_BUS_TCON_LCD0]	= { 0xb7c, BIT(16) },
1107 	[RST_BUS_TCON_TV0]	= { 0xb9c, BIT(16) },
1108 	[RST_BUS_CSI]		= { 0xc2c, BIT(16) },
1109 	[RST_BUS_HDCP]		= { 0xc4c, BIT(16) },
1110 };
1111 
1112 static const struct sunxi_ccu_desc sun50i_h6_ccu_desc = {
1113 	.ccu_clks	= sun50i_h6_ccu_clks,
1114 	.num_ccu_clks	= ARRAY_SIZE(sun50i_h6_ccu_clks),
1115 
1116 	.hw_clks	= &sun50i_h6_hw_clks,
1117 
1118 	.resets		= sun50i_h6_ccu_resets,
1119 	.num_resets	= ARRAY_SIZE(sun50i_h6_ccu_resets),
1120 };
1121 
1122 static const u32 pll_regs[] = {
1123 	SUN50I_H6_PLL_CPUX_REG,
1124 	SUN50I_H6_PLL_DDR0_REG,
1125 	SUN50I_H6_PLL_PERIPH0_REG,
1126 	SUN50I_H6_PLL_PERIPH1_REG,
1127 	SUN50I_H6_PLL_GPU_REG,
1128 	SUN50I_H6_PLL_VIDEO0_REG,
1129 	SUN50I_H6_PLL_VIDEO1_REG,
1130 	SUN50I_H6_PLL_VE_REG,
1131 	SUN50I_H6_PLL_DE_REG,
1132 	SUN50I_H6_PLL_HSIC_REG,
1133 	SUN50I_H6_PLL_AUDIO_REG,
1134 };
1135 
1136 static const u32 pll_video_regs[] = {
1137 	SUN50I_H6_PLL_VIDEO0_REG,
1138 	SUN50I_H6_PLL_VIDEO1_REG,
1139 };
1140 
1141 static const u32 usb2_clk_regs[] = {
1142 	SUN50I_H6_USB0_CLK_REG,
1143 	SUN50I_H6_USB3_CLK_REG,
1144 };
1145 
sun50i_h6_ccu_probe(struct platform_device * pdev)1146 static int sun50i_h6_ccu_probe(struct platform_device *pdev)
1147 {
1148 	struct resource *res;
1149 	void __iomem *reg;
1150 	u32 val;
1151 	int i;
1152 
1153 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1154 	reg = devm_ioremap_resource(&pdev->dev, res);
1155 	if (IS_ERR(reg))
1156 		return PTR_ERR(reg);
1157 
1158 	/* Enable the lock bits on all PLLs */
1159 	for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
1160 		val = readl(reg + pll_regs[i]);
1161 		val |= BIT(29);
1162 		writel(val, reg + pll_regs[i]);
1163 	}
1164 
1165 	/*
1166 	 * Force the output divider of video PLLs to 0.
1167 	 *
1168 	 * See the comment before pll-video0 definition for the reason.
1169 	 */
1170 	for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
1171 		val = readl(reg + pll_video_regs[i]);
1172 		val &= ~BIT(0);
1173 		writel(val, reg + pll_video_regs[i]);
1174 	}
1175 
1176 	/*
1177 	 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
1178 	 *
1179 	 * This clock mux is still mysterious, and the code just enforces
1180 	 * it to have a valid clock parent.
1181 	 */
1182 	for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) {
1183 		val = readl(reg + usb2_clk_regs[i]);
1184 		val &= ~GENMASK(25, 24);
1185 		writel (val, reg + usb2_clk_regs[i]);
1186 	}
1187 
1188 	/*
1189 	 * Force the post-divider of pll-audio to 8 and the output divider
1190 	 * of it to 1, to make the clock name represents the real frequency.
1191 	 */
1192 	val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
1193 	val &= ~(GENMASK(21, 16) | BIT(0));
1194 	writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
1195 
1196 	return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc);
1197 }
1198 
1199 static const struct of_device_id sun50i_h6_ccu_ids[] = {
1200 	{ .compatible = "allwinner,sun50i-h6-ccu" },
1201 	{ }
1202 };
1203 
1204 static struct platform_driver sun50i_h6_ccu_driver = {
1205 	.probe	= sun50i_h6_ccu_probe,
1206 	.driver	= {
1207 		.name	= "sun50i-h6-ccu",
1208 		.of_match_table	= sun50i_h6_ccu_ids,
1209 	},
1210 };
1211 builtin_platform_driver(sun50i_h6_ccu_driver);
1212