xref: /wlan-driver/platform/icnss2/power.c (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/of.h>
9 #include <linux/pinctrl/consumer.h>
10 #include <linux/regulator/consumer.h>
11 #include <soc/qcom/cmd-db.h>
12 #include "main.h"
13 #include "qmi.h"
14 #include "debug.h"
15 #include "power.h"
16 #if IS_ENABLED(CONFIG_MSM_QMP)
17 #include <linux/soc/qcom/qcom_aoss.h>
18 #endif
19 
20 static struct icnss_vreg_cfg icnss_wcn6750_vreg_list[] = {
21 	{"vdd-cx-mx", 824000, 952000, 0, 0, 0, false, true},
22 	{"vdd-1.8-xo", 1872000, 1872000, 0, 0, 0, false, true},
23 	{"vdd-1.3-rfa", 1256000, 1352000, 0, 0, 0, false, true},
24 	{"vdd-ipa-2p2", 2200000, 2200000, 0, 0, 0, false, true},
25 };
26 
27 static struct icnss_vreg_cfg icnss_adrestea_vreg_list[] = {
28 	{"vdd-cx-mx", 752000, 752000, 0, 0, 0, false, true},
29 	{"vdd-1.8-xo", 1800000, 1800000, 0, 0, 0, false, true},
30 	{"vdd-1.3-rfa", 1304000, 1304000, 0, 0, 0, false, true},
31 	{"vdd-3.3-ch1", 3312000, 3312000, 0, 0, 0, false, false},
32 	{"vdd-3.3-ch0", 3312000, 3312000, 0, 0, 0, false, true},
33 };
34 
35 static struct icnss_battery_level icnss_battery_level[] = {
36 	{70, 3300000},
37 	{60, 3200000},
38 	{50, 3100000},
39 	{25, 3000000},
40 	{0, 2850000},
41 };
42 
43 static struct icnss_vreg_cfg icnss_wcn6450_vreg_list[] = {
44 	{"vdd-cx-mx", 824000, 952000, 0, 0, 0, false, true},
45 	{"vdd-1.8-xo", 1872000, 1872000, 0, 0, 0, false, true},
46 	{"vdd-1.3-rfa", 1256000, 1352000, 0, 0, 0, false, true},
47 	{"vdd-aon", 1256000, 1352000, 0, 0, 0, false, true},
48 };
49 
50 static struct icnss_clk_cfg icnss_clk_list[] = {
51 	{"rf_clk", 0, 0},
52 };
53 
54 static struct icnss_clk_cfg icnss_adrestea_clk_list[] = {
55 	{"cxo_ref_clk_pin", 0, 0},
56 };
57 
58 #define ICNSS_VREG_LIST_SIZE		ARRAY_SIZE(icnss_wcn6750_vreg_list)
59 #define ICNSS_VREG_ADRESTEA_LIST_SIZE	ARRAY_SIZE(icnss_adrestea_vreg_list)
60 #define ICNSS_VREG_EVROS_LIST_SIZE	ARRAY_SIZE(icnss_wcn6450_vreg_list)
61 #define ICNSS_CLK_LIST_SIZE		ARRAY_SIZE(icnss_clk_list)
62 #define ICNSS_CLK_ADRESTEA_LIST_SIZE	ARRAY_SIZE(icnss_adrestea_clk_list)
63 
64 #define ICNSS_CHAIN1_REGULATOR                          "vdd-3.3-ch1"
65 #define MAX_PROP_SIZE					32
66 
67 #define BT_CXMX_VOLTAGE_MV		950
68 #define ICNSS_MBOX_MSG_MAX_LEN 64
69 #define ICNSS_MBOX_TIMEOUT_MS 1000
70 
71 #define ICNSS_BATTERY_LEVEL_COUNT	ARRAY_SIZE(icnss_battery_level)
72 #define ICNSS_MAX_BATTERY_LEVEL		100
73 
74 /**
75  * enum icnss_vreg_param: Voltage regulator TCS param
76  * @ICNSS_VREG_VOLTAGE: Provides voltage level to be configured in TCS
77  * @ICNSS_VREG_MODE: Regulator mode
78  * @ICNSS_VREG_ENABLE: Set Voltage regulator enable config in TCS
79  */
80 enum icnss_vreg_param {
81 	ICNSS_VREG_VOLTAGE,
82 	ICNSS_VREG_MODE,
83 	ICNSS_VREG_ENABLE,
84 };
85 
86 /**
87  * enum icnss_tcs_seq: TCS sequence ID for trigger
88  * ICNSS_TCS_UP_SEQ: TCS Sequence based on up trigger / Wake TCS
89  * ICNSS_TCS_DOWN_SEQ: TCS Sequence based on down trigger / Sleep TCS
90  * ICNSS_TCS_ALL_SEQ: Update for both up and down triggers
91  */
92 enum icnss_tcs_seq {
93 	ICNSS_TCS_UP_SEQ,
94 	ICNSS_TCS_DOWN_SEQ,
95 	ICNSS_TCS_ALL_SEQ,
96 };
97 
icnss_get_vreg_single(struct icnss_priv * priv,struct icnss_vreg_info * vreg)98 static int icnss_get_vreg_single(struct icnss_priv *priv,
99 				 struct icnss_vreg_info *vreg)
100 {
101 	int ret = 0;
102 	struct device *dev = NULL;
103 	struct regulator *reg = NULL;
104 	const __be32 *prop = NULL;
105 	char prop_name[MAX_PROP_SIZE] = {0};
106 	int len = 0;
107 	int i;
108 
109 	dev = &priv->pdev->dev;
110 
111 	reg = devm_regulator_get_optional(dev, vreg->cfg.name);
112 	if (IS_ERR(reg)) {
113 		ret = PTR_ERR(reg);
114 		if (ret == -ENODEV) {
115 			return ret;
116 		} else if (ret == -EPROBE_DEFER) {
117 			icnss_pr_info("EPROBE_DEFER for regulator: %s\n",
118 				      vreg->cfg.name);
119 			goto out;
120 		} else if (priv->device_id == ADRASTEA_DEVICE_ID) {
121 			if (vreg->cfg.required) {
122 				icnss_pr_err("Regulator %s doesn't exist: %d\n",
123 					     vreg->cfg.name, ret);
124 			goto out;
125 			} else {
126 				icnss_pr_dbg("Optional regulator %s doesn't exist: %d\n",
127 					     vreg->cfg.name, ret);
128 				goto done;
129 			}
130 		} else {
131 			icnss_pr_err("Failed to get regulator %s, err = %d\n",
132 				     vreg->cfg.name, ret);
133 			goto out;
134 		}
135 	}
136 
137 	vreg->reg = reg;
138 
139 	snprintf(prop_name, MAX_PROP_SIZE, "qcom,%s-config",
140 		 vreg->cfg.name);
141 
142 	prop = of_get_property(dev->of_node, prop_name, &len);
143 
144 	icnss_pr_dbg("Got regulator config, prop: %s, len: %d\n",
145 		     prop_name, len);
146 
147 	if (!prop || len < (2 * sizeof(__be32))) {
148 		icnss_pr_dbg("Property %s %s, use default\n", prop_name,
149 			     prop ? "invalid format" : "doesn't exist");
150 		goto done;
151 	}
152 
153 	for (i = 0; (i * sizeof(__be32)) < len; i++) {
154 		switch (i) {
155 		case 0:
156 			vreg->cfg.min_uv = be32_to_cpup(&prop[0]);
157 			break;
158 		case 1:
159 			vreg->cfg.max_uv = be32_to_cpup(&prop[1]);
160 			break;
161 		case 2:
162 			vreg->cfg.load_ua = be32_to_cpup(&prop[2]);
163 			break;
164 		case 3:
165 			vreg->cfg.delay_us = be32_to_cpup(&prop[3]);
166 			break;
167 		case 4:
168 			if (priv->device_id == WCN6750_DEVICE_ID)
169 				vreg->cfg.need_unvote = be32_to_cpup(&prop[4]);
170 			else
171 				vreg->cfg.need_unvote = 0;
172 			break;
173 		default:
174 			icnss_pr_dbg("Property %s, ignoring value at %d\n",
175 				     prop_name, i);
176 			break;
177 		}
178 	}
179 
180 done:
181 	icnss_pr_dbg("Got regulator: %s, min_uv: %u, max_uv: %u, load_ua: %u, delay_us: %u, need_unvote: %u\n",
182 		     vreg->cfg.name, vreg->cfg.min_uv,
183 		     vreg->cfg.max_uv, vreg->cfg.load_ua,
184 		     vreg->cfg.delay_us, vreg->cfg.need_unvote);
185 
186 	return 0;
187 
188 out:
189 	return ret;
190 }
191 
icnss_vreg_on_single(struct icnss_vreg_info * vreg)192 static int icnss_vreg_on_single(struct icnss_vreg_info *vreg)
193 {
194 	int ret = 0;
195 
196 	if (vreg->enabled) {
197 		icnss_pr_dbg("Regulator %s is already enabled\n",
198 			     vreg->cfg.name);
199 		return 0;
200 	}
201 
202 	icnss_pr_dbg("Regulator %s is being enabled\n", vreg->cfg.name);
203 
204 	if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
205 		ret = regulator_set_voltage(vreg->reg,
206 					    vreg->cfg.min_uv,
207 					    vreg->cfg.max_uv);
208 
209 		if (ret) {
210 			icnss_pr_err("Failed to set voltage for regulator %s, min_uv: %u, max_uv: %u, err = %d\n",
211 				     vreg->cfg.name, vreg->cfg.min_uv,
212 				     vreg->cfg.max_uv, ret);
213 			goto out;
214 		}
215 	}
216 
217 	if (vreg->cfg.load_ua) {
218 		ret = regulator_set_load(vreg->reg,
219 					 vreg->cfg.load_ua);
220 
221 		if (ret < 0) {
222 			icnss_pr_err("Failed to set load for regulator %s, load: %u, err = %d\n",
223 				     vreg->cfg.name, vreg->cfg.load_ua,
224 				     ret);
225 			goto out;
226 		}
227 	}
228 
229 	if (vreg->cfg.delay_us)
230 		udelay(vreg->cfg.delay_us);
231 
232 	ret = regulator_enable(vreg->reg);
233 	if (ret) {
234 		icnss_pr_err("Failed to enable regulator %s, err = %d\n",
235 			     vreg->cfg.name, ret);
236 		goto out;
237 	}
238 
239 	vreg->enabled = true;
240 
241 out:
242 	return ret;
243 }
244 
icnss_vreg_unvote_single(struct icnss_vreg_info * vreg)245 static int icnss_vreg_unvote_single(struct icnss_vreg_info *vreg)
246 {
247 	int ret = 0;
248 
249 	if (!vreg->enabled) {
250 		icnss_pr_dbg("Regulator %s is already disabled\n",
251 			     vreg->cfg.name);
252 		return 0;
253 	}
254 
255 	icnss_pr_dbg("Removing vote for Regulator %s\n", vreg->cfg.name);
256 
257 	if (vreg->cfg.load_ua) {
258 		ret = regulator_set_load(vreg->reg, 0);
259 		if (ret < 0)
260 			icnss_pr_err("Failed to set load for regulator %s, err = %d\n",
261 				     vreg->cfg.name, ret);
262 	}
263 
264 	if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
265 		ret = regulator_set_voltage(vreg->reg, 0,
266 					    vreg->cfg.max_uv);
267 		if (ret)
268 			icnss_pr_err("Failed to set voltage for regulator %s, err = %d\n",
269 				     vreg->cfg.name, ret);
270 	}
271 
272 	return ret;
273 }
274 
icnss_vreg_off_single(struct icnss_vreg_info * vreg)275 static int icnss_vreg_off_single(struct icnss_vreg_info *vreg)
276 {
277 	int ret = 0;
278 
279 	if (!vreg->enabled) {
280 		icnss_pr_dbg("Regulator %s is already disabled\n",
281 			     vreg->cfg.name);
282 		return 0;
283 	}
284 
285 	icnss_pr_dbg("Regulator %s is being disabled\n",
286 		     vreg->cfg.name);
287 
288 	ret = regulator_disable(vreg->reg);
289 	if (ret)
290 		icnss_pr_err("Failed to disable regulator %s, err = %d\n",
291 			     vreg->cfg.name, ret);
292 
293 	if (vreg->cfg.load_ua) {
294 		ret = regulator_set_load(vreg->reg, 0);
295 		if (ret < 0)
296 			icnss_pr_err("Failed to set load for regulator %s, err = %d\n",
297 				     vreg->cfg.name, ret);
298 	}
299 
300 	if (vreg->cfg.min_uv != 0 && vreg->cfg.max_uv != 0) {
301 		ret = regulator_set_voltage(vreg->reg, 0,
302 					    vreg->cfg.max_uv);
303 		if (ret)
304 			icnss_pr_err("Failed to set voltage for regulator %s, err = %d\n",
305 				     vreg->cfg.name, ret);
306 	}
307 	vreg->enabled = false;
308 
309 	return ret;
310 }
311 
get_vreg_list(u32 * vreg_list_size,unsigned long device_id)312 static struct icnss_vreg_cfg *get_vreg_list(u32 *vreg_list_size,
313 					    unsigned long device_id)
314 {
315 	switch (device_id) {
316 	case WCN6750_DEVICE_ID:
317 		*vreg_list_size = ICNSS_VREG_LIST_SIZE;
318 		return icnss_wcn6750_vreg_list;
319 
320 	case ADRASTEA_DEVICE_ID:
321 		*vreg_list_size = ICNSS_VREG_ADRESTEA_LIST_SIZE;
322 		return icnss_adrestea_vreg_list;
323 
324 	case WCN6450_DEVICE_ID:
325 		*vreg_list_size = ICNSS_VREG_EVROS_LIST_SIZE;
326 		return icnss_wcn6450_vreg_list;
327 
328 	default:
329 		icnss_pr_err("Unsupported device_id 0x%x\n", device_id);
330 		*vreg_list_size = 0;
331 		return NULL;
332 	}
333 }
334 
icnss_get_vreg(struct icnss_priv * priv)335 int icnss_get_vreg(struct icnss_priv *priv)
336 {
337 	int ret = 0;
338 	int i;
339 	struct icnss_vreg_info *vreg;
340 	struct icnss_vreg_cfg *vreg_cfg = NULL;
341 	struct list_head *vreg_list = &priv->vreg_list;
342 	struct device *dev = &priv->pdev->dev;
343 	u32 vreg_list_size = 0;
344 
345 	vreg_cfg = get_vreg_list(&vreg_list_size, priv->device_id);
346 	if (!vreg_cfg)
347 		return -EINVAL;
348 
349 	for (i = 0; i < vreg_list_size; i++) {
350 		vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
351 		if (!vreg)
352 			return -ENOMEM;
353 
354 		memcpy(&vreg->cfg, &vreg_cfg[i], sizeof(vreg->cfg));
355 		ret = icnss_get_vreg_single(priv, vreg);
356 		if (ret != 0) {
357 			if (ret == -ENODEV)
358 				continue;
359 			else
360 				return ret;
361 		}
362 		list_add_tail(&vreg->list, vreg_list);
363 	}
364 
365 	return 0;
366 }
367 
icnss_put_vreg(struct icnss_priv * priv)368 void icnss_put_vreg(struct icnss_priv *priv)
369 {
370 	struct list_head *vreg_list = &priv->vreg_list;
371 	struct icnss_vreg_info *vreg = NULL;
372 
373 	while (!list_empty(vreg_list)) {
374 		vreg = list_first_entry(vreg_list,
375 					struct icnss_vreg_info, list);
376 		list_del(&vreg->list);
377 	}
378 }
379 
icnss_vreg_on(struct icnss_priv * priv)380 static int icnss_vreg_on(struct icnss_priv *priv)
381 {
382 	struct list_head *vreg_list = &priv->vreg_list;
383 	struct icnss_vreg_info *vreg = NULL;
384 	int ret = 0;
385 
386 	list_for_each_entry(vreg, vreg_list, list) {
387 		if (IS_ERR_OR_NULL(vreg->reg) || !vreg->cfg.is_supported)
388 			continue;
389 
390 		ret = icnss_vreg_on_single(vreg);
391 		if (ret)
392 			break;
393 	}
394 
395 	if (!ret)
396 		return 0;
397 
398 	list_for_each_entry_continue_reverse(vreg, vreg_list, list) {
399 		if (IS_ERR_OR_NULL(vreg->reg) || !vreg->enabled)
400 			continue;
401 
402 		icnss_vreg_off_single(vreg);
403 	}
404 
405 	return ret;
406 }
407 
icnss_vreg_off(struct icnss_priv * priv)408 static int icnss_vreg_off(struct icnss_priv *priv)
409 {
410 	struct list_head *vreg_list = &priv->vreg_list;
411 	struct icnss_vreg_info *vreg = NULL;
412 
413 	list_for_each_entry_reverse(vreg, vreg_list, list) {
414 		if (IS_ERR_OR_NULL(vreg->reg))
415 			continue;
416 
417 		icnss_vreg_off_single(vreg);
418 	}
419 
420 	return 0;
421 }
422 
icnss_vreg_unvote(struct icnss_priv * priv)423 int icnss_vreg_unvote(struct icnss_priv *priv)
424 {
425 	struct list_head *vreg_list = &priv->vreg_list;
426 	struct icnss_vreg_info *vreg = NULL;
427 
428 	list_for_each_entry_reverse(vreg, vreg_list, list) {
429 		if (IS_ERR_OR_NULL(vreg->reg))
430 			continue;
431 
432 		if (vreg->cfg.need_unvote)
433 			icnss_vreg_unvote_single(vreg);
434 	}
435 
436 	return 0;
437 }
438 
icnss_get_clk_single(struct icnss_priv * priv,struct icnss_clk_info * clk_info)439 int icnss_get_clk_single(struct icnss_priv *priv,
440 			 struct icnss_clk_info *clk_info)
441 {
442 	struct device *dev = &priv->pdev->dev;
443 	struct clk *clk;
444 	int ret;
445 
446 	clk = devm_clk_get(dev, clk_info->cfg.name);
447 	if (IS_ERR(clk)) {
448 		ret = PTR_ERR(clk);
449 		if (clk_info->cfg.required)
450 			icnss_pr_err("Failed to get clock %s, err = %d\n",
451 				     clk_info->cfg.name, ret);
452 		else
453 			icnss_pr_dbg("Failed to get optional clock %s, err = %d\n",
454 				     clk_info->cfg.name, ret);
455 		return ret;
456 	}
457 
458 	clk_info->clk = clk;
459 	icnss_pr_dbg("Got clock: %s, freq: %u\n",
460 		     clk_info->cfg.name, clk_info->cfg.freq);
461 
462 	return 0;
463 }
464 
icnss_clk_on_single(struct icnss_clk_info * clk_info)465 static int icnss_clk_on_single(struct icnss_clk_info *clk_info)
466 {
467 	int ret;
468 
469 	if (clk_info->enabled) {
470 		icnss_pr_dbg("Clock %s is already enabled\n",
471 			     clk_info->cfg.name);
472 		return 0;
473 	}
474 
475 	icnss_pr_dbg("Clock %s is being enabled\n", clk_info->cfg.name);
476 
477 	if (clk_info->cfg.freq) {
478 		ret = clk_set_rate(clk_info->clk, clk_info->cfg.freq);
479 		if (ret) {
480 			icnss_pr_err("Failed to set frequency %u for clock %s, err = %d\n",
481 				     clk_info->cfg.freq, clk_info->cfg.name,
482 				     ret);
483 			return ret;
484 		}
485 	}
486 
487 	ret = clk_prepare_enable(clk_info->clk);
488 	if (ret) {
489 		icnss_pr_err("Failed to enable clock %s, err = %d\n",
490 			     clk_info->cfg.name, ret);
491 		return ret;
492 	}
493 
494 	clk_info->enabled = true;
495 
496 	return 0;
497 }
498 
icnss_clk_off_single(struct icnss_clk_info * clk_info)499 static int icnss_clk_off_single(struct icnss_clk_info *clk_info)
500 {
501 	if (!clk_info->enabled) {
502 		icnss_pr_dbg("Clock %s is already disabled\n",
503 			     clk_info->cfg.name);
504 		return 0;
505 	}
506 
507 	icnss_pr_dbg("Clock %s is being disabled\n", clk_info->cfg.name);
508 
509 	clk_disable_unprepare(clk_info->clk);
510 	clk_info->enabled = false;
511 
512 	return 0;
513 }
514 
icnss_get_clk(struct icnss_priv * priv)515 int icnss_get_clk(struct icnss_priv *priv)
516 {
517 	struct device *dev;
518 	struct list_head *clk_list;
519 	struct icnss_clk_info *clk_info;
520 	struct icnss_clk_cfg *clk_cfg;
521 	int ret, i;
522 	u32 clk_list_size = 0;
523 
524 	if (!priv)
525 		return -ENODEV;
526 
527 	dev = &priv->pdev->dev;
528 	clk_list = &priv->clk_list;
529 
530 	if (priv->device_id == ADRASTEA_DEVICE_ID) {
531 		clk_cfg = icnss_adrestea_clk_list;
532 		clk_list_size = ICNSS_CLK_ADRESTEA_LIST_SIZE;
533 	} else if (priv->device_id == WCN6750_DEVICE_ID ||
534 		   priv->device_id == WCN6450_DEVICE_ID) {
535 		clk_cfg = icnss_clk_list;
536 		clk_list_size = ICNSS_CLK_LIST_SIZE;
537 	}
538 
539 	if (!list_empty(clk_list)) {
540 		icnss_pr_dbg("Clocks have already been updated\n");
541 		return 0;
542 	}
543 
544 	for (i = 0; i < clk_list_size; i++) {
545 		clk_info = devm_kzalloc(dev, sizeof(*clk_info), GFP_KERNEL);
546 		if (!clk_info) {
547 			ret = -ENOMEM;
548 			goto cleanup;
549 		}
550 
551 		memcpy(&clk_info->cfg, &clk_cfg[i],
552 		       sizeof(clk_info->cfg));
553 		ret = icnss_get_clk_single(priv, clk_info);
554 		if (ret != 0) {
555 			if (clk_info->cfg.required)
556 				goto cleanup;
557 			else
558 				continue;
559 		}
560 		list_add_tail(&clk_info->list, clk_list);
561 	}
562 
563 	return 0;
564 
565 cleanup:
566 	while (!list_empty(clk_list)) {
567 		clk_info = list_first_entry(clk_list, struct icnss_clk_info,
568 					    list);
569 		list_del(&clk_info->list);
570 	}
571 
572 	return ret;
573 }
574 
icnss_put_clk(struct icnss_priv * priv)575 void icnss_put_clk(struct icnss_priv *priv)
576 {
577 	struct device *dev;
578 	struct list_head *clk_list;
579 	struct icnss_clk_info *clk_info;
580 
581 	if (!priv)
582 		return;
583 
584 	dev = &priv->pdev->dev;
585 	clk_list = &priv->clk_list;
586 
587 	while (!list_empty(clk_list)) {
588 		clk_info = list_first_entry(clk_list, struct icnss_clk_info,
589 					    list);
590 		list_del(&clk_info->list);
591 	}
592 }
593 
icnss_clk_on(struct list_head * clk_list)594 static int icnss_clk_on(struct list_head *clk_list)
595 {
596 	struct icnss_clk_info *clk_info;
597 	int ret = 0;
598 
599 	list_for_each_entry(clk_info, clk_list, list) {
600 		if (IS_ERR_OR_NULL(clk_info->clk))
601 			continue;
602 		ret = icnss_clk_on_single(clk_info);
603 		if (ret)
604 			break;
605 	}
606 
607 	if (!ret)
608 		return 0;
609 
610 	list_for_each_entry_continue_reverse(clk_info, clk_list, list) {
611 		if (IS_ERR_OR_NULL(clk_info->clk))
612 			continue;
613 
614 		icnss_clk_off_single(clk_info);
615 	}
616 
617 	return ret;
618 }
619 
icnss_clk_off(struct list_head * clk_list)620 static int icnss_clk_off(struct list_head *clk_list)
621 {
622 	struct icnss_clk_info *clk_info;
623 
624 	list_for_each_entry_reverse(clk_info, clk_list, list) {
625 		if (IS_ERR_OR_NULL(clk_info->clk))
626 			continue;
627 
628 		icnss_clk_off_single(clk_info);
629 	}
630 
631 	return 0;
632 }
633 
icnss_hw_power_on(struct icnss_priv * priv)634 int icnss_hw_power_on(struct icnss_priv *priv)
635 {
636 	int ret = 0;
637 
638 	icnss_pr_dbg("HW Power on: state: 0x%lx\n", priv->state);
639 
640 	spin_lock(&priv->on_off_lock);
641 	if (test_bit(ICNSS_POWER_ON, &priv->state)) {
642 		spin_unlock(&priv->on_off_lock);
643 		return ret;
644 	}
645 	set_bit(ICNSS_POWER_ON, &priv->state);
646 	spin_unlock(&priv->on_off_lock);
647 
648 	ret = icnss_vreg_on(priv);
649 	if (ret) {
650 		icnss_pr_err("Failed to turn on vreg, err = %d\n", ret);
651 		goto out;
652 	}
653 
654 	ret = icnss_clk_on(&priv->clk_list);
655 	if (ret)
656 		goto vreg_off;
657 
658 	return ret;
659 
660 vreg_off:
661 	icnss_vreg_off(priv);
662 out:
663 	clear_bit(ICNSS_POWER_ON, &priv->state);
664 	return ret;
665 }
666 
icnss_hw_power_off(struct icnss_priv * priv)667 int icnss_hw_power_off(struct icnss_priv *priv)
668 {
669 	int ret = 0;
670 
671 	if (test_bit(HW_ALWAYS_ON, &priv->ctrl_params.quirks))
672 		return 0;
673 
674 	if (test_bit(ICNSS_FW_DOWN, &priv->state))
675 		return 0;
676 
677 	icnss_pr_dbg("HW Power off: 0x%lx\n", priv->state);
678 
679 	spin_lock(&priv->on_off_lock);
680 	if (!test_bit(ICNSS_POWER_ON, &priv->state)) {
681 		spin_unlock(&priv->on_off_lock);
682 		return ret;
683 	}
684 	clear_bit(ICNSS_POWER_ON, &priv->state);
685 	spin_unlock(&priv->on_off_lock);
686 
687 	icnss_clk_off(&priv->clk_list);
688 
689 	ret = icnss_vreg_off(priv);
690 
691 	return ret;
692 }
693 
icnss_power_on(struct device * dev)694 int icnss_power_on(struct device *dev)
695 {
696 	struct icnss_priv *priv = dev_get_drvdata(dev);
697 
698 	if (!priv) {
699 		icnss_pr_err("Invalid drvdata: dev %pK, data %pK\n",
700 			     dev, priv);
701 		return -EINVAL;
702 	}
703 
704 	icnss_pr_dbg("Power On: 0x%lx\n", priv->state);
705 
706 	return icnss_hw_power_on(priv);
707 }
708 EXPORT_SYMBOL(icnss_power_on);
709 
icnss_power_off(struct device * dev)710 int icnss_power_off(struct device *dev)
711 {
712 	struct icnss_priv *priv = dev_get_drvdata(dev);
713 
714 	if (!priv) {
715 		icnss_pr_err("Invalid drvdata: dev %pK, data %pK\n",
716 			     dev, priv);
717 		return -EINVAL;
718 	}
719 
720 	icnss_pr_dbg("Power Off: 0x%lx\n", priv->state);
721 
722 	return icnss_hw_power_off(priv);
723 }
724 EXPORT_SYMBOL(icnss_power_off);
725 
icnss_power_on_chain1_reg(struct icnss_priv * priv)726 int icnss_power_on_chain1_reg(struct icnss_priv *priv)
727 {
728 	struct list_head *vreg_list = &priv->vreg_list;
729 	struct icnss_vreg_info *vreg = NULL;
730 	int ret = 0;
731 
732 	list_for_each_entry(vreg, vreg_list, list) {
733 		if (!strcmp(ICNSS_CHAIN1_REGULATOR, vreg->cfg.name) && priv->is_chain1_supported) {
734 			vreg->cfg.is_supported = true;
735 			ret = icnss_vreg_on_single(vreg);
736 			break;
737 		}
738 	}
739 
740 	/* Setting chain1 supported to false as chain1 regulator cfg already updated */
741 	priv->is_chain1_supported = false;
742 
743 	return ret;
744 }
745 
icnss_put_resources(struct icnss_priv * priv)746 void icnss_put_resources(struct icnss_priv *priv)
747 {
748 	icnss_put_clk(priv);
749 	icnss_put_vreg(priv);
750 }
751 
752 
753 #if IS_ENABLED(CONFIG_MSM_QMP)
754 /**
755  * icnss_aop_interface_init: Initialize AOP interface: either mbox channel or direct QMP
756  * @priv: Pointer to icnss platform data
757  *
758  * Device tree file should have either mbox or qmp configured, but not both.
759  * Based on device tree configuration setup mbox channel or QMP
760  *
761  * Return: 0 for success, otherwise error code
762 */
icnss_aop_interface_init(struct icnss_priv * priv)763 int icnss_aop_interface_init(struct icnss_priv *priv)
764 {
765 	struct mbox_client *mbox = &priv->mbox_client_data;
766 	struct mbox_chan *chan;
767 	int ret = 0, ol_cpr = 0;
768 
769 	ol_cpr = of_property_read_string(priv->pdev->dev.of_node,
770 					 "qcom,vreg_ol_cpr",
771 					 &priv->cpr_info.vreg_ol_cpr);
772 
773 	if (ol_cpr && !priv->pdc_init_table) {
774 		icnss_pr_dbg("Vreg for OL CPR and pdc_init table not configured\n");
775 		return -EINVAL;
776 	}
777 
778 	mbox->dev = &priv->pdev->dev;
779 	mbox->tx_block = true;
780 	mbox->tx_tout = ICNSS_MBOX_TIMEOUT_MS;
781 	mbox->knows_txdone = false;
782 
783 	priv->mbox_chan = NULL;
784 	priv->qmp = NULL;
785 	priv->use_direct_qmp = false;
786 	/* First try to get mbox channel, if it fails then try qmp_get
787 	 * In device tree file there should be either mboxes or qmp,
788 	 * cannot have both properties at the same time.
789 	 */
790 	chan = mbox_request_channel(mbox, 0);
791 	if (IS_ERR(chan)) {
792 		ret = PTR_ERR(chan);
793 		icnss_pr_dbg("Failed to get mbox channel with err %d\n", ret);
794 		priv->qmp = qmp_get(&priv->pdev->dev);
795 		if (IS_ERR(priv->qmp)) {
796 			icnss_pr_err("Failed to get qmp\n");
797 			return PTR_ERR(priv->qmp);
798 		} else {
799 			priv->use_direct_qmp = true;
800 			icnss_pr_dbg("QMP initialized\n");
801 		}
802 	} else {
803 		priv->mbox_chan = chan;
804 		icnss_pr_dbg("Mbox channel initialized\n");
805 	}
806 	ret = icnss_aop_pdc_reconfig(priv);
807 	if (ret)
808 		icnss_pr_err("Failed to reconfig WLAN PDC, err = %d\n", ret);
809 
810 	return ret;
811 }
812 
813 /**
814  * icnss_aop_interface_deinit: Cleanup AOP interface
815  * @priv: Pointer to icnss platform data
816  *
817  * Cleanup mbox channel or QMP whichever was configured during initialization.
818  *
819  * Return: None
820  */
icnss_aop_interface_deinit(struct icnss_priv * priv)821 void icnss_aop_interface_deinit(struct icnss_priv *priv)
822 {
823 	if (!IS_ERR_OR_NULL(priv->mbox_chan))
824 		mbox_free_channel(priv->mbox_chan);
825 
826 	if (!IS_ERR_OR_NULL(priv->qmp)) {
827 		qmp_put(priv->qmp);
828 		priv->use_direct_qmp = false;
829 	}
830 }
831 
icnss_aop_set_vreg_param(struct icnss_priv * priv,const char * vreg_name,enum icnss_vreg_param param,enum icnss_tcs_seq seq,int val)832 static int icnss_aop_set_vreg_param(struct icnss_priv *priv,
833 				    const char *vreg_name,
834 				    enum icnss_vreg_param param,
835 				    enum icnss_tcs_seq seq, int val)
836 {
837 	struct qmp_pkt pkt;
838 	char mbox_msg[ICNSS_MBOX_MSG_MAX_LEN];
839 	static const char * const vreg_param_str[] = {"v", "m", "e"};
840 	static const char *const tcs_seq_str[] = {"upval", "dwnval", "enable"};
841 	int ret = 0;
842 
843 	if (param > ICNSS_VREG_ENABLE || seq > ICNSS_TCS_ALL_SEQ || !vreg_name)
844 		return -EINVAL;
845 
846 	snprintf(mbox_msg, ICNSS_MBOX_MSG_MAX_LEN,
847 		 "{class: wlan_pdc, res: %s.%s, %s: %d}", vreg_name,
848 		 vreg_param_str[param], tcs_seq_str[seq], val);
849 	if (priv->use_direct_qmp) {
850 		icnss_pr_dbg("Sending AOP QMP msg: %s\n", mbox_msg);
851 		ret = qmp_send(priv->qmp, mbox_msg, ICNSS_MBOX_MSG_MAX_LEN);
852 		if (ret < 0)
853 			icnss_pr_err("Failed to send AOP QMP msg: %s\n", mbox_msg);
854 		else
855 			ret = 0;
856 	} else {
857 		icnss_pr_dbg("Sending AOP Mbox msg: %s\n", mbox_msg);
858 		pkt.size = ICNSS_MBOX_MSG_MAX_LEN;
859 		pkt.data = mbox_msg;
860 
861 		ret = mbox_send_message(priv->mbox_chan, &pkt);
862 		if (ret < 0)
863 			icnss_pr_err("Failed to send AOP mbox msg: %s,ret: %d\n",
864 				     mbox_msg, ret);
865 		else
866 			ret = 0;
867 	}
868 
869 	return ret;
870 }
871 
872 /* icnss_aop_pdc_reconfig: Send AOP msg to configure PDC table for WLAN device
873  * @priv: Pointer to icnss platform data
874  *
875  * Send AOP QMP or Mbox msg to configure PDC table for WLAN device
876  *
877  * Return: 0 for success, otherwise error code
878  */
icnss_aop_pdc_reconfig(struct icnss_priv * priv)879 int icnss_aop_pdc_reconfig(struct icnss_priv *priv)
880 {
881 	u32 i;
882 	int ret;
883 	char *mbox_msg;
884 	struct qmp_pkt pkt;
885 
886 	if (priv->pdc_init_table_len <= 0 || !priv->pdc_init_table)
887 		return 0;
888 
889 	icnss_pr_dbg("Setting PDC defaults for device ID: (0x%x)\n",
890 		     priv->device_id);
891 	for (i = 0; i < priv->pdc_init_table_len; i++) {
892 		mbox_msg = (char *)priv->pdc_init_table[i];
893 		if (priv->use_direct_qmp) {
894 			icnss_pr_dbg("Sending AOP QMP msg: %s\n", mbox_msg);
895 			ret = qmp_send(priv->qmp, mbox_msg,
896 				       ICNSS_MBOX_MSG_MAX_LEN);
897 			if (ret < 0)
898 				icnss_pr_err("Failed to send AOP QMP msg: %s\n",
899 					     mbox_msg);
900 			else
901 				ret = 0;
902 		} else {
903 			icnss_pr_dbg("Sending AOP Mbox msg: %s\n", mbox_msg);
904 			pkt.size = ICNSS_MBOX_MSG_MAX_LEN;
905 			pkt.data = mbox_msg;
906 
907 			ret = mbox_send_message(priv->mbox_chan, &pkt);
908 			if (ret < 0)
909 				icnss_pr_err("Failed to send AOP mbox msg: %s,ret: %d\n",
910 					     mbox_msg, ret);
911 			else
912 				ret = 0;
913 		}
914 	}
915 	return ret;
916 }
917 
918 #else
icnss_aop_interface_init(struct icnss_priv * priv)919 int icnss_aop_interface_init(struct icnss_priv *priv)
920 {
921 	return 0;
922 }
923 
icnss_aop_interface_deinit(struct icnss_priv * priv)924 void icnss_aop_interface_deinit(struct icnss_priv *priv)
925 {
926 }
927 
icnss_aop_set_vreg_param(struct icnss_priv * priv,const char * vreg_name,enum icnss_vreg_param param,enum icnss_tcs_seq seq,int val)928 static int icnss_aop_set_vreg_param(struct icnss_priv *priv,
929 				    const char *vreg_name,
930 				    enum icnss_vreg_param param,
931 				    enum icnss_tcs_seq seq, int val)
932 {
933 	return 0;
934 }
935 
icnss_aop_pdc_reconfig(struct icnss_priv * priv)936 int icnss_aop_pdc_reconfig(struct icnss_priv *priv)
937 {
938 	return 0;
939 }
940 
941 #endif
942 
icnss_power_misc_params_init(struct icnss_priv * priv)943 void icnss_power_misc_params_init(struct icnss_priv *priv)
944 {
945 	struct device *dev = &priv->pdev->dev;
946 	int ret;
947 
948 	/* common DT Entries */
949 	priv->pdc_init_table_len =
950 				of_property_count_strings(dev->of_node,
951 							  "qcom,pdc_init_table");
952 	if (priv->pdc_init_table_len > 0) {
953 		priv->pdc_init_table =
954 			kcalloc(priv->pdc_init_table_len,
955 				sizeof(char *), GFP_KERNEL);
956 		if (priv->pdc_init_table) {
957 			ret = of_property_read_string_array(dev->of_node,
958 						"qcom,pdc_init_table",
959 						priv->pdc_init_table,
960 						priv->pdc_init_table_len);
961 			if (ret < 0)
962 				icnss_pr_err("Failed to get PDC Init Table\n");
963 		} else {
964 			icnss_pr_err("Failed to alloc PDC Init Table mem\n");
965 		}
966 	} else {
967 		icnss_pr_dbg("PDC Init Table not configured\n");
968 	}
969 }
970 
icnss_update_cpr_info(struct icnss_priv * priv)971 int icnss_update_cpr_info(struct icnss_priv *priv)
972 {
973 	struct icnss_cpr_info *cpr_info = &priv->cpr_info;
974 
975 	if (!cpr_info->vreg_ol_cpr || (!priv->mbox_chan && !priv->use_direct_qmp)) {
976 		icnss_pr_dbg("Mbox channel / QMP / OL CPR Vreg not configured\n");
977 		return 0;
978 	}
979 
980 	if (cpr_info->voltage == 0) {
981 		icnss_pr_err("Voltage %dmV is not valid\n", cpr_info->voltage);
982 		return -EINVAL;
983 	}
984 
985 	cpr_info->voltage = cpr_info->voltage > BT_CXMX_VOLTAGE_MV ?
986 		cpr_info->voltage : BT_CXMX_VOLTAGE_MV;
987 
988 	return icnss_aop_set_vreg_param(priv,
989 				       cpr_info->vreg_ol_cpr,
990 				       ICNSS_VREG_VOLTAGE,
991 				       ICNSS_TCS_UP_SEQ,
992 				       cpr_info->voltage);
993 }
994 
icnss_get_battery_level(struct icnss_priv * priv)995 static int icnss_get_battery_level(struct icnss_priv *priv)
996 {
997 	int err = 0, battery_percentage = 0;
998 	union power_supply_propval psp = {0,};
999 
1000 	if (!priv->batt_psy)
1001 		priv->batt_psy = power_supply_get_by_name("battery");
1002 
1003 	if (priv->batt_psy) {
1004 		err = power_supply_get_property(priv->batt_psy,
1005 						POWER_SUPPLY_PROP_CAPACITY,
1006 						&psp);
1007 		if (err) {
1008 			icnss_pr_err("battery percentage read error:%d\n", err);
1009 			goto out;
1010 		}
1011 		battery_percentage = psp.intval;
1012 	}
1013 
1014 	icnss_pr_info("Battery Percentage: %d\n", battery_percentage);
1015 out:
1016 	return battery_percentage;
1017 }
1018 
icnss_update_soc_level(struct work_struct * work)1019 static void icnss_update_soc_level(struct work_struct *work)
1020 {
1021 	int battery_percentage = 0, current_updated_voltage = 0, err = 0;
1022 	int level_count;
1023 	struct icnss_priv *priv = container_of(work, struct icnss_priv, soc_update_work);
1024 
1025 	battery_percentage = icnss_get_battery_level(priv);
1026 	if (!battery_percentage ||
1027 	    battery_percentage > ICNSS_MAX_BATTERY_LEVEL) {
1028 		icnss_pr_err("Battery percentage read failure\n");
1029 		return;
1030 	}
1031 
1032 	for (level_count = 0; level_count < ICNSS_BATTERY_LEVEL_COUNT;
1033 	     level_count++) {
1034 		if (battery_percentage >=
1035 		    icnss_battery_level[level_count].lower_battery_threshold) {
1036 			current_updated_voltage =
1037 				icnss_battery_level[level_count].ldo_voltage;
1038 			break;
1039 		}
1040 	}
1041 
1042 	if (level_count != ICNSS_BATTERY_LEVEL_COUNT &&
1043 	    priv->last_updated_voltage != current_updated_voltage) {
1044 		err = icnss_send_vbatt_update(priv, current_updated_voltage);
1045 		if (err < 0) {
1046 			icnss_pr_err("Unable to update ldo voltage");
1047 			return;
1048 		}
1049 		priv->last_updated_voltage = current_updated_voltage;
1050 	}
1051 }
1052 
icnss_battery_supply_callback(struct notifier_block * nb,unsigned long event,void * data)1053 static int icnss_battery_supply_callback(struct notifier_block *nb,
1054 					 unsigned long event, void *data)
1055 {
1056 	struct power_supply *psy = data;
1057 	struct icnss_priv *priv = container_of(nb, struct icnss_priv,
1058 					       psf_nb);
1059 	if (strcmp(psy->desc->name, "battery"))
1060 		return NOTIFY_OK;
1061 
1062 	if (test_bit(ICNSS_WLFW_CONNECTED, &priv->state) &&
1063 	    !test_bit(ICNSS_FW_DOWN, &priv->state))
1064 		queue_work(priv->soc_update_wq, &priv->soc_update_work);
1065 
1066 	return NOTIFY_OK;
1067 }
1068 
icnss_get_psf_info(struct icnss_priv * priv)1069 int icnss_get_psf_info(struct icnss_priv *priv)
1070 {
1071 	int ret = 0;
1072 
1073 	priv->soc_update_wq = alloc_workqueue("icnss_soc_update",
1074 					      WQ_UNBOUND, 1);
1075 	if (!priv->soc_update_wq) {
1076 		icnss_pr_err("Workqueue creation failed for soc update\n");
1077 		ret = -EFAULT;
1078 		goto out;
1079 	}
1080 
1081 	priv->psf_nb.notifier_call = icnss_battery_supply_callback;
1082 	ret = power_supply_reg_notifier(&priv->psf_nb);
1083 	if (ret < 0) {
1084 		icnss_pr_err("Power supply framework registration err: %d\n",
1085 			     ret);
1086 		goto err_psf_registration;
1087 	}
1088 
1089 	INIT_WORK(&priv->soc_update_work, icnss_update_soc_level);
1090 
1091 	return 0;
1092 
1093 err_psf_registration:
1094 	destroy_workqueue(priv->soc_update_wq);
1095 out:
1096 	return ret;
1097 }
1098