1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __MACH_IMX_CLK_H
3 #define __MACH_IMX_CLK_H
4
5 #include <linux/spinlock.h>
6 #include <linux/clk-provider.h>
7
8 extern spinlock_t imx_ccm_lock;
9
10 void imx_check_clocks(struct clk *clks[], unsigned int count);
11 void imx_register_uart_clocks(struct clk ** const clks[]);
12
13 extern void imx_cscmr1_fixup(u32 *val);
14
15 enum imx_pllv1_type {
16 IMX_PLLV1_IMX1,
17 IMX_PLLV1_IMX21,
18 IMX_PLLV1_IMX25,
19 IMX_PLLV1_IMX27,
20 IMX_PLLV1_IMX31,
21 IMX_PLLV1_IMX35,
22 };
23
24 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
25 const char *parent, void __iomem *base);
26
27 struct clk *imx_clk_pllv2(const char *name, const char *parent,
28 void __iomem *base);
29
30 enum imx_pllv3_type {
31 IMX_PLLV3_GENERIC,
32 IMX_PLLV3_SYS,
33 IMX_PLLV3_USB,
34 IMX_PLLV3_USB_VF610,
35 IMX_PLLV3_AV,
36 IMX_PLLV3_ENET,
37 IMX_PLLV3_ENET_IMX7,
38 IMX_PLLV3_SYS_VF610,
39 IMX_PLLV3_DDR_IMX7,
40 };
41
42 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
43 const char *parent_name, void __iomem *base, u32 div_mask);
44
45 struct clk *clk_register_gate2(struct device *dev, const char *name,
46 const char *parent_name, unsigned long flags,
47 void __iomem *reg, u8 bit_idx, u8 cgr_val,
48 u8 clk_gate_flags, spinlock_t *lock,
49 unsigned int *share_count);
50
51 struct clk * imx_obtain_fixed_clock(
52 const char *name, unsigned long rate);
53
54 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
55 void __iomem *reg, u8 shift, u32 exclusive_mask);
56
57 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
58 void __iomem *reg, u8 idx);
59
60 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
61 void __iomem *reg, u8 shift, u8 width,
62 void __iomem *busy_reg, u8 busy_shift);
63
64 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
65 u8 width, void __iomem *busy_reg, u8 busy_shift,
66 const char * const *parent_names, int num_parents);
67
68 struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
69 void __iomem *reg, u8 shift, u8 width,
70 void (*fixup)(u32 *val));
71
72 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
73 u8 shift, u8 width, const char * const *parents,
74 int num_parents, void (*fixup)(u32 *val));
75
imx_clk_fixed(const char * name,int rate)76 static inline struct clk *imx_clk_fixed(const char *name, int rate)
77 {
78 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
79 }
80
imx_clk_mux_ldb(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)81 static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
82 u8 shift, u8 width, const char * const *parents,
83 int num_parents)
84 {
85 return clk_register_mux(NULL, name, parents, num_parents,
86 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
87 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
88 }
89
imx_clk_fixed_factor(const char * name,const char * parent,unsigned int mult,unsigned int div)90 static inline struct clk *imx_clk_fixed_factor(const char *name,
91 const char *parent, unsigned int mult, unsigned int div)
92 {
93 return clk_register_fixed_factor(NULL, name, parent,
94 CLK_SET_RATE_PARENT, mult, div);
95 }
96
imx_clk_divider(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width)97 static inline struct clk *imx_clk_divider(const char *name, const char *parent,
98 void __iomem *reg, u8 shift, u8 width)
99 {
100 return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
101 reg, shift, width, 0, &imx_ccm_lock);
102 }
103
imx_clk_divider_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width,unsigned long flags)104 static inline struct clk *imx_clk_divider_flags(const char *name,
105 const char *parent, void __iomem *reg, u8 shift, u8 width,
106 unsigned long flags)
107 {
108 return clk_register_divider(NULL, name, parent, flags,
109 reg, shift, width, 0, &imx_ccm_lock);
110 }
111
imx_clk_divider2(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width)112 static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
113 void __iomem *reg, u8 shift, u8 width)
114 {
115 return clk_register_divider(NULL, name, parent,
116 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
117 reg, shift, width, 0, &imx_ccm_lock);
118 }
119
imx_clk_gate(const char * name,const char * parent,void __iomem * reg,u8 shift)120 static inline struct clk *imx_clk_gate(const char *name, const char *parent,
121 void __iomem *reg, u8 shift)
122 {
123 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
124 shift, 0, &imx_ccm_lock);
125 }
126
imx_clk_gate_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags)127 static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
128 void __iomem *reg, u8 shift, unsigned long flags)
129 {
130 return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
131 shift, 0, &imx_ccm_lock);
132 }
133
imx_clk_gate_dis(const char * name,const char * parent,void __iomem * reg,u8 shift)134 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
135 void __iomem *reg, u8 shift)
136 {
137 return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
138 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
139 }
140
imx_clk_gate2(const char * name,const char * parent,void __iomem * reg,u8 shift)141 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
142 void __iomem *reg, u8 shift)
143 {
144 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
145 shift, 0x3, 0, &imx_ccm_lock, NULL);
146 }
147
imx_clk_gate2_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags)148 static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent,
149 void __iomem *reg, u8 shift, unsigned long flags)
150 {
151 return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
152 shift, 0x3, 0, &imx_ccm_lock, NULL);
153 }
154
imx_clk_gate2_shared(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned int * share_count)155 static inline struct clk *imx_clk_gate2_shared(const char *name,
156 const char *parent, void __iomem *reg, u8 shift,
157 unsigned int *share_count)
158 {
159 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
160 shift, 0x3, 0, &imx_ccm_lock, share_count);
161 }
162
imx_clk_gate2_shared2(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned int * share_count)163 static inline struct clk *imx_clk_gate2_shared2(const char *name,
164 const char *parent, void __iomem *reg, u8 shift,
165 unsigned int *share_count)
166 {
167 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
168 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
169 &imx_ccm_lock, share_count);
170 }
171
imx_clk_gate2_cgr(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 cgr_val)172 static inline struct clk *imx_clk_gate2_cgr(const char *name,
173 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
174 {
175 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
176 shift, cgr_val, 0, &imx_ccm_lock, NULL);
177 }
178
imx_clk_gate3(const char * name,const char * parent,void __iomem * reg,u8 shift)179 static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
180 void __iomem *reg, u8 shift)
181 {
182 return clk_register_gate(NULL, name, parent,
183 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
184 reg, shift, 0, &imx_ccm_lock);
185 }
186
imx_clk_gate4(const char * name,const char * parent,void __iomem * reg,u8 shift)187 static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
188 void __iomem *reg, u8 shift)
189 {
190 return clk_register_gate2(NULL, name, parent,
191 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
192 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
193 }
194
imx_clk_mux(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)195 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
196 u8 shift, u8 width, const char * const *parents,
197 int num_parents)
198 {
199 return clk_register_mux(NULL, name, parents, num_parents,
200 CLK_SET_RATE_NO_REPARENT, reg, shift,
201 width, 0, &imx_ccm_lock);
202 }
203
imx_clk_mux2(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)204 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
205 u8 shift, u8 width, const char * const *parents,
206 int num_parents)
207 {
208 return clk_register_mux(NULL, name, parents, num_parents,
209 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
210 reg, shift, width, 0, &imx_ccm_lock);
211 }
212
imx_clk_mux_flags(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,unsigned long flags)213 static inline struct clk *imx_clk_mux_flags(const char *name,
214 void __iomem *reg, u8 shift, u8 width,
215 const char * const *parents, int num_parents,
216 unsigned long flags)
217 {
218 return clk_register_mux(NULL, name, parents, num_parents,
219 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
220 &imx_ccm_lock);
221 }
222
223 struct clk *imx_clk_cpu(const char *name, const char *parent_name,
224 struct clk *div, struct clk *mux, struct clk *pll,
225 struct clk *step);
226
227 #endif
228