1 /* $Id: isar.c,v 1.22.2.6 2004/02/11 13:21:34 keil Exp $
2 *
3 * isar.c ISAR (Siemens PSB 7110) specific routines
4 *
5 * Author Karsten Keil (keil@isdn4linux.de)
6 *
7 * This file is (c) under GNU General Public License
8 *
9 */
10
11 #include <linux/init.h>
12 #include "hisax.h"
13 #include "isar.h"
14 #include "isdnl1.h"
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17
18 #define DBG_LOADFIRM 0
19 #define DUMP_MBOXFRAME 2
20
21 #define DLE 0x10
22 #define ETX 0x03
23
24 #define FAXMODCNT 13
25 static const u_char faxmodulation[] = {3, 24, 48, 72, 73, 74, 96, 97, 98, 121, 122, 145, 146};
26 static u_int modmask = 0x1fff;
27 static int frm_extra_delay = 2;
28 static int para_TOA = 6;
29 static const u_char *FC1_CMD[] = {"FAE", "FTS", "FRS", "FTM", "FRM", "FTH", "FRH", "CTRL"};
30
31 static void isar_setup(struct IsdnCardState *cs);
32 static void isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para);
33 static void ll_deliver_faxstat(struct BCState *bcs, u_char status);
34
35 static inline int
waitforHIA(struct IsdnCardState * cs,int timeout)36 waitforHIA(struct IsdnCardState *cs, int timeout)
37 {
38
39 while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) {
40 udelay(1);
41 timeout--;
42 }
43 if (!timeout)
44 printk(KERN_WARNING "HiSax: ISAR waitforHIA timeout\n");
45 return (timeout);
46 }
47
48
49 static int
sendmsg(struct IsdnCardState * cs,u_char his,u_char creg,u_char len,u_char * msg)50 sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len,
51 u_char *msg)
52 {
53 int i;
54
55 if (!waitforHIA(cs, 4000))
56 return (0);
57 #if DUMP_MBOXFRAME
58 if (cs->debug & L1_DEB_HSCX)
59 debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len);
60 #endif
61 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg);
62 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len);
63 cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0);
64 if (msg && len) {
65 cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]);
66 for (i = 1; i < len; i++)
67 cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]);
68 #if DUMP_MBOXFRAME > 1
69 if (cs->debug & L1_DEB_HSCX_FIFO) {
70 char tmp[256], *t;
71
72 i = len;
73 while (i > 0) {
74 t = tmp;
75 t += sprintf(t, "sendmbox cnt %d", len);
76 QuickHex(t, &msg[len-i], (i > 64) ? 64 : i);
77 debugl1(cs, "%s", tmp);
78 i -= 64;
79 }
80 }
81 #endif
82 }
83 cs->BC_Write_Reg(cs, 1, ISAR_HIS, his);
84 waitforHIA(cs, 10000);
85 return (1);
86 }
87
88 /* Call only with IRQ disabled !!! */
89 static inline void
rcv_mbox(struct IsdnCardState * cs,struct isar_reg * ireg,u_char * msg)90 rcv_mbox(struct IsdnCardState *cs, struct isar_reg *ireg, u_char *msg)
91 {
92 int i;
93
94 cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0);
95 if (msg && ireg->clsb) {
96 msg[0] = cs->BC_Read_Reg(cs, 1, ISAR_MBOX);
97 for (i = 1; i < ireg->clsb; i++)
98 msg[i] = cs->BC_Read_Reg(cs, 2, ISAR_MBOX);
99 #if DUMP_MBOXFRAME > 1
100 if (cs->debug & L1_DEB_HSCX_FIFO) {
101 char tmp[256], *t;
102
103 i = ireg->clsb;
104 while (i > 0) {
105 t = tmp;
106 t += sprintf(t, "rcv_mbox cnt %d", ireg->clsb);
107 QuickHex(t, &msg[ireg->clsb - i], (i > 64) ? 64 : i);
108 debugl1(cs, "%s", tmp);
109 i -= 64;
110 }
111 }
112 #endif
113 }
114 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
115 }
116
117 /* Call only with IRQ disabled !!! */
118 static inline void
get_irq_infos(struct IsdnCardState * cs,struct isar_reg * ireg)119 get_irq_infos(struct IsdnCardState *cs, struct isar_reg *ireg)
120 {
121 ireg->iis = cs->BC_Read_Reg(cs, 1, ISAR_IIS);
122 ireg->cmsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_H);
123 ireg->clsb = cs->BC_Read_Reg(cs, 1, ISAR_CTRL_L);
124 #if DUMP_MBOXFRAME
125 if (cs->debug & L1_DEB_HSCX)
126 debugl1(cs, "irq_stat(%02x,%02x,%d)", ireg->iis, ireg->cmsb,
127 ireg->clsb);
128 #endif
129 }
130
131 static int
waitrecmsg(struct IsdnCardState * cs,u_char * len,u_char * msg,int maxdelay)132 waitrecmsg(struct IsdnCardState *cs, u_char *len,
133 u_char *msg, int maxdelay)
134 {
135 int timeout = 0;
136 struct isar_reg *ir = cs->bcs[0].hw.isar.reg;
137
138
139 while ((!(cs->BC_Read_Reg(cs, 0, ISAR_IRQBIT) & ISAR_IRQSTA)) &&
140 (timeout++ < maxdelay))
141 udelay(1);
142 if (timeout > maxdelay) {
143 printk(KERN_WARNING"isar recmsg IRQSTA timeout\n");
144 return (0);
145 }
146 get_irq_infos(cs, ir);
147 rcv_mbox(cs, ir, msg);
148 *len = ir->clsb;
149 return (1);
150 }
151
152 int
ISARVersion(struct IsdnCardState * cs,char * s)153 ISARVersion(struct IsdnCardState *cs, char *s)
154 {
155 int ver;
156 u_char msg[] = ISAR_MSG_HWVER;
157 u_char tmp[64];
158 u_char len;
159 u_long flags;
160 int debug;
161
162 cs->cardmsg(cs, CARD_RESET, NULL);
163 spin_lock_irqsave(&cs->lock, flags);
164 /* disable ISAR IRQ */
165 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
166 debug = cs->debug;
167 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
168 if (!sendmsg(cs, ISAR_HIS_VNR, 0, 3, msg)) {
169 spin_unlock_irqrestore(&cs->lock, flags);
170 return (-1);
171 }
172 if (!waitrecmsg(cs, &len, tmp, 100000)) {
173 spin_unlock_irqrestore(&cs->lock, flags);
174 return (-2);
175 }
176 cs->debug = debug;
177 if (cs->bcs[0].hw.isar.reg->iis == ISAR_IIS_VNR) {
178 if (len == 1) {
179 ver = tmp[0] & 0xf;
180 printk(KERN_INFO "%s ISAR version %d\n", s, ver);
181 } else
182 ver = -3;
183 } else
184 ver = -4;
185 spin_unlock_irqrestore(&cs->lock, flags);
186 return (ver);
187 }
188
189 static int
isar_load_firmware(struct IsdnCardState * cs,u_char __user * buf)190 isar_load_firmware(struct IsdnCardState *cs, u_char __user *buf)
191 {
192 int cfu_ret, ret, size, cnt, debug;
193 u_char len, nom, noc;
194 u_short sadr, left, *sp;
195 u_char __user *p = buf;
196 u_char *msg, *tmpmsg, *mp, tmp[64];
197 u_long flags;
198 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
199
200 struct {u_short sadr;
201 u_short len;
202 u_short d_key;
203 } blk_head;
204
205 #define BLK_HEAD_SIZE 6
206 if (1 != (ret = ISARVersion(cs, "Testing"))) {
207 printk(KERN_ERR"isar_load_firmware wrong isar version %d\n", ret);
208 return (1);
209 }
210 debug = cs->debug;
211 #if DBG_LOADFIRM < 2
212 cs->debug &= ~(L1_DEB_HSCX | L1_DEB_HSCX_FIFO);
213 #endif
214
215 cfu_ret = copy_from_user(&size, p, sizeof(int));
216 if (cfu_ret) {
217 printk(KERN_ERR "isar_load_firmware copy_from_user ret %d\n", cfu_ret);
218 return -EFAULT;
219 }
220 p += sizeof(int);
221 printk(KERN_DEBUG"isar_load_firmware size: %d\n", size);
222 cnt = 0;
223 /* disable ISAR IRQ */
224 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
225 if (!(msg = kmalloc(256, GFP_KERNEL))) {
226 printk(KERN_ERR"isar_load_firmware no buffer\n");
227 return (1);
228 }
229 if (!(tmpmsg = kmalloc(256, GFP_KERNEL))) {
230 printk(KERN_ERR"isar_load_firmware no tmp buffer\n");
231 kfree(msg);
232 return (1);
233 }
234 spin_lock_irqsave(&cs->lock, flags);
235 /* disable ISAR IRQ */
236 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
237 spin_unlock_irqrestore(&cs->lock, flags);
238 while (cnt < size) {
239 if ((ret = copy_from_user(&blk_head, p, BLK_HEAD_SIZE))) {
240 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
241 goto reterror;
242 }
243 #ifdef __BIG_ENDIAN
244 sadr = (blk_head.sadr & 0xff) * 256 + blk_head.sadr / 256;
245 blk_head.sadr = sadr;
246 sadr = (blk_head.len & 0xff) * 256 + blk_head.len / 256;
247 blk_head.len = sadr;
248 sadr = (blk_head.d_key & 0xff) * 256 + blk_head.d_key / 256;
249 blk_head.d_key = sadr;
250 #endif /* __BIG_ENDIAN */
251 cnt += BLK_HEAD_SIZE;
252 p += BLK_HEAD_SIZE;
253 printk(KERN_DEBUG"isar firmware block (%#x,%5d,%#x)\n",
254 blk_head.sadr, blk_head.len, blk_head.d_key & 0xff);
255 sadr = blk_head.sadr;
256 left = blk_head.len;
257 spin_lock_irqsave(&cs->lock, flags);
258 if (!sendmsg(cs, ISAR_HIS_DKEY, blk_head.d_key & 0xff, 0, NULL)) {
259 printk(KERN_ERR"isar sendmsg dkey failed\n");
260 ret = 1; goto reterr_unlock;
261 }
262 if (!waitrecmsg(cs, &len, tmp, 100000)) {
263 printk(KERN_ERR"isar waitrecmsg dkey failed\n");
264 ret = 1; goto reterr_unlock;
265 }
266 if ((ireg->iis != ISAR_IIS_DKEY) || ireg->cmsb || len) {
267 printk(KERN_ERR"isar wrong dkey response (%x,%x,%x)\n",
268 ireg->iis, ireg->cmsb, len);
269 ret = 1; goto reterr_unlock;
270 }
271 spin_unlock_irqrestore(&cs->lock, flags);
272 while (left > 0) {
273 if (left > 126)
274 noc = 126;
275 else
276 noc = left;
277 nom = 2 * noc;
278 mp = msg;
279 *mp++ = sadr / 256;
280 *mp++ = sadr % 256;
281 left -= noc;
282 *mp++ = noc;
283 if ((ret = copy_from_user(tmpmsg, p, nom))) {
284 printk(KERN_ERR"isar_load_firmware copy_from_user ret %d\n", ret);
285 goto reterror;
286 }
287 p += nom;
288 cnt += nom;
289 nom += 3;
290 sp = (u_short *)tmpmsg;
291 #if DBG_LOADFIRM
292 printk(KERN_DEBUG"isar: load %3d words at %04x left %d\n",
293 noc, sadr, left);
294 #endif
295 sadr += noc;
296 while (noc) {
297 #ifdef __BIG_ENDIAN
298 *mp++ = *sp % 256;
299 *mp++ = *sp / 256;
300 #else
301 *mp++ = *sp / 256;
302 *mp++ = *sp % 256;
303 #endif /* __BIG_ENDIAN */
304 sp++;
305 noc--;
306 }
307 spin_lock_irqsave(&cs->lock, flags);
308 if (!sendmsg(cs, ISAR_HIS_FIRM, 0, nom, msg)) {
309 printk(KERN_ERR"isar sendmsg prog failed\n");
310 ret = 1; goto reterr_unlock;
311 }
312 if (!waitrecmsg(cs, &len, tmp, 100000)) {
313 printk(KERN_ERR"isar waitrecmsg prog failed\n");
314 ret = 1; goto reterr_unlock;
315 }
316 if ((ireg->iis != ISAR_IIS_FIRM) || ireg->cmsb || len) {
317 printk(KERN_ERR"isar wrong prog response (%x,%x,%x)\n",
318 ireg->iis, ireg->cmsb, len);
319 ret = 1; goto reterr_unlock;
320 }
321 spin_unlock_irqrestore(&cs->lock, flags);
322 }
323 printk(KERN_DEBUG"isar firmware block %5d words loaded\n",
324 blk_head.len);
325 }
326 /* 10ms delay */
327 cnt = 10;
328 while (cnt--)
329 udelay(1000);
330 msg[0] = 0xff;
331 msg[1] = 0xfe;
332 ireg->bstat = 0;
333 spin_lock_irqsave(&cs->lock, flags);
334 if (!sendmsg(cs, ISAR_HIS_STDSP, 0, 2, msg)) {
335 printk(KERN_ERR"isar sendmsg start dsp failed\n");
336 ret = 1; goto reterr_unlock;
337 }
338 if (!waitrecmsg(cs, &len, tmp, 100000)) {
339 printk(KERN_ERR"isar waitrecmsg start dsp failed\n");
340 ret = 1; goto reterr_unlock;
341 }
342 if ((ireg->iis != ISAR_IIS_STDSP) || ireg->cmsb || len) {
343 printk(KERN_ERR"isar wrong start dsp response (%x,%x,%x)\n",
344 ireg->iis, ireg->cmsb, len);
345 ret = 1; goto reterr_unlock;
346 } else
347 printk(KERN_DEBUG"isar start dsp success\n");
348 /* NORMAL mode entered */
349 /* Enable IRQs of ISAR */
350 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA);
351 spin_unlock_irqrestore(&cs->lock, flags);
352 cnt = 1000; /* max 1s */
353 while ((!ireg->bstat) && cnt) {
354 udelay(1000);
355 cnt--;
356 }
357 if (!cnt) {
358 printk(KERN_ERR"isar no general status event received\n");
359 ret = 1; goto reterror;
360 } else {
361 printk(KERN_DEBUG"isar general status event %x\n",
362 ireg->bstat);
363 }
364 /* 10ms delay */
365 cnt = 10;
366 while (cnt--)
367 udelay(1000);
368 spin_lock_irqsave(&cs->lock, flags);
369 ireg->iis = 0;
370 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
371 printk(KERN_ERR"isar sendmsg self tst failed\n");
372 ret = 1; goto reterr_unlock;
373 }
374 cnt = 10000; /* max 100 ms */
375 spin_unlock_irqrestore(&cs->lock, flags);
376 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
377 udelay(10);
378 cnt--;
379 }
380 udelay(1000);
381 if (!cnt) {
382 printk(KERN_ERR"isar no self tst response\n");
383 ret = 1; goto reterror;
384 }
385 if ((ireg->cmsb == ISAR_CTRL_STST) && (ireg->clsb == 1)
386 && (ireg->par[0] == 0)) {
387 printk(KERN_DEBUG"isar selftest OK\n");
388 } else {
389 printk(KERN_DEBUG"isar selftest not OK %x/%x/%x\n",
390 ireg->cmsb, ireg->clsb, ireg->par[0]);
391 ret = 1; goto reterror;
392 }
393 spin_lock_irqsave(&cs->lock, flags);
394 ireg->iis = 0;
395 if (!sendmsg(cs, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
396 printk(KERN_ERR"isar RQST SVN failed\n");
397 ret = 1; goto reterr_unlock;
398 }
399 spin_unlock_irqrestore(&cs->lock, flags);
400 cnt = 30000; /* max 300 ms */
401 while ((ireg->iis != ISAR_IIS_DIAG) && cnt) {
402 udelay(10);
403 cnt--;
404 }
405 udelay(1000);
406 if (!cnt) {
407 printk(KERN_ERR"isar no SVN response\n");
408 ret = 1; goto reterror;
409 } else {
410 if ((ireg->cmsb == ISAR_CTRL_SWVER) && (ireg->clsb == 1))
411 printk(KERN_DEBUG"isar software version %#x\n",
412 ireg->par[0]);
413 else {
414 printk(KERN_ERR"isar wrong swver response (%x,%x) cnt(%d)\n",
415 ireg->cmsb, ireg->clsb, cnt);
416 ret = 1; goto reterror;
417 }
418 }
419 spin_lock_irqsave(&cs->lock, flags);
420 cs->debug = debug;
421 isar_setup(cs);
422
423 ret = 0;
424 reterr_unlock:
425 spin_unlock_irqrestore(&cs->lock, flags);
426 reterror:
427 cs->debug = debug;
428 if (ret)
429 /* disable ISAR IRQ */
430 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0);
431 kfree(msg);
432 kfree(tmpmsg);
433 return (ret);
434 }
435
436 #define B_LL_NOCARRIER 8
437 #define B_LL_CONNECT 9
438 #define B_LL_OK 10
439
440 static void
isar_bh(struct work_struct * work)441 isar_bh(struct work_struct *work)
442 {
443 struct BCState *bcs = container_of(work, struct BCState, tqueue);
444
445 BChannel_bh(work);
446 if (test_and_clear_bit(B_LL_NOCARRIER, &bcs->event))
447 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_NOCARR);
448 if (test_and_clear_bit(B_LL_CONNECT, &bcs->event))
449 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
450 if (test_and_clear_bit(B_LL_OK, &bcs->event))
451 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_OK);
452 }
453
454 static void
send_DLE_ETX(struct BCState * bcs)455 send_DLE_ETX(struct BCState *bcs)
456 {
457 u_char dleetx[2] = {DLE, ETX};
458 struct sk_buff *skb;
459
460 if ((skb = dev_alloc_skb(2))) {
461 skb_put_data(skb, dleetx, 2);
462 skb_queue_tail(&bcs->rqueue, skb);
463 schedule_event(bcs, B_RCVBUFREADY);
464 } else {
465 printk(KERN_WARNING "HiSax: skb out of memory\n");
466 }
467 }
468
469 static inline int
dle_count(unsigned char * buf,int len)470 dle_count(unsigned char *buf, int len)
471 {
472 int count = 0;
473
474 while (len--)
475 if (*buf++ == DLE)
476 count++;
477 return count;
478 }
479
480 static inline void
insert_dle(unsigned char * dest,unsigned char * src,int count)481 insert_dle(unsigned char *dest, unsigned char *src, int count) {
482 /* <DLE> in input stream have to be flagged as <DLE><DLE> */
483 while (count--) {
484 *dest++ = *src;
485 if (*src++ == DLE)
486 *dest++ = DLE;
487 }
488 }
489
490 static void
isar_rcv_frame(struct IsdnCardState * cs,struct BCState * bcs)491 isar_rcv_frame(struct IsdnCardState *cs, struct BCState *bcs)
492 {
493 u_char *ptr;
494 struct sk_buff *skb;
495 struct isar_reg *ireg = bcs->hw.isar.reg;
496
497 if (!ireg->clsb) {
498 debugl1(cs, "isar zero len frame");
499 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
500 return;
501 }
502 switch (bcs->mode) {
503 case L1_MODE_NULL:
504 debugl1(cs, "isar mode 0 spurious IIS_RDATA %x/%x/%x",
505 ireg->iis, ireg->cmsb, ireg->clsb);
506 printk(KERN_WARNING"isar mode 0 spurious IIS_RDATA %x/%x/%x\n",
507 ireg->iis, ireg->cmsb, ireg->clsb);
508 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
509 break;
510 case L1_MODE_TRANS:
511 case L1_MODE_V32:
512 if ((skb = dev_alloc_skb(ireg->clsb))) {
513 rcv_mbox(cs, ireg, (u_char *)skb_put(skb, ireg->clsb));
514 skb_queue_tail(&bcs->rqueue, skb);
515 schedule_event(bcs, B_RCVBUFREADY);
516 } else {
517 printk(KERN_WARNING "HiSax: skb out of memory\n");
518 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
519 }
520 break;
521 case L1_MODE_HDLC:
522 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
523 if (cs->debug & L1_DEB_WARN)
524 debugl1(cs, "isar_rcv_frame: incoming packet too large");
525 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
526 bcs->hw.isar.rcvidx = 0;
527 } else if (ireg->cmsb & HDLC_ERROR) {
528 if (cs->debug & L1_DEB_WARN)
529 debugl1(cs, "isar frame error %x len %d",
530 ireg->cmsb, ireg->clsb);
531 #ifdef ERROR_STATISTIC
532 if (ireg->cmsb & HDLC_ERR_RER)
533 bcs->err_inv++;
534 if (ireg->cmsb & HDLC_ERR_CER)
535 bcs->err_crc++;
536 #endif
537 bcs->hw.isar.rcvidx = 0;
538 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
539 } else {
540 if (ireg->cmsb & HDLC_FSD)
541 bcs->hw.isar.rcvidx = 0;
542 ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
543 bcs->hw.isar.rcvidx += ireg->clsb;
544 rcv_mbox(cs, ireg, ptr);
545 if (ireg->cmsb & HDLC_FED) {
546 if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
547 if (cs->debug & L1_DEB_WARN)
548 debugl1(cs, "isar frame to short %d",
549 bcs->hw.isar.rcvidx);
550 } else if (!(skb = dev_alloc_skb(bcs->hw.isar.rcvidx - 2))) {
551 printk(KERN_WARNING "ISAR: receive out of memory\n");
552 } else {
553 skb_put_data(skb, bcs->hw.isar.rcvbuf,
554 bcs->hw.isar.rcvidx - 2);
555 skb_queue_tail(&bcs->rqueue, skb);
556 schedule_event(bcs, B_RCVBUFREADY);
557 }
558 bcs->hw.isar.rcvidx = 0;
559 }
560 }
561 break;
562 case L1_MODE_FAX:
563 if (bcs->hw.isar.state != STFAX_ACTIV) {
564 if (cs->debug & L1_DEB_WARN)
565 debugl1(cs, "isar_rcv_frame: not ACTIV");
566 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
567 bcs->hw.isar.rcvidx = 0;
568 break;
569 }
570 if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
571 rcv_mbox(cs, ireg, bcs->hw.isar.rcvbuf);
572 bcs->hw.isar.rcvidx = ireg->clsb +
573 dle_count(bcs->hw.isar.rcvbuf, ireg->clsb);
574 if (cs->debug & L1_DEB_HSCX)
575 debugl1(cs, "isar_rcv_frame: raw(%d) dle(%d)",
576 ireg->clsb, bcs->hw.isar.rcvidx);
577 if ((skb = dev_alloc_skb(bcs->hw.isar.rcvidx))) {
578 insert_dle((u_char *)skb_put(skb, bcs->hw.isar.rcvidx),
579 bcs->hw.isar.rcvbuf, ireg->clsb);
580 skb_queue_tail(&bcs->rqueue, skb);
581 schedule_event(bcs, B_RCVBUFREADY);
582 if (ireg->cmsb & SART_NMD) { /* ABORT */
583 if (cs->debug & L1_DEB_WARN)
584 debugl1(cs, "isar_rcv_frame: no more data");
585 bcs->hw.isar.rcvidx = 0;
586 send_DLE_ETX(bcs);
587 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
588 ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC,
589 0, NULL);
590 bcs->hw.isar.state = STFAX_ESCAPE;
591 schedule_event(bcs, B_LL_NOCARRIER);
592 }
593 } else {
594 printk(KERN_WARNING "HiSax: skb out of memory\n");
595 }
596 break;
597 }
598 if (bcs->hw.isar.cmd != PCTRL_CMD_FRH) {
599 if (cs->debug & L1_DEB_WARN)
600 debugl1(cs, "isar_rcv_frame: unknown fax mode %x",
601 bcs->hw.isar.cmd);
602 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
603 bcs->hw.isar.rcvidx = 0;
604 break;
605 }
606 /* PCTRL_CMD_FRH */
607 if ((bcs->hw.isar.rcvidx + ireg->clsb) > HSCX_BUFMAX) {
608 if (cs->debug & L1_DEB_WARN)
609 debugl1(cs, "isar_rcv_frame: incoming packet too large");
610 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
611 bcs->hw.isar.rcvidx = 0;
612 } else if (ireg->cmsb & HDLC_ERROR) {
613 if (cs->debug & L1_DEB_WARN)
614 debugl1(cs, "isar frame error %x len %d",
615 ireg->cmsb, ireg->clsb);
616 bcs->hw.isar.rcvidx = 0;
617 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
618 } else {
619 if (ireg->cmsb & HDLC_FSD) {
620 bcs->hw.isar.rcvidx = 0;
621 }
622 ptr = bcs->hw.isar.rcvbuf + bcs->hw.isar.rcvidx;
623 bcs->hw.isar.rcvidx += ireg->clsb;
624 rcv_mbox(cs, ireg, ptr);
625 if (ireg->cmsb & HDLC_FED) {
626 int len = bcs->hw.isar.rcvidx +
627 dle_count(bcs->hw.isar.rcvbuf, bcs->hw.isar.rcvidx);
628 if (bcs->hw.isar.rcvidx < 3) { /* last 2 bytes are the FCS */
629 if (cs->debug & L1_DEB_WARN)
630 debugl1(cs, "isar frame to short %d",
631 bcs->hw.isar.rcvidx);
632 printk(KERN_WARNING "ISAR: frame to short %d\n",
633 bcs->hw.isar.rcvidx);
634 } else if (!(skb = dev_alloc_skb(len))) {
635 printk(KERN_WARNING "ISAR: receive out of memory\n");
636 } else {
637 insert_dle((u_char *)skb_put(skb, len),
638 bcs->hw.isar.rcvbuf,
639 bcs->hw.isar.rcvidx);
640 skb_queue_tail(&bcs->rqueue, skb);
641 schedule_event(bcs, B_RCVBUFREADY);
642 send_DLE_ETX(bcs);
643 schedule_event(bcs, B_LL_OK);
644 test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
645 }
646 bcs->hw.isar.rcvidx = 0;
647 }
648 }
649 if (ireg->cmsb & SART_NMD) { /* ABORT */
650 if (cs->debug & L1_DEB_WARN)
651 debugl1(cs, "isar_rcv_frame: no more data");
652 bcs->hw.isar.rcvidx = 0;
653 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) |
654 ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
655 bcs->hw.isar.state = STFAX_ESCAPE;
656 if (test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag)) {
657 send_DLE_ETX(bcs);
658 schedule_event(bcs, B_LL_NOCARRIER);
659 }
660 }
661 break;
662 default:
663 printk(KERN_ERR"isar_rcv_frame mode (%x)error\n", bcs->mode);
664 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
665 break;
666 }
667 }
668
669 void
isar_fill_fifo(struct BCState * bcs)670 isar_fill_fifo(struct BCState *bcs)
671 {
672 struct IsdnCardState *cs = bcs->cs;
673 int count;
674 u_char msb;
675 u_char *ptr;
676
677 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
678 debugl1(cs, "isar_fill_fifo");
679 if (!bcs->tx_skb)
680 return;
681 if (bcs->tx_skb->len <= 0)
682 return;
683 if (!(bcs->hw.isar.reg->bstat &
684 (bcs->hw.isar.dpath == 1 ? BSTAT_RDM1 : BSTAT_RDM2)))
685 return;
686 if (bcs->tx_skb->len > bcs->hw.isar.mml) {
687 msb = 0;
688 count = bcs->hw.isar.mml;
689 } else {
690 count = bcs->tx_skb->len;
691 msb = HDLC_FED;
692 }
693 ptr = bcs->tx_skb->data;
694 if (!bcs->hw.isar.txcnt) {
695 msb |= HDLC_FST;
696 if ((bcs->mode == L1_MODE_FAX) &&
697 (bcs->hw.isar.cmd == PCTRL_CMD_FTH)) {
698 if (bcs->tx_skb->len > 1) {
699 if ((ptr[0] == 0xff) && (ptr[1] == 0x13))
700 /* last frame */
701 test_and_set_bit(BC_FLG_LASTDATA,
702 &bcs->Flag);
703 }
704 }
705 }
706 skb_pull(bcs->tx_skb, count);
707 bcs->tx_cnt -= count;
708 bcs->hw.isar.txcnt += count;
709 switch (bcs->mode) {
710 case L1_MODE_NULL:
711 printk(KERN_ERR"isar_fill_fifo wrong mode 0\n");
712 break;
713 case L1_MODE_TRANS:
714 case L1_MODE_V32:
715 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
716 0, count, ptr);
717 break;
718 case L1_MODE_HDLC:
719 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
720 msb, count, ptr);
721 break;
722 case L1_MODE_FAX:
723 if (bcs->hw.isar.state != STFAX_ACTIV) {
724 if (cs->debug & L1_DEB_WARN)
725 debugl1(cs, "isar_fill_fifo: not ACTIV");
726 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
727 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
728 msb, count, ptr);
729 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
730 sendmsg(cs, SET_DPS(bcs->hw.isar.dpath) | ISAR_HIS_SDATA,
731 0, count, ptr);
732 } else {
733 if (cs->debug & L1_DEB_WARN)
734 debugl1(cs, "isar_fill_fifo: not FTH/FTM");
735 }
736 break;
737 default:
738 if (cs->debug)
739 debugl1(cs, "isar_fill_fifo mode(%x) error", bcs->mode);
740 printk(KERN_ERR"isar_fill_fifo mode(%x) error\n", bcs->mode);
741 break;
742 }
743 }
744
745 static inline
sel_bcs_isar(struct IsdnCardState * cs,u_char dpath)746 struct BCState *sel_bcs_isar(struct IsdnCardState *cs, u_char dpath)
747 {
748 if ((!dpath) || (dpath == 3))
749 return (NULL);
750 if (cs->bcs[0].hw.isar.dpath == dpath)
751 return (&cs->bcs[0]);
752 if (cs->bcs[1].hw.isar.dpath == dpath)
753 return (&cs->bcs[1]);
754 return (NULL);
755 }
756
757 static void
send_frames(struct BCState * bcs)758 send_frames(struct BCState *bcs)
759 {
760 if (bcs->tx_skb) {
761 if (bcs->tx_skb->len) {
762 isar_fill_fifo(bcs);
763 return;
764 } else {
765 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
766 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
767 u_long flags;
768 spin_lock_irqsave(&bcs->aclock, flags);
769 bcs->ackcnt += bcs->hw.isar.txcnt;
770 spin_unlock_irqrestore(&bcs->aclock, flags);
771 schedule_event(bcs, B_ACKPENDING);
772 }
773 if (bcs->mode == L1_MODE_FAX) {
774 if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
775 if (test_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
776 test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
777 }
778 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FTM) {
779 if (test_bit(BC_FLG_DLEETX, &bcs->Flag)) {
780 test_and_set_bit(BC_FLG_LASTDATA, &bcs->Flag);
781 test_and_set_bit(BC_FLG_NMD_DATA, &bcs->Flag);
782 }
783 }
784 }
785 dev_kfree_skb_any(bcs->tx_skb);
786 bcs->hw.isar.txcnt = 0;
787 bcs->tx_skb = NULL;
788 }
789 }
790 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
791 bcs->hw.isar.txcnt = 0;
792 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
793 isar_fill_fifo(bcs);
794 } else {
795 if (test_and_clear_bit(BC_FLG_DLEETX, &bcs->Flag)) {
796 if (test_and_clear_bit(BC_FLG_LASTDATA, &bcs->Flag)) {
797 if (test_and_clear_bit(BC_FLG_NMD_DATA, &bcs->Flag)) {
798 u_char dummy = 0;
799 sendmsg(bcs->cs, SET_DPS(bcs->hw.isar.dpath) |
800 ISAR_HIS_SDATA, 0x01, 1, &dummy);
801 }
802 test_and_set_bit(BC_FLG_LL_OK, &bcs->Flag);
803 } else {
804 schedule_event(bcs, B_LL_CONNECT);
805 }
806 }
807 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
808 schedule_event(bcs, B_XMTBUFREADY);
809 }
810 }
811
812 static inline void
check_send(struct IsdnCardState * cs,u_char rdm)813 check_send(struct IsdnCardState *cs, u_char rdm)
814 {
815 struct BCState *bcs;
816
817 if (rdm & BSTAT_RDM1) {
818 if ((bcs = sel_bcs_isar(cs, 1))) {
819 if (bcs->mode) {
820 send_frames(bcs);
821 }
822 }
823 }
824 if (rdm & BSTAT_RDM2) {
825 if ((bcs = sel_bcs_isar(cs, 2))) {
826 if (bcs->mode) {
827 send_frames(bcs);
828 }
829 }
830 }
831
832 }
833
834 static const char *dmril[] = {"NO SPEED", "1200/75", "NODEF2", "75/1200",
835 "NODEF4", "300", "600", "1200", "2400",
836 "4800", "7200", "9600nt", "9600t", "12000",
837 "14400", "WRONG"};
838 static const char *dmrim[] = {"NO MOD", "NO DEF", "V32/V32b", "V22", "V21",
839 "Bell103", "V23", "Bell202", "V17", "V29",
840 "V27ter"};
841
842 static void
isar_pump_status_rsp(struct BCState * bcs,struct isar_reg * ireg)843 isar_pump_status_rsp(struct BCState *bcs, struct isar_reg *ireg) {
844 struct IsdnCardState *cs = bcs->cs;
845 u_char ril = ireg->par[0];
846 u_char rim;
847
848 if (!test_and_clear_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags))
849 return;
850 if (ril > 14) {
851 if (cs->debug & L1_DEB_WARN)
852 debugl1(cs, "wrong pstrsp ril=%d", ril);
853 ril = 15;
854 }
855 switch (ireg->par[1]) {
856 case 0:
857 rim = 0;
858 break;
859 case 0x20:
860 rim = 2;
861 break;
862 case 0x40:
863 rim = 3;
864 break;
865 case 0x41:
866 rim = 4;
867 break;
868 case 0x51:
869 rim = 5;
870 break;
871 case 0x61:
872 rim = 6;
873 break;
874 case 0x71:
875 rim = 7;
876 break;
877 case 0x82:
878 rim = 8;
879 break;
880 case 0x92:
881 rim = 9;
882 break;
883 case 0xa2:
884 rim = 10;
885 break;
886 default:
887 rim = 1;
888 break;
889 }
890 sprintf(bcs->hw.isar.conmsg, "%s %s", dmril[ril], dmrim[rim]);
891 bcs->conmsg = bcs->hw.isar.conmsg;
892 if (cs->debug & L1_DEB_HSCX)
893 debugl1(cs, "pump strsp %s", bcs->conmsg);
894 }
895
896 static void
isar_pump_statev_modem(struct BCState * bcs,u_char devt)897 isar_pump_statev_modem(struct BCState *bcs, u_char devt) {
898 struct IsdnCardState *cs = bcs->cs;
899 u_char dps = SET_DPS(bcs->hw.isar.dpath);
900
901 switch (devt) {
902 case PSEV_10MS_TIMER:
903 if (cs->debug & L1_DEB_HSCX)
904 debugl1(cs, "pump stev TIMER");
905 break;
906 case PSEV_CON_ON:
907 if (cs->debug & L1_DEB_HSCX)
908 debugl1(cs, "pump stev CONNECT");
909 l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
910 break;
911 case PSEV_CON_OFF:
912 if (cs->debug & L1_DEB_HSCX)
913 debugl1(cs, "pump stev NO CONNECT");
914 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
915 l1_msg_b(bcs->st, PH_DEACTIVATE | REQUEST, NULL);
916 break;
917 case PSEV_V24_OFF:
918 if (cs->debug & L1_DEB_HSCX)
919 debugl1(cs, "pump stev V24 OFF");
920 break;
921 case PSEV_CTS_ON:
922 if (cs->debug & L1_DEB_HSCX)
923 debugl1(cs, "pump stev CTS ON");
924 break;
925 case PSEV_CTS_OFF:
926 if (cs->debug & L1_DEB_HSCX)
927 debugl1(cs, "pump stev CTS OFF");
928 break;
929 case PSEV_DCD_ON:
930 if (cs->debug & L1_DEB_HSCX)
931 debugl1(cs, "pump stev CARRIER ON");
932 test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
933 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
934 break;
935 case PSEV_DCD_OFF:
936 if (cs->debug & L1_DEB_HSCX)
937 debugl1(cs, "pump stev CARRIER OFF");
938 break;
939 case PSEV_DSR_ON:
940 if (cs->debug & L1_DEB_HSCX)
941 debugl1(cs, "pump stev DSR ON");
942 break;
943 case PSEV_DSR_OFF:
944 if (cs->debug & L1_DEB_HSCX)
945 debugl1(cs, "pump stev DSR_OFF");
946 break;
947 case PSEV_REM_RET:
948 if (cs->debug & L1_DEB_HSCX)
949 debugl1(cs, "pump stev REMOTE RETRAIN");
950 break;
951 case PSEV_REM_REN:
952 if (cs->debug & L1_DEB_HSCX)
953 debugl1(cs, "pump stev REMOTE RENEGOTIATE");
954 break;
955 case PSEV_GSTN_CLR:
956 if (cs->debug & L1_DEB_HSCX)
957 debugl1(cs, "pump stev GSTN CLEAR");
958 break;
959 default:
960 if (cs->debug & L1_DEB_HSCX)
961 debugl1(cs, "unknown pump stev %x", devt);
962 break;
963 }
964 }
965
966 static void
ll_deliver_faxstat(struct BCState * bcs,u_char status)967 ll_deliver_faxstat(struct BCState *bcs, u_char status)
968 {
969 isdn_ctrl ic;
970 struct Channel *chanp = (struct Channel *) bcs->st->lli.userdata;
971
972 if (bcs->cs->debug & L1_DEB_HSCX)
973 debugl1(bcs->cs, "HL->LL FAXIND %x", status);
974 ic.driver = bcs->cs->myid;
975 ic.command = ISDN_STAT_FAXIND;
976 ic.arg = chanp->chan;
977 ic.parm.aux.cmd = status;
978 bcs->cs->iif.statcallb(&ic);
979 }
980
981 static void
isar_pump_statev_fax(struct BCState * bcs,u_char devt)982 isar_pump_statev_fax(struct BCState *bcs, u_char devt) {
983 struct IsdnCardState *cs = bcs->cs;
984 u_char dps = SET_DPS(bcs->hw.isar.dpath);
985 u_char p1;
986
987 switch (devt) {
988 case PSEV_10MS_TIMER:
989 if (cs->debug & L1_DEB_HSCX)
990 debugl1(cs, "pump stev TIMER");
991 break;
992 case PSEV_RSP_READY:
993 if (cs->debug & L1_DEB_HSCX)
994 debugl1(cs, "pump stev RSP_READY");
995 bcs->hw.isar.state = STFAX_READY;
996 l1_msg_b(bcs->st, PH_ACTIVATE | REQUEST, NULL);
997 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
998 isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FRH, 3);
999 } else {
1000 isar_pump_cmd(bcs, ISDN_FAX_CLASS1_FTH, 3);
1001 }
1002 break;
1003 case PSEV_LINE_TX_H:
1004 if (bcs->hw.isar.state == STFAX_LINE) {
1005 if (cs->debug & L1_DEB_HSCX)
1006 debugl1(cs, "pump stev LINE_TX_H");
1007 bcs->hw.isar.state = STFAX_CONT;
1008 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1009 } else {
1010 if (cs->debug & L1_DEB_WARN)
1011 debugl1(cs, "pump stev LINE_TX_H wrong st %x",
1012 bcs->hw.isar.state);
1013 }
1014 break;
1015 case PSEV_LINE_RX_H:
1016 if (bcs->hw.isar.state == STFAX_LINE) {
1017 if (cs->debug & L1_DEB_HSCX)
1018 debugl1(cs, "pump stev LINE_RX_H");
1019 bcs->hw.isar.state = STFAX_CONT;
1020 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1021 } else {
1022 if (cs->debug & L1_DEB_WARN)
1023 debugl1(cs, "pump stev LINE_RX_H wrong st %x",
1024 bcs->hw.isar.state);
1025 }
1026 break;
1027 case PSEV_LINE_TX_B:
1028 if (bcs->hw.isar.state == STFAX_LINE) {
1029 if (cs->debug & L1_DEB_HSCX)
1030 debugl1(cs, "pump stev LINE_TX_B");
1031 bcs->hw.isar.state = STFAX_CONT;
1032 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1033 } else {
1034 if (cs->debug & L1_DEB_WARN)
1035 debugl1(cs, "pump stev LINE_TX_B wrong st %x",
1036 bcs->hw.isar.state);
1037 }
1038 break;
1039 case PSEV_LINE_RX_B:
1040 if (bcs->hw.isar.state == STFAX_LINE) {
1041 if (cs->debug & L1_DEB_HSCX)
1042 debugl1(cs, "pump stev LINE_RX_B");
1043 bcs->hw.isar.state = STFAX_CONT;
1044 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_CONT, 0, NULL);
1045 } else {
1046 if (cs->debug & L1_DEB_WARN)
1047 debugl1(cs, "pump stev LINE_RX_B wrong st %x",
1048 bcs->hw.isar.state);
1049 }
1050 break;
1051 case PSEV_RSP_CONN:
1052 if (bcs->hw.isar.state == STFAX_CONT) {
1053 if (cs->debug & L1_DEB_HSCX)
1054 debugl1(cs, "pump stev RSP_CONN");
1055 bcs->hw.isar.state = STFAX_ACTIV;
1056 test_and_set_bit(ISAR_RATE_REQ, &bcs->hw.isar.reg->Flags);
1057 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
1058 if (bcs->hw.isar.cmd == PCTRL_CMD_FTH) {
1059 /* 1s Flags before data */
1060 if (test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag))
1061 del_timer(&bcs->hw.isar.ftimer);
1062 /* 1000 ms */
1063 bcs->hw.isar.ftimer.expires =
1064 jiffies + ((1000 * HZ) / 1000);
1065 test_and_set_bit(BC_FLG_LL_CONN,
1066 &bcs->Flag);
1067 add_timer(&bcs->hw.isar.ftimer);
1068 } else {
1069 schedule_event(bcs, B_LL_CONNECT);
1070 }
1071 } else {
1072 if (cs->debug & L1_DEB_WARN)
1073 debugl1(cs, "pump stev RSP_CONN wrong st %x",
1074 bcs->hw.isar.state);
1075 }
1076 break;
1077 case PSEV_FLAGS_DET:
1078 if (cs->debug & L1_DEB_HSCX)
1079 debugl1(cs, "pump stev FLAGS_DET");
1080 break;
1081 case PSEV_RSP_DISC:
1082 if (cs->debug & L1_DEB_HSCX)
1083 debugl1(cs, "pump stev RSP_DISC");
1084 if (bcs->hw.isar.state == STFAX_ESCAPE) {
1085 p1 = 5;
1086 switch (bcs->hw.isar.newcmd) {
1087 case 0:
1088 bcs->hw.isar.state = STFAX_READY;
1089 break;
1090 case PCTRL_CMD_FTM:
1091 p1 = 2;
1092 /* fall through */
1093 case PCTRL_CMD_FTH:
1094 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1095 PCTRL_CMD_SILON, 1, &p1);
1096 bcs->hw.isar.state = STFAX_SILDET;
1097 break;
1098 case PCTRL_CMD_FRM:
1099 if (frm_extra_delay)
1100 mdelay(frm_extra_delay);
1101 /* fall through */
1102 case PCTRL_CMD_FRH:
1103 p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
1104 bcs->hw.isar.newmod = 0;
1105 bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
1106 bcs->hw.isar.newcmd = 0;
1107 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1108 bcs->hw.isar.cmd, 1, &p1);
1109 bcs->hw.isar.state = STFAX_LINE;
1110 bcs->hw.isar.try_mod = 3;
1111 break;
1112 default:
1113 if (cs->debug & L1_DEB_HSCX)
1114 debugl1(cs, "RSP_DISC unknown newcmd %x", bcs->hw.isar.newcmd);
1115 break;
1116 }
1117 } else if (bcs->hw.isar.state == STFAX_ACTIV) {
1118 if (test_and_clear_bit(BC_FLG_LL_OK, &bcs->Flag)) {
1119 schedule_event(bcs, B_LL_OK);
1120 } else if (bcs->hw.isar.cmd == PCTRL_CMD_FRM) {
1121 send_DLE_ETX(bcs);
1122 schedule_event(bcs, B_LL_NOCARRIER);
1123 } else {
1124 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1125 }
1126 bcs->hw.isar.state = STFAX_READY;
1127 } else {
1128 bcs->hw.isar.state = STFAX_READY;
1129 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1130 }
1131 break;
1132 case PSEV_RSP_SILDET:
1133 if (cs->debug & L1_DEB_HSCX)
1134 debugl1(cs, "pump stev RSP_SILDET");
1135 if (bcs->hw.isar.state == STFAX_SILDET) {
1136 p1 = bcs->hw.isar.mod = bcs->hw.isar.newmod;
1137 bcs->hw.isar.newmod = 0;
1138 bcs->hw.isar.cmd = bcs->hw.isar.newcmd;
1139 bcs->hw.isar.newcmd = 0;
1140 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1141 bcs->hw.isar.cmd, 1, &p1);
1142 bcs->hw.isar.state = STFAX_LINE;
1143 bcs->hw.isar.try_mod = 3;
1144 }
1145 break;
1146 case PSEV_RSP_SILOFF:
1147 if (cs->debug & L1_DEB_HSCX)
1148 debugl1(cs, "pump stev RSP_SILOFF");
1149 break;
1150 case PSEV_RSP_FCERR:
1151 if (bcs->hw.isar.state == STFAX_LINE) {
1152 if (cs->debug & L1_DEB_HSCX)
1153 debugl1(cs, "pump stev RSP_FCERR try %d",
1154 bcs->hw.isar.try_mod);
1155 if (bcs->hw.isar.try_mod--) {
1156 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL,
1157 bcs->hw.isar.cmd, 1,
1158 &bcs->hw.isar.mod);
1159 break;
1160 }
1161 }
1162 if (cs->debug & L1_DEB_HSCX)
1163 debugl1(cs, "pump stev RSP_FCERR");
1164 bcs->hw.isar.state = STFAX_ESCAPE;
1165 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, PCTRL_CMD_ESC, 0, NULL);
1166 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_FCERROR);
1167 break;
1168 default:
1169 break;
1170 }
1171 }
1172
1173 static char debbuf[128];
1174
1175 void
isar_int_main(struct IsdnCardState * cs)1176 isar_int_main(struct IsdnCardState *cs)
1177 {
1178 struct isar_reg *ireg = cs->bcs[0].hw.isar.reg;
1179 struct BCState *bcs;
1180
1181 get_irq_infos(cs, ireg);
1182 switch (ireg->iis & ISAR_IIS_MSCMSD) {
1183 case ISAR_IIS_RDATA:
1184 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1185 isar_rcv_frame(cs, bcs);
1186 } else {
1187 debugl1(cs, "isar spurious IIS_RDATA %x/%x/%x",
1188 ireg->iis, ireg->cmsb, ireg->clsb);
1189 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1190 }
1191 break;
1192 case ISAR_IIS_GSTEV:
1193 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1194 ireg->bstat |= ireg->cmsb;
1195 check_send(cs, ireg->cmsb);
1196 break;
1197 case ISAR_IIS_BSTEV:
1198 #ifdef ERROR_STATISTIC
1199 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1200 if (ireg->cmsb == BSTEV_TBO)
1201 bcs->err_tx++;
1202 if (ireg->cmsb == BSTEV_RBO)
1203 bcs->err_rdo++;
1204 }
1205 #endif
1206 if (cs->debug & L1_DEB_WARN)
1207 debugl1(cs, "Buffer STEV dpath%d msb(%x)",
1208 ireg->iis >> 6, ireg->cmsb);
1209 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1210 break;
1211 case ISAR_IIS_PSTEV:
1212 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1213 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1214 if (bcs->mode == L1_MODE_V32) {
1215 isar_pump_statev_modem(bcs, ireg->cmsb);
1216 } else if (bcs->mode == L1_MODE_FAX) {
1217 isar_pump_statev_fax(bcs, ireg->cmsb);
1218 } else if (ireg->cmsb == PSEV_10MS_TIMER) {
1219 if (cs->debug & L1_DEB_HSCX)
1220 debugl1(cs, "pump stev TIMER");
1221 } else {
1222 if (cs->debug & L1_DEB_WARN)
1223 debugl1(cs, "isar IIS_PSTEV pmode %d stat %x",
1224 bcs->mode, ireg->cmsb);
1225 }
1226 } else {
1227 debugl1(cs, "isar spurious IIS_PSTEV %x/%x/%x",
1228 ireg->iis, ireg->cmsb, ireg->clsb);
1229 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1230 }
1231 break;
1232 case ISAR_IIS_PSTRSP:
1233 if ((bcs = sel_bcs_isar(cs, ireg->iis >> 6))) {
1234 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1235 isar_pump_status_rsp(bcs, ireg);
1236 } else {
1237 debugl1(cs, "isar spurious IIS_PSTRSP %x/%x/%x",
1238 ireg->iis, ireg->cmsb, ireg->clsb);
1239 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0);
1240 }
1241 break;
1242 case ISAR_IIS_DIAG:
1243 case ISAR_IIS_BSTRSP:
1244 case ISAR_IIS_IOM2RSP:
1245 rcv_mbox(cs, ireg, (u_char *)ireg->par);
1246 if ((cs->debug & (L1_DEB_HSCX | L1_DEB_HSCX_FIFO))
1247 == L1_DEB_HSCX) {
1248 u_char *tp = debbuf;
1249
1250 tp += sprintf(debbuf, "msg iis(%x) msb(%x)",
1251 ireg->iis, ireg->cmsb);
1252 QuickHex(tp, (u_char *)ireg->par, ireg->clsb);
1253 debugl1(cs, "%s", debbuf);
1254 }
1255 break;
1256 case ISAR_IIS_INVMSG:
1257 rcv_mbox(cs, ireg, debbuf);
1258 if (cs->debug & L1_DEB_WARN)
1259 debugl1(cs, "invalid msg his:%x",
1260 ireg->cmsb);
1261 break;
1262 default:
1263 rcv_mbox(cs, ireg, debbuf);
1264 if (cs->debug & L1_DEB_WARN)
1265 debugl1(cs, "unhandled msg iis(%x) ctrl(%x/%x)",
1266 ireg->iis, ireg->cmsb, ireg->clsb);
1267 break;
1268 }
1269 }
1270
1271 static void
ftimer_handler(struct timer_list * t)1272 ftimer_handler(struct timer_list *t) {
1273 struct BCState *bcs = from_timer(bcs, t, hw.isar.ftimer);
1274 if (bcs->cs->debug)
1275 debugl1(bcs->cs, "ftimer flags %04lx",
1276 bcs->Flag);
1277 test_and_clear_bit(BC_FLG_FTI_RUN, &bcs->Flag);
1278 if (test_and_clear_bit(BC_FLG_LL_CONN, &bcs->Flag)) {
1279 schedule_event(bcs, B_LL_CONNECT);
1280 }
1281 if (test_and_clear_bit(BC_FLG_FTI_FTS, &bcs->Flag)) {
1282 schedule_event(bcs, B_LL_OK);
1283 }
1284 }
1285
1286 static void
setup_pump(struct BCState * bcs)1287 setup_pump(struct BCState *bcs) {
1288 struct IsdnCardState *cs = bcs->cs;
1289 u_char dps = SET_DPS(bcs->hw.isar.dpath);
1290 u_char ctrl, param[6];
1291
1292 switch (bcs->mode) {
1293 case L1_MODE_NULL:
1294 case L1_MODE_TRANS:
1295 case L1_MODE_HDLC:
1296 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, PMOD_BYPASS, 0, NULL);
1297 break;
1298 case L1_MODE_V32:
1299 ctrl = PMOD_DATAMODEM;
1300 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
1301 ctrl |= PCTRL_ORIG;
1302 param[5] = PV32P6_CTN;
1303 } else {
1304 param[5] = PV32P6_ATN;
1305 }
1306 param[0] = para_TOA; /* 6 db */
1307 param[1] = PV32P2_V23R | PV32P2_V22A | PV32P2_V22B |
1308 PV32P2_V22C | PV32P2_V21 | PV32P2_BEL;
1309 param[2] = PV32P3_AMOD | PV32P3_V32B | PV32P3_V23B;
1310 param[3] = PV32P4_UT144;
1311 param[4] = PV32P5_UT144;
1312 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 6, param);
1313 break;
1314 case L1_MODE_FAX:
1315 ctrl = PMOD_FAX;
1316 if (test_bit(BC_FLG_ORIG, &bcs->Flag)) {
1317 ctrl |= PCTRL_ORIG;
1318 param[1] = PFAXP2_CTN;
1319 } else {
1320 param[1] = PFAXP2_ATN;
1321 }
1322 param[0] = para_TOA; /* 6 db */
1323 sendmsg(cs, dps | ISAR_HIS_PUMPCFG, ctrl, 2, param);
1324 bcs->hw.isar.state = STFAX_NULL;
1325 bcs->hw.isar.newcmd = 0;
1326 bcs->hw.isar.newmod = 0;
1327 test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag);
1328 break;
1329 }
1330 udelay(1000);
1331 sendmsg(cs, dps | ISAR_HIS_PSTREQ, 0, 0, NULL);
1332 udelay(1000);
1333 }
1334
1335 static void
setup_sart(struct BCState * bcs)1336 setup_sart(struct BCState *bcs) {
1337 struct IsdnCardState *cs = bcs->cs;
1338 u_char dps = SET_DPS(bcs->hw.isar.dpath);
1339 u_char ctrl, param[2];
1340
1341 switch (bcs->mode) {
1342 case L1_MODE_NULL:
1343 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_DISABLE, 0,
1344 NULL);
1345 break;
1346 case L1_MODE_TRANS:
1347 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_BINARY, 2,
1348 "\0\0");
1349 break;
1350 case L1_MODE_HDLC:
1351 param[0] = 0;
1352 sendmsg(cs, dps | ISAR_HIS_SARTCFG, SMODE_HDLC, 1,
1353 param);
1354 break;
1355 case L1_MODE_V32:
1356 ctrl = SMODE_V14 | SCTRL_HDMC_BOTH;
1357 param[0] = S_P1_CHS_8;
1358 param[1] = S_P2_BFT_DEF;
1359 sendmsg(cs, dps | ISAR_HIS_SARTCFG, ctrl, 2,
1360 param);
1361 break;
1362 case L1_MODE_FAX:
1363 /* SART must not configured with FAX */
1364 break;
1365 }
1366 udelay(1000);
1367 sendmsg(cs, dps | ISAR_HIS_BSTREQ, 0, 0, NULL);
1368 udelay(1000);
1369 }
1370
1371 static void
setup_iom2(struct BCState * bcs)1372 setup_iom2(struct BCState *bcs) {
1373 struct IsdnCardState *cs = bcs->cs;
1374 u_char dps = SET_DPS(bcs->hw.isar.dpath);
1375 u_char cmsb = IOM_CTRL_ENA, msg[5] = {IOM_P1_TXD, 0, 0, 0, 0};
1376
1377 if (bcs->channel)
1378 msg[1] = msg[3] = 1;
1379 switch (bcs->mode) {
1380 case L1_MODE_NULL:
1381 cmsb = 0;
1382 /* dummy slot */
1383 msg[1] = msg[3] = bcs->hw.isar.dpath + 2;
1384 break;
1385 case L1_MODE_TRANS:
1386 case L1_MODE_HDLC:
1387 break;
1388 case L1_MODE_V32:
1389 case L1_MODE_FAX:
1390 cmsb |= IOM_CTRL_ALAW | IOM_CTRL_RCV;
1391 break;
1392 }
1393 sendmsg(cs, dps | ISAR_HIS_IOM2CFG, cmsb, 5, msg);
1394 udelay(1000);
1395 sendmsg(cs, dps | ISAR_HIS_IOM2REQ, 0, 0, NULL);
1396 udelay(1000);
1397 }
1398
1399 static int
modeisar(struct BCState * bcs,int mode,int bc)1400 modeisar(struct BCState *bcs, int mode, int bc)
1401 {
1402 struct IsdnCardState *cs = bcs->cs;
1403
1404 /* Here we are selecting the best datapath for requested mode */
1405 if (bcs->mode == L1_MODE_NULL) { /* New Setup */
1406 bcs->channel = bc;
1407 switch (mode) {
1408 case L1_MODE_NULL: /* init */
1409 if (!bcs->hw.isar.dpath)
1410 /* no init for dpath 0 */
1411 return (0);
1412 break;
1413 case L1_MODE_TRANS:
1414 case L1_MODE_HDLC:
1415 /* best is datapath 2 */
1416 if (!test_and_set_bit(ISAR_DP2_USE,
1417 &bcs->hw.isar.reg->Flags))
1418 bcs->hw.isar.dpath = 2;
1419 else if (!test_and_set_bit(ISAR_DP1_USE,
1420 &bcs->hw.isar.reg->Flags))
1421 bcs->hw.isar.dpath = 1;
1422 else {
1423 printk(KERN_WARNING"isar modeisar both paths in use\n");
1424 return (1);
1425 }
1426 break;
1427 case L1_MODE_V32:
1428 case L1_MODE_FAX:
1429 /* only datapath 1 */
1430 if (!test_and_set_bit(ISAR_DP1_USE,
1431 &bcs->hw.isar.reg->Flags))
1432 bcs->hw.isar.dpath = 1;
1433 else {
1434 printk(KERN_WARNING"isar modeisar analog functions only with DP1\n");
1435 debugl1(cs, "isar modeisar analog functions only with DP1");
1436 return (1);
1437 }
1438 break;
1439 }
1440 }
1441 if (cs->debug & L1_DEB_HSCX)
1442 debugl1(cs, "isar dp%d mode %d->%d ichan %d",
1443 bcs->hw.isar.dpath, bcs->mode, mode, bc);
1444 bcs->mode = mode;
1445 setup_pump(bcs);
1446 setup_iom2(bcs);
1447 setup_sart(bcs);
1448 if (bcs->mode == L1_MODE_NULL) {
1449 /* Clear resources */
1450 if (bcs->hw.isar.dpath == 1)
1451 test_and_clear_bit(ISAR_DP1_USE, &bcs->hw.isar.reg->Flags);
1452 else if (bcs->hw.isar.dpath == 2)
1453 test_and_clear_bit(ISAR_DP2_USE, &bcs->hw.isar.reg->Flags);
1454 bcs->hw.isar.dpath = 0;
1455 }
1456 return (0);
1457 }
1458
1459 static void
isar_pump_cmd(struct BCState * bcs,u_char cmd,u_char para)1460 isar_pump_cmd(struct BCState *bcs, u_char cmd, u_char para)
1461 {
1462 struct IsdnCardState *cs = bcs->cs;
1463 u_char dps = SET_DPS(bcs->hw.isar.dpath);
1464 u_char ctrl = 0, nom = 0, p1 = 0;
1465
1466 switch (cmd) {
1467 case ISDN_FAX_CLASS1_FTM:
1468 test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1469 if (bcs->hw.isar.state == STFAX_READY) {
1470 p1 = para;
1471 ctrl = PCTRL_CMD_FTM;
1472 nom = 1;
1473 bcs->hw.isar.state = STFAX_LINE;
1474 bcs->hw.isar.cmd = ctrl;
1475 bcs->hw.isar.mod = para;
1476 bcs->hw.isar.newmod = 0;
1477 bcs->hw.isar.newcmd = 0;
1478 bcs->hw.isar.try_mod = 3;
1479 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1480 (bcs->hw.isar.cmd == PCTRL_CMD_FTM) &&
1481 (bcs->hw.isar.mod == para)) {
1482 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1483 } else {
1484 bcs->hw.isar.newmod = para;
1485 bcs->hw.isar.newcmd = PCTRL_CMD_FTM;
1486 nom = 0;
1487 ctrl = PCTRL_CMD_ESC;
1488 bcs->hw.isar.state = STFAX_ESCAPE;
1489 }
1490 break;
1491 case ISDN_FAX_CLASS1_FTH:
1492 test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1493 if (bcs->hw.isar.state == STFAX_READY) {
1494 p1 = para;
1495 ctrl = PCTRL_CMD_FTH;
1496 nom = 1;
1497 bcs->hw.isar.state = STFAX_LINE;
1498 bcs->hw.isar.cmd = ctrl;
1499 bcs->hw.isar.mod = para;
1500 bcs->hw.isar.newmod = 0;
1501 bcs->hw.isar.newcmd = 0;
1502 bcs->hw.isar.try_mod = 3;
1503 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1504 (bcs->hw.isar.cmd == PCTRL_CMD_FTH) &&
1505 (bcs->hw.isar.mod == para)) {
1506 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1507 } else {
1508 bcs->hw.isar.newmod = para;
1509 bcs->hw.isar.newcmd = PCTRL_CMD_FTH;
1510 nom = 0;
1511 ctrl = PCTRL_CMD_ESC;
1512 bcs->hw.isar.state = STFAX_ESCAPE;
1513 }
1514 break;
1515 case ISDN_FAX_CLASS1_FRM:
1516 test_and_clear_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1517 if (bcs->hw.isar.state == STFAX_READY) {
1518 p1 = para;
1519 ctrl = PCTRL_CMD_FRM;
1520 nom = 1;
1521 bcs->hw.isar.state = STFAX_LINE;
1522 bcs->hw.isar.cmd = ctrl;
1523 bcs->hw.isar.mod = para;
1524 bcs->hw.isar.newmod = 0;
1525 bcs->hw.isar.newcmd = 0;
1526 bcs->hw.isar.try_mod = 3;
1527 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1528 (bcs->hw.isar.cmd == PCTRL_CMD_FRM) &&
1529 (bcs->hw.isar.mod == para)) {
1530 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1531 } else {
1532 bcs->hw.isar.newmod = para;
1533 bcs->hw.isar.newcmd = PCTRL_CMD_FRM;
1534 nom = 0;
1535 ctrl = PCTRL_CMD_ESC;
1536 bcs->hw.isar.state = STFAX_ESCAPE;
1537 }
1538 break;
1539 case ISDN_FAX_CLASS1_FRH:
1540 test_and_set_bit(BC_FLG_FRH_WAIT, &bcs->Flag);
1541 if (bcs->hw.isar.state == STFAX_READY) {
1542 p1 = para;
1543 ctrl = PCTRL_CMD_FRH;
1544 nom = 1;
1545 bcs->hw.isar.state = STFAX_LINE;
1546 bcs->hw.isar.cmd = ctrl;
1547 bcs->hw.isar.mod = para;
1548 bcs->hw.isar.newmod = 0;
1549 bcs->hw.isar.newcmd = 0;
1550 bcs->hw.isar.try_mod = 3;
1551 } else if ((bcs->hw.isar.state == STFAX_ACTIV) &&
1552 (bcs->hw.isar.cmd == PCTRL_CMD_FRH) &&
1553 (bcs->hw.isar.mod == para)) {
1554 ll_deliver_faxstat(bcs, ISDN_FAX_CLASS1_CONNECT);
1555 } else {
1556 bcs->hw.isar.newmod = para;
1557 bcs->hw.isar.newcmd = PCTRL_CMD_FRH;
1558 nom = 0;
1559 ctrl = PCTRL_CMD_ESC;
1560 bcs->hw.isar.state = STFAX_ESCAPE;
1561 }
1562 break;
1563 case ISDN_FAXPUMP_HALT:
1564 bcs->hw.isar.state = STFAX_NULL;
1565 nom = 0;
1566 ctrl = PCTRL_CMD_HALT;
1567 break;
1568 }
1569 if (ctrl)
1570 sendmsg(cs, dps | ISAR_HIS_PUMPCTRL, ctrl, nom, &p1);
1571 }
1572
1573 static void
isar_setup(struct IsdnCardState * cs)1574 isar_setup(struct IsdnCardState *cs)
1575 {
1576 u_char msg;
1577 int i;
1578
1579 /* Dpath 1, 2 */
1580 msg = 61;
1581 for (i = 0; i < 2; i++) {
1582 /* Buffer Config */
1583 sendmsg(cs, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
1584 ISAR_HIS_P12CFG, 4, 1, &msg);
1585 cs->bcs[i].hw.isar.mml = msg;
1586 cs->bcs[i].mode = 0;
1587 cs->bcs[i].hw.isar.dpath = i + 1;
1588 modeisar(&cs->bcs[i], 0, 0);
1589 INIT_WORK(&cs->bcs[i].tqueue, isar_bh);
1590 }
1591 }
1592
1593 static void
isar_l2l1(struct PStack * st,int pr,void * arg)1594 isar_l2l1(struct PStack *st, int pr, void *arg)
1595 {
1596 struct BCState *bcs = st->l1.bcs;
1597 struct sk_buff *skb = arg;
1598 int ret;
1599 u_long flags;
1600
1601 switch (pr) {
1602 case (PH_DATA | REQUEST):
1603 spin_lock_irqsave(&bcs->cs->lock, flags);
1604 if (bcs->tx_skb) {
1605 skb_queue_tail(&bcs->squeue, skb);
1606 } else {
1607 bcs->tx_skb = skb;
1608 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1609 if (bcs->cs->debug & L1_DEB_HSCX)
1610 debugl1(bcs->cs, "DRQ set BC_FLG_BUSY");
1611 bcs->hw.isar.txcnt = 0;
1612 bcs->cs->BC_Send_Data(bcs);
1613 }
1614 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1615 break;
1616 case (PH_PULL | INDICATION):
1617 spin_lock_irqsave(&bcs->cs->lock, flags);
1618 if (bcs->tx_skb) {
1619 printk(KERN_WARNING "isar_l2l1: this shouldn't happen\n");
1620 } else {
1621 test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1622 if (bcs->cs->debug & L1_DEB_HSCX)
1623 debugl1(bcs->cs, "PUI set BC_FLG_BUSY");
1624 bcs->tx_skb = skb;
1625 bcs->hw.isar.txcnt = 0;
1626 bcs->cs->BC_Send_Data(bcs);
1627 }
1628 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1629 break;
1630 case (PH_PULL | REQUEST):
1631 if (!bcs->tx_skb) {
1632 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1633 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1634 } else
1635 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1636 break;
1637 case (PH_ACTIVATE | REQUEST):
1638 spin_lock_irqsave(&bcs->cs->lock, flags);
1639 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1640 bcs->hw.isar.conmsg[0] = 0;
1641 if (test_bit(FLG_ORIG, &st->l2.flag))
1642 test_and_set_bit(BC_FLG_ORIG, &bcs->Flag);
1643 else
1644 test_and_clear_bit(BC_FLG_ORIG, &bcs->Flag);
1645 switch (st->l1.mode) {
1646 case L1_MODE_TRANS:
1647 case L1_MODE_HDLC:
1648 ret = modeisar(bcs, st->l1.mode, st->l1.bc);
1649 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1650 if (ret)
1651 l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1652 else
1653 l1_msg_b(st, PH_ACTIVATE | REQUEST, arg);
1654 break;
1655 case L1_MODE_V32:
1656 case L1_MODE_FAX:
1657 ret = modeisar(bcs, st->l1.mode, st->l1.bc);
1658 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1659 if (ret)
1660 l1_msg_b(st, PH_DEACTIVATE | REQUEST, arg);
1661 break;
1662 default:
1663 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1664 break;
1665 }
1666 break;
1667 case (PH_DEACTIVATE | REQUEST):
1668 l1_msg_b(st, pr, arg);
1669 break;
1670 case (PH_DEACTIVATE | CONFIRM):
1671 spin_lock_irqsave(&bcs->cs->lock, flags);
1672 switch (st->l1.mode) {
1673 case L1_MODE_TRANS:
1674 case L1_MODE_HDLC:
1675 case L1_MODE_V32:
1676 break;
1677 case L1_MODE_FAX:
1678 isar_pump_cmd(bcs, ISDN_FAXPUMP_HALT, 0);
1679 break;
1680 }
1681 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1682 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1683 if (bcs->cs->debug & L1_DEB_HSCX)
1684 debugl1(bcs->cs, "PDAC clear BC_FLG_BUSY");
1685 modeisar(bcs, 0, st->l1.bc);
1686 spin_unlock_irqrestore(&bcs->cs->lock, flags);
1687 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1688 break;
1689 }
1690 }
1691
1692 static void
close_isarstate(struct BCState * bcs)1693 close_isarstate(struct BCState *bcs)
1694 {
1695 modeisar(bcs, 0, bcs->channel);
1696 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1697 kfree(bcs->hw.isar.rcvbuf);
1698 bcs->hw.isar.rcvbuf = NULL;
1699 skb_queue_purge(&bcs->rqueue);
1700 skb_queue_purge(&bcs->squeue);
1701 if (bcs->tx_skb) {
1702 dev_kfree_skb_any(bcs->tx_skb);
1703 bcs->tx_skb = NULL;
1704 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1705 if (bcs->cs->debug & L1_DEB_HSCX)
1706 debugl1(bcs->cs, "closeisar clear BC_FLG_BUSY");
1707 }
1708 }
1709 del_timer(&bcs->hw.isar.ftimer);
1710 }
1711
1712 static int
open_isarstate(struct IsdnCardState * cs,struct BCState * bcs)1713 open_isarstate(struct IsdnCardState *cs, struct BCState *bcs)
1714 {
1715 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1716 if (!(bcs->hw.isar.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
1717 printk(KERN_WARNING
1718 "HiSax: No memory for isar.rcvbuf\n");
1719 return (1);
1720 }
1721 skb_queue_head_init(&bcs->rqueue);
1722 skb_queue_head_init(&bcs->squeue);
1723 }
1724 bcs->tx_skb = NULL;
1725 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1726 if (cs->debug & L1_DEB_HSCX)
1727 debugl1(cs, "openisar clear BC_FLG_BUSY");
1728 bcs->event = 0;
1729 bcs->hw.isar.rcvidx = 0;
1730 bcs->tx_cnt = 0;
1731 return (0);
1732 }
1733
1734 static int
setstack_isar(struct PStack * st,struct BCState * bcs)1735 setstack_isar(struct PStack *st, struct BCState *bcs)
1736 {
1737 bcs->channel = st->l1.bc;
1738 if (open_isarstate(st->l1.hardware, bcs))
1739 return (-1);
1740 st->l1.bcs = bcs;
1741 st->l2.l2l1 = isar_l2l1;
1742 setstack_manager(st);
1743 bcs->st = st;
1744 setstack_l1_B(st);
1745 return (0);
1746 }
1747
1748 int
isar_auxcmd(struct IsdnCardState * cs,isdn_ctrl * ic)1749 isar_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) {
1750 u_long adr;
1751 int features, i;
1752 struct BCState *bcs;
1753
1754 if (cs->debug & L1_DEB_HSCX)
1755 debugl1(cs, "isar_auxcmd cmd/ch %x/%ld", ic->command, ic->arg);
1756 switch (ic->command) {
1757 case (ISDN_CMD_FAXCMD):
1758 bcs = cs->channel[ic->arg].bcs;
1759 if (cs->debug & L1_DEB_HSCX)
1760 debugl1(cs, "isar_auxcmd cmd/subcmd %d/%d",
1761 ic->parm.aux.cmd, ic->parm.aux.subcmd);
1762 switch (ic->parm.aux.cmd) {
1763 case ISDN_FAX_CLASS1_CTRL:
1764 if (ic->parm.aux.subcmd == ETX)
1765 test_and_set_bit(BC_FLG_DLEETX,
1766 &bcs->Flag);
1767 break;
1768 case ISDN_FAX_CLASS1_FTS:
1769 if (ic->parm.aux.subcmd == AT_QUERY) {
1770 ic->command = ISDN_STAT_FAXIND;
1771 ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
1772 cs->iif.statcallb(ic);
1773 return (0);
1774 } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
1775 strcpy(ic->parm.aux.para, "0-255");
1776 ic->command = ISDN_STAT_FAXIND;
1777 ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1778 cs->iif.statcallb(ic);
1779 return (0);
1780 } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
1781 if (cs->debug & L1_DEB_HSCX)
1782 debugl1(cs, "isar_auxcmd %s=%d",
1783 FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
1784 if (bcs->hw.isar.state == STFAX_READY) {
1785 if (!ic->parm.aux.para[0]) {
1786 ic->command = ISDN_STAT_FAXIND;
1787 ic->parm.aux.cmd = ISDN_FAX_CLASS1_OK;
1788 cs->iif.statcallb(ic);
1789 return (0);
1790 }
1791 if (!test_and_set_bit(BC_FLG_FTI_RUN, &bcs->Flag)) {
1792 /* n*10 ms */
1793 bcs->hw.isar.ftimer.expires =
1794 jiffies + ((ic->parm.aux.para[0] * 10 * HZ) / 1000);
1795 test_and_set_bit(BC_FLG_FTI_FTS, &bcs->Flag);
1796 add_timer(&bcs->hw.isar.ftimer);
1797 return (0);
1798 } else {
1799 if (cs->debug)
1800 debugl1(cs, "isar FTS=%d and FTI busy",
1801 ic->parm.aux.para[0]);
1802 }
1803 } else {
1804 if (cs->debug)
1805 debugl1(cs, "isar FTS=%d and isar.state not ready(%x)",
1806 ic->parm.aux.para[0], bcs->hw.isar.state);
1807 }
1808 ic->command = ISDN_STAT_FAXIND;
1809 ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
1810 cs->iif.statcallb(ic);
1811 }
1812 break;
1813 case ISDN_FAX_CLASS1_FRM:
1814 case ISDN_FAX_CLASS1_FRH:
1815 case ISDN_FAX_CLASS1_FTM:
1816 case ISDN_FAX_CLASS1_FTH:
1817 if (ic->parm.aux.subcmd == AT_QUERY) {
1818 sprintf(ic->parm.aux.para,
1819 "%d", bcs->hw.isar.mod);
1820 ic->command = ISDN_STAT_FAXIND;
1821 ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1822 cs->iif.statcallb(ic);
1823 return (0);
1824 } else if (ic->parm.aux.subcmd == AT_EQ_QUERY) {
1825 char *p = ic->parm.aux.para;
1826 for (i = 0; i < FAXMODCNT; i++)
1827 if ((1 << i) & modmask)
1828 p += sprintf(p, "%d,", faxmodulation[i]);
1829 p--;
1830 *p = 0;
1831 ic->command = ISDN_STAT_FAXIND;
1832 ic->parm.aux.cmd = ISDN_FAX_CLASS1_QUERY;
1833 cs->iif.statcallb(ic);
1834 return (0);
1835 } else if (ic->parm.aux.subcmd == AT_EQ_VALUE) {
1836 if (cs->debug & L1_DEB_HSCX)
1837 debugl1(cs, "isar_auxcmd %s=%d",
1838 FC1_CMD[ic->parm.aux.cmd], ic->parm.aux.para[0]);
1839 for (i = 0; i < FAXMODCNT; i++)
1840 if (faxmodulation[i] == ic->parm.aux.para[0])
1841 break;
1842 if ((i < FAXMODCNT) && ((1 << i) & modmask) &&
1843 test_bit(BC_FLG_INIT, &bcs->Flag)) {
1844 isar_pump_cmd(bcs,
1845 ic->parm.aux.cmd,
1846 ic->parm.aux.para[0]);
1847 return (0);
1848 }
1849 }
1850 /* wrong modulation or not activ */
1851 /* fall through */
1852 default:
1853 ic->command = ISDN_STAT_FAXIND;
1854 ic->parm.aux.cmd = ISDN_FAX_CLASS1_ERROR;
1855 cs->iif.statcallb(ic);
1856 }
1857 break;
1858 case (ISDN_CMD_IOCTL):
1859 switch (ic->arg) {
1860 case 9: /* load firmware */
1861 features = ISDN_FEATURE_L2_MODEM |
1862 ISDN_FEATURE_L2_FAX |
1863 ISDN_FEATURE_L3_FCLASS1;
1864 memcpy(&adr, ic->parm.num, sizeof(ulong));
1865 if (isar_load_firmware(cs, (u_char __user *)adr))
1866 return (1);
1867 else
1868 ll_run(cs, features);
1869 break;
1870 case 20:
1871 features = *(unsigned int *) ic->parm.num;
1872 printk(KERN_DEBUG "HiSax: max modulation old(%04x) new(%04x)\n",
1873 modmask, features);
1874 modmask = features;
1875 break;
1876 case 21:
1877 features = *(unsigned int *) ic->parm.num;
1878 printk(KERN_DEBUG "HiSax: FRM extra delay old(%d) new(%d) ms\n",
1879 frm_extra_delay, features);
1880 if (features >= 0)
1881 frm_extra_delay = features;
1882 break;
1883 case 22:
1884 features = *(unsigned int *) ic->parm.num;
1885 printk(KERN_DEBUG "HiSax: TOA old(%d) new(%d) db\n",
1886 para_TOA, features);
1887 if (features >= 0 && features < 32)
1888 para_TOA = features;
1889 break;
1890 default:
1891 printk(KERN_DEBUG "HiSax: invalid ioctl %d\n",
1892 (int) ic->arg);
1893 return (-EINVAL);
1894 }
1895 break;
1896 default:
1897 return (-EINVAL);
1898 }
1899 return (0);
1900 }
1901
initisar(struct IsdnCardState * cs)1902 void initisar(struct IsdnCardState *cs)
1903 {
1904 cs->bcs[0].BC_SetStack = setstack_isar;
1905 cs->bcs[1].BC_SetStack = setstack_isar;
1906 cs->bcs[0].BC_Close = close_isarstate;
1907 cs->bcs[1].BC_Close = close_isarstate;
1908 timer_setup(&cs->bcs[0].hw.isar.ftimer, ftimer_handler, 0);
1909 timer_setup(&cs->bcs[1].hw.isar.ftimer, ftimer_handler, 0);
1910 }
1911