1 /*
2  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 
17 #include <linux/io.h>
18 #include <linux/clk-provider.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/clk/tegra.h>
24 
25 #include "clk.h"
26 #include "clk-id.h"
27 
28 #define OSC_CTRL			0x50
29 #define OSC_CTRL_OSC_FREQ_SHIFT		28
30 #define OSC_CTRL_PLL_REF_DIV_SHIFT	26
31 
tegra_osc_clk_init(void __iomem * clk_base,struct tegra_clk * clks,unsigned long * input_freqs,unsigned int num,unsigned int clk_m_div,unsigned long * osc_freq,unsigned long * pll_ref_freq)32 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
33 			      unsigned long *input_freqs, unsigned int num,
34 			      unsigned int clk_m_div, unsigned long *osc_freq,
35 			      unsigned long *pll_ref_freq)
36 {
37 	struct clk *clk, *osc;
38 	struct clk **dt_clk;
39 	u32 val, pll_ref_div;
40 	unsigned osc_idx;
41 
42 	val = readl_relaxed(clk_base + OSC_CTRL);
43 	osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
44 
45 	if (osc_idx < num)
46 		*osc_freq = input_freqs[osc_idx];
47 	else
48 		*osc_freq = 0;
49 
50 	if (!*osc_freq) {
51 		WARN_ON(1);
52 		return -EINVAL;
53 	}
54 
55 	osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
56 
57 	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
58 	if (!dt_clk)
59 		return 0;
60 
61 	clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
62 					0, 1, clk_m_div);
63 	*dt_clk = clk;
64 
65 	/* pll_ref */
66 	val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
67 	pll_ref_div = 1 << val;
68 	dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
69 	if (!dt_clk)
70 		return 0;
71 
72 	clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
73 					0, 1, pll_ref_div);
74 	*dt_clk = clk;
75 
76 	if (pll_ref_freq)
77 		*pll_ref_freq = *osc_freq / pll_ref_div;
78 
79 	return 0;
80 }
81 
tegra_fixed_clk_init(struct tegra_clk * tegra_clks)82 void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
83 {
84 	struct clk *clk;
85 	struct clk **dt_clk;
86 
87 	/* clk_32k */
88 	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
89 	if (dt_clk) {
90 		clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
91 		*dt_clk = clk;
92 	}
93 
94 	/* clk_m_div2 */
95 	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
96 	if (dt_clk) {
97 		clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
98 					CLK_SET_RATE_PARENT, 1, 2);
99 		*dt_clk = clk;
100 	}
101 
102 	/* clk_m_div4 */
103 	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
104 	if (dt_clk) {
105 		clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
106 					CLK_SET_RATE_PARENT, 1, 4);
107 		*dt_clk = clk;
108 	}
109 }
110