1 /*
2 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef _DP_UMAC_RESET_H_
18 #define _DP_UMAC_RESET_H_
19
20 #include <qdf_types.h>
21 struct dp_soc;
22
23 #define DP_UMAC_RESET_NOTIFY_DONE 20
24 /**
25 * enum umac_reset_action - Actions supported by the UMAC reset
26 * @UMAC_RESET_ACTION_NONE: No action
27 * @UMAC_RESET_ACTION_DO_TRIGGER_RECOVERY: Trigger umac recovery
28 * @UMAC_RESET_ACTION_DO_PRE_RESET: DO_PRE_RESET
29 * @UMAC_RESET_ACTION_DO_POST_RESET_START: DO_POST_RESET_START
30 * @UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE: DO_POST_RESET_COMPLETE
31 * @UMAC_RESET_ACTION_ABORT: Abort the current Umac reset session
32 * @UMAC_RESET_ACTION_MAX: Maximum actions
33 */
34 enum umac_reset_action {
35 UMAC_RESET_ACTION_NONE,
36 UMAC_RESET_ACTION_DO_TRIGGER_RECOVERY,
37 UMAC_RESET_ACTION_DO_PRE_RESET,
38 UMAC_RESET_ACTION_DO_POST_RESET_START,
39 UMAC_RESET_ACTION_DO_POST_RESET_COMPLETE,
40 UMAC_RESET_ACTION_ABORT,
41 UMAC_RESET_ACTION_MAX
42 };
43
44 #ifdef DP_UMAC_HW_RESET_SUPPORT
45
46 #define dp_umac_reset_alert(params...) \
47 QDF_TRACE_FATAL(QDF_MODULE_ID_DP_UMAC_RESET, params)
48 #define dp_umac_reset_err(params...) \
49 QDF_TRACE_ERROR(QDF_MODULE_ID_DP_UMAC_RESET, params)
50 #define dp_umac_reset_warn(params...) \
51 QDF_TRACE_WARN(QDF_MODULE_ID_DP_UMAC_RESET, params)
52 #define dp_umac_reset_notice(params...) \
53 QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params)
54 #define dp_umac_reset_info(params...) \
55 QDF_TRACE_INFO(QDF_MODULE_ID_DP_UMAC_RESET, params)
56 #define dp_umac_reset_debug(params...) \
57 QDF_TRACE_DEBUG(QDF_MODULE_ID_DP_UMAC_RESET, params)
58
59 #define DP_UMAC_RESET_PRINT_STATS(fmt, args ...)\
60 QDF_TRACE(QDF_MODULE_ID_DP_UMAC_RESET, QDF_TRACE_LEVEL_FATAL,\
61 fmt, ## args)
62
63 #define DP_UMAC_RESET_SHMEM_ALIGN 8
64 #define DP_UMAC_RESET_SHMEM_MAGIC_NUM (0xDEADBEEF)
65
66 /**
67 * enum umac_reset_state - States required by the UMAC reset state machine
68 * @UMAC_RESET_STATE_WAIT_FOR_TRIGGER: Waiting for trigger event
69 * @UMAC_RESET_STATE_DO_TRIGGER_RECEIVED: Received the DO_TRIGGER event
70 * @UMAC_RESET_STATE_HOST_TRIGGER_DONE: Host completed handling Trigger event
71 * @UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET: Waiting for the DO_PRE_RESET event
72 * @UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED: Received the DO_PRE_RESET event
73 * @UMAC_RESET_STATE_HOST_PRE_RESET_DONE: Host has completed handling the
74 * PRE_RESET event
75 * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START: Waiting for the
76 * DO_POST_RESET_START event
77 * @UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED: Received the
78 * DO_POST_RESET_START event
79 * @UMAC_RESET_STATE_HOST_POST_RESET_START_DONE: Host has completed handling the
80 * POST_RESET_START event
81 * @UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE: Waiting for the
82 * DO_POST_RESET_COMPLETE event
83 * @UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED: Received the
84 * DO_POST_RESET_COMPLETE event
85 * @UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE: Host has completed handling
86 * the DO_POST_RESET_COMPLETE event
87 */
88 enum umac_reset_state {
89 UMAC_RESET_STATE_WAIT_FOR_TRIGGER = 0,
90 UMAC_RESET_STATE_DO_TRIGGER_RECEIVED,
91 UMAC_RESET_STATE_HOST_TRIGGER_DONE,
92
93 UMAC_RESET_STATE_WAIT_FOR_DO_PRE_RESET,
94 UMAC_RESET_STATE_DO_PRE_RESET_RECEIVED,
95 UMAC_RESET_STATE_HOST_PRE_RESET_DONE,
96
97 UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_START,
98 UMAC_RESET_STATE_DO_POST_RESET_START_RECEIVED,
99 UMAC_RESET_STATE_HOST_POST_RESET_START_DONE,
100
101 UMAC_RESET_STATE_WAIT_FOR_DO_POST_RESET_COMPLETE,
102 UMAC_RESET_STATE_DO_POST_RESET_COMPLETE_RECEIVED,
103 UMAC_RESET_STATE_HOST_POST_RESET_COMPLETE_DONE,
104 };
105
106 /**
107 * enum umac_reset_rx_event - Rx events deduced by the UMAC reset
108 * @UMAC_RESET_RX_EVENT_NONE: No event
109 * @UMAC_RESET_RX_EVENT_DO_TRIGGER_RECOVERY: ACTION_DO_TRIGGER_RECOVERY event
110 * @UMAC_RESET_RX_EVENT_DO_TRIGGER_TR_SYNC: ACTION_DO_TRIGGER_RECOVERY event
111 * @UMAC_RESET_RX_EVENT_DO_PRE_RESET: DO_PRE_RESET event
112 * @UMAC_RESET_RX_EVENT_DO_POST_RESET_START: DO_POST_RESET_START event
113 * @UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE: DO_POST_RESET_COMPELTE event
114 * @UMAC_RESET_RX_EVENT_ERROR: Error while processing the Rx event
115 */
116 enum umac_reset_rx_event {
117 UMAC_RESET_RX_EVENT_NONE = 0x0,
118 UMAC_RESET_RX_EVENT_DO_TRIGGER_RECOVERY,
119 UMAC_RESET_RX_EVENT_DO_TRIGGER_TR_SYNC,
120 UMAC_RESET_RX_EVENT_DO_PRE_RESET,
121 UMAC_RESET_RX_EVENT_DO_POST_RESET_START,
122 UMAC_RESET_RX_EVENT_DO_POST_RESET_COMPELTE,
123
124 UMAC_RESET_RX_EVENT_ERROR = 0xFFFFFFFF,
125 };
126
127 /**
128 * enum umac_reset_tx_cmd: UMAC reset Tx command
129 * @UMAC_RESET_TX_CMD_TRIGGER_DONE: TRIGGER_DONE
130 * @UMAC_RESET_TX_CMD_PRE_RESET_DONE: PRE_RESET_DONE
131 * @UMAC_RESET_TX_CMD_POST_RESET_START_DONE: POST_RESET_START_DONE
132 * @UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE: POST_RESET_COMPLETE_DONE
133 */
134 enum umac_reset_tx_cmd {
135 UMAC_RESET_TX_CMD_TRIGGER_DONE,
136 UMAC_RESET_TX_CMD_PRE_RESET_DONE,
137 UMAC_RESET_TX_CMD_POST_RESET_START_DONE,
138 UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE,
139 };
140
141 /**
142 * struct umac_reset_rx_actions - callbacks for handling UMAC reset actions
143 * @cb: Array of pointers where each pointer contains callback for each UMAC
144 * reset action for that index
145 */
146 struct umac_reset_rx_actions {
147 QDF_STATUS (*cb[UMAC_RESET_ACTION_MAX])(struct dp_soc *soc);
148 };
149
150 /**
151 * struct reset_ts - timestamps of for umac reset events for debug
152 * @trigger_start: Umac reset trigger event timestamp
153 * @trigger_done: Umac reset trigger done timestamp
154 * @pre_reset_start: Umac prereset start event timestamp
155 * @pre_reset_done: Umac prereset done timestamp
156 * @post_reset_start: Umac postreset start event timestamp
157 * @post_reset_done: Umac postreset done timestamp
158 * @post_reset_complete_start: Umac postreset complete event timestamp
159 * @post_reset_complete_done: Umac postreset complete done timestamp
160 */
161 struct reset_ts {
162 uint64_t trigger_start;
163 uint64_t trigger_done;
164 uint64_t pre_reset_start;
165 uint64_t pre_reset_done;
166 uint64_t post_reset_start;
167 uint64_t post_reset_done;
168 uint64_t post_reset_complete_start;
169 uint64_t post_reset_complete_done;
170 };
171
172 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)
173 /**
174 * struct dp_soc_mlo_umac_reset_ctx - UMAC reset context at mlo group level
175 * @partner_map: Partner soc map
176 * @request_map: Partner soc request map
177 * @response_map: Partner soc response map
178 * @grp_ctx_lock: lock for accessing group level umac reset context
179 * @umac_reset_in_progress: Flag to indicate if umac reset is in progress
180 * @is_target_recovery: Flag to indicate if this is for target recovery
181 * @tx_desc_pool_cleaned: Global tx_desc pool clean up has been done
182 * @initiator_chip_id: chip id of the Umac reset initiator
183 * @umac_reset_count: Number of times Umac reset happened on this MLO group
184 */
185 struct dp_soc_mlo_umac_reset_ctx {
186 unsigned long partner_map;
187 unsigned long request_map;
188 unsigned long response_map;
189 qdf_spinlock_t grp_ctx_lock;
190 uint8_t umac_reset_in_progress:1,
191 is_target_recovery:1,
192 tx_desc_pool_cleaned:1;
193 uint8_t initiator_chip_id;
194 uint32_t umac_reset_count;
195 };
196 #endif
197
198 /**
199 * struct dp_soc_umac_reset_ctx - UMAC reset context at soc level
200 * @shmem_paddr_unaligned: Physical address of the shared memory (unaligned)
201 * @shmem_vaddr_unaligned: Virtual address of the shared memory (unaligned)
202 * @shmem_paddr_aligned: Physical address of the shared memory (aligned)
203 * @shmem_vaddr_aligned: Virtual address of the shared memory (aligned)
204 * @shmem_size: Size of the shared memory
205 * @intr_offset: Offset of the UMAC reset interrupt w.r.t DP base interrupt
206 * @current_state: current state of the UMAC reset state machine
207 * @shmem_exp_magic_num: Expected magic number in the shared memory
208 * @rx_actions: callbacks for handling UMAC reset actions
209 * @pending_action: Action pending to be executed.
210 * @intr_ctx_bkp: DP Interrupts ring masks backup
211 * @nbuf_list: skb list for delayed free
212 * @skel_enable: Enable skeleton code for umac reset
213 * @ts: timestamps debug
214 */
215 struct dp_soc_umac_reset_ctx {
216 qdf_dma_addr_t shmem_paddr_unaligned;
217 void *shmem_vaddr_unaligned;
218 qdf_dma_addr_t shmem_paddr_aligned;
219 htt_umac_hang_recovery_msg_shmem_t *shmem_vaddr_aligned;
220 size_t shmem_size;
221 int intr_offset;
222 enum umac_reset_state current_state;
223 uint32_t shmem_exp_magic_num;
224 struct umac_reset_rx_actions rx_actions;
225 enum umac_reset_action pending_action;
226 struct dp_intr_bkp *intr_ctx_bkp;
227 qdf_nbuf_t nbuf_list;
228 bool skel_enable;
229 struct reset_ts ts;
230 };
231
232 /**
233 * dp_soc_umac_reset_init() - Initialize UMAC reset context
234 * @txrx_soc: DP soc object
235 *
236 * Return: QDF status of operation
237 */
238 QDF_STATUS dp_soc_umac_reset_init(struct cdp_soc_t *txrx_soc);
239
240 /**
241 * dp_soc_umac_reset_deinit() - De-initialize UMAC reset context
242 * @txrx_soc: DP soc object
243 *
244 * Return: QDF status of operation
245 */
246 QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc);
247
248 /**
249 * dp_umac_reset_interrupt_attach() - Register handlers for UMAC reset interrupt
250 * @soc: DP soc object
251 *
252 * Return: QDF status of operation
253 */
254 QDF_STATUS dp_umac_reset_interrupt_attach(struct dp_soc *soc);
255
256 /**
257 * dp_umac_reset_interrupt_detach() - Unregister UMAC reset interrupt handlers
258 * @soc: DP soc object
259 *
260 * Return: QDF status of operation
261 */
262 QDF_STATUS dp_umac_reset_interrupt_detach(struct dp_soc *soc);
263
264 /**
265 * dp_umac_reset_register_rx_action_callback() - Register a callback for a given
266 * UMAC reset action
267 * @soc: DP soc object
268 * @handler: callback handler to be registered
269 * @action: UMAC reset action for which @handler needs to be registered
270 *
271 * Return: QDF status of operation
272 */
273 QDF_STATUS dp_umac_reset_register_rx_action_callback(
274 struct dp_soc *soc,
275 QDF_STATUS (*handler)(struct dp_soc *soc),
276 enum umac_reset_action action);
277
278 /**
279 * dp_umac_reset_notify_action_completion() - Notify that a given action has
280 * been completed
281 * @soc: DP soc object
282 * @action: UMAC reset action that got completed
283 *
284 * Return: QDF status of operation
285 */
286 QDF_STATUS dp_umac_reset_notify_action_completion(
287 struct dp_soc *soc,
288 enum umac_reset_action action);
289
290 /**
291 * dp_umac_reset_post_tx_cmd_via_shmem() - Post Tx command using shared memory
292 * @soc: DP soc object
293 * @ctxt: Tx command to be posted
294 * @chip_id: Chip id of the mlo soc
295 *
296 * Return: None
297 */
298 void dp_umac_reset_post_tx_cmd_via_shmem(struct dp_soc *soc, void *ctxt,
299 int chip_id);
300
301 /**
302 * dp_check_umac_reset_in_progress() - Check if Umac reset is in progress
303 * @soc: dp soc handle
304 *
305 * Return: true if Umac reset is in progress or false otherwise
306 */
307 bool dp_check_umac_reset_in_progress(struct dp_soc *soc);
308
309 /**
310 * dp_umac_reset_stats_print - API to print UMAC reset stats
311 * @soc: dp soc handle
312 *
313 * Return: QDF_STATUS
314 */
315 QDF_STATUS dp_umac_reset_stats_print(struct dp_soc *soc);
316
317 /**
318 * dp_umac_reset_validate_n_update_state_machine_on_rx() - Validate the state
319 * machine for a given rx event and update the state machine
320 * @umac_reset_ctx: UMAC reset context
321 * @rx_event: Rx event
322 * @current_exp_state: Expected state
323 * @next_state: The state to which the state machine needs to be updated
324 *
325 * Return: QDF_STATUS of operation
326 */
327 QDF_STATUS
328 dp_umac_reset_validate_n_update_state_machine_on_rx(
329 struct dp_soc_umac_reset_ctx *umac_reset_ctx,
330 enum umac_reset_rx_event rx_event,
331 enum umac_reset_state current_exp_state,
332 enum umac_reset_state next_state);
333 #else
dp_check_umac_reset_in_progress(struct dp_soc * soc)334 static inline bool dp_check_umac_reset_in_progress(struct dp_soc *soc)
335 {
336 return false;
337 }
338
339 static inline
dp_soc_umac_reset_init(struct cdp_soc_t * txrx_soc)340 QDF_STATUS dp_soc_umac_reset_init(struct cdp_soc_t *txrx_soc)
341 {
342 return QDF_STATUS_SUCCESS;
343 }
344
345 static inline
dp_soc_umac_reset_deinit(struct cdp_soc_t * txrx_soc)346 QDF_STATUS dp_soc_umac_reset_deinit(struct cdp_soc_t *txrx_soc)
347 {
348 return QDF_STATUS_SUCCESS;
349 }
350
351 static inline
dp_umac_reset_register_rx_action_callback(struct dp_soc * soc,QDF_STATUS (* handler)(struct dp_soc * soc),enum umac_reset_action action)352 QDF_STATUS dp_umac_reset_register_rx_action_callback(
353 struct dp_soc *soc,
354 QDF_STATUS (*handler)(struct dp_soc *soc),
355 enum umac_reset_action action)
356 {
357 return QDF_STATUS_SUCCESS;
358 }
359
360 static inline
dp_umac_reset_notify_action_completion(struct dp_soc * soc,enum umac_reset_action action)361 QDF_STATUS dp_umac_reset_notify_action_completion(
362 struct dp_soc *soc,
363 enum umac_reset_action action)
364 {
365 return QDF_STATUS_SUCCESS;
366 }
367
368 static inline
dp_umac_reset_stats_print(struct dp_soc * soc)369 QDF_STATUS dp_umac_reset_stats_print(struct dp_soc *soc)
370 {
371 return QDF_STATUS_SUCCESS;
372 }
373 #endif /* DP_UMAC_HW_RESET_SUPPORT */
374 #endif /* _DP_UMAC_RESET_H_ */
375